2 FreeRTOS V7.4.2 - Copyright (C) 2013 Real Time Engineers Ltd.
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4 FEATURES AND PORTS ARE ADDED TO FREERTOS ALL THE TIME. PLEASE VISIT
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5 http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
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7 ***************************************************************************
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9 * FreeRTOS tutorial books are available in pdf and paperback. *
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10 * Complete, revised, and edited pdf reference manuals are also *
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13 * Purchasing FreeRTOS documentation will not only help you, by *
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14 * ensuring you get running as quickly as possible and with an *
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15 * in-depth knowledge of how to use FreeRTOS, it will also help *
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16 * the FreeRTOS project to continue with its mission of providing *
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17 * professional grade, cross platform, de facto standard solutions *
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18 * for microcontrollers - completely free of charge! *
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20 * >>> See http://www.FreeRTOS.org/Documentation for details. <<< *
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22 * Thank you for using FreeRTOS, and thank you for your support! *
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24 ***************************************************************************
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27 This file is part of the FreeRTOS distribution.
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29 FreeRTOS is free software; you can redistribute it and/or modify it under
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30 the terms of the GNU General Public License (version 2) as published by the
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31 Free Software Foundation AND MODIFIED BY the FreeRTOS exception.
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33 >>>>>>NOTE<<<<<< The modification to the GPL is included to allow you to
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34 distribute a combined work that includes FreeRTOS without being obliged to
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35 provide the source code for proprietary components outside of the FreeRTOS
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38 FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
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39 WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
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40 FOR A PARTICULAR PURPOSE. See the GNU General Public License for more
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41 details. You should have received a copy of the GNU General Public License
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42 and the FreeRTOS license exception along with FreeRTOS; if not it can be
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43 viewed here: http://www.freertos.org/a00114.html and also obtained by
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44 writing to Real Time Engineers Ltd., contact details for whom are available
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45 on the FreeRTOS WEB site.
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49 ***************************************************************************
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51 * Having a problem? Start by reading the FAQ "My application does *
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52 * not run, what could be wrong?" *
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54 * http://www.FreeRTOS.org/FAQHelp.html *
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56 ***************************************************************************
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59 http://www.FreeRTOS.org - Documentation, books, training, latest versions,
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60 license and Real Time Engineers Ltd. contact details.
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62 http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
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63 including FreeRTOS+Trace - an indispensable productivity tool, and our new
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64 fully thread aware and reentrant UDP/IP stack.
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66 http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High
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67 Integrity Systems, who sell the code with commercial support,
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68 indemnification and middleware, under the OpenRTOS brand.
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70 http://www.SafeRTOS.com - High Integrity Systems also provide a safety
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71 engineered and independently SIL3 certified version for use in safety and
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72 mission critical applications that require provable dependability.
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75 /* Hardware specific includes. */
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76 #include <iorx62n.h>
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77 #include "typedefine.h"
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78 #include "r_ether.h"
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81 /* FreeRTOS includes. */
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82 #include "FreeRTOS.h"
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87 #include "net/uip.h"
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89 /* The time to wait between attempts to obtain a free buffer. */
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90 #define emacBUFFER_WAIT_DELAY_ms ( 3 / portTICK_RATE_MS )
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92 /* The number of times emacBUFFER_WAIT_DELAY_ms should be waited before giving
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93 up on attempting to obtain a free buffer all together. */
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94 #define emacBUFFER_WAIT_ATTEMPTS ( 30 )
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96 /* The number of Rx descriptors. */
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97 #define emacNUM_RX_DESCRIPTORS 8
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99 /* The number of Tx descriptors. When using uIP there is not point in having
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101 #define emacNUM_TX_BUFFERS 2
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103 /* The total number of EMAC buffers to allocate. */
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104 #define emacNUM_BUFFERS ( emacNUM_RX_DESCRIPTORS + emacNUM_TX_BUFFERS )
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106 /* The time to wait for the Tx descriptor to become free. */
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107 #define emacTX_WAIT_DELAY_ms ( 10 / portTICK_RATE_MS )
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109 /* The total number of times to wait emacTX_WAIT_DELAY_ms for the Tx descriptor to
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111 #define emacTX_WAIT_ATTEMPTS ( 50 )
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113 /* Only Rx end and Tx end interrupts are used by this driver. */
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114 #define emacTX_END_INTERRUPT ( 1UL << 21UL )
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115 #define emacRX_END_INTERRUPT ( 1UL << 18UL )
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117 /*-----------------------------------------------------------*/
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119 /* The buffers and descriptors themselves. */
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120 #pragma data_alignment=32
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121 volatile ethfifo xRxDescriptors[ emacNUM_RX_DESCRIPTORS ];
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123 #pragma data_alignment=32
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124 volatile ethfifo xTxDescriptors[ emacNUM_TX_BUFFERS ];
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126 #pragma data_alignment=32
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127 char xEthernetBuffers[ emacNUM_BUFFERS ][ UIP_BUFSIZE ];
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130 /* Used to indicate which buffers are free and which are in use. If an index
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131 contains 0 then the corresponding buffer in xEthernetBuffers is free, otherwise
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132 the buffer is in use or about to be used. */
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133 static unsigned char ucBufferInUse[ emacNUM_BUFFERS ];
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135 /*-----------------------------------------------------------*/
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138 * Initialise both the Rx and Tx descriptors.
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140 static void prvInitialiseDescriptors( void );
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143 * Return a pointer to a free buffer within xEthernetBuffers.
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145 static unsigned char *prvGetNextBuffer( void );
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148 * Return a buffer to the list of free buffers.
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150 static void prvReturnBuffer( unsigned char *pucBuffer );
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153 * Examine the status of the next Rx FIFO to see if it contains new data.
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155 static unsigned long prvCheckRxFifoStatus( void );
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158 * Setup the microcontroller for communication with the PHY.
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160 static void prvResetMAC( void );
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163 * Configure the Ethernet interface peripherals.
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165 static void prvConfigureEtherCAndEDMAC( void );
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168 * Something has gone wrong with the descriptor usage. Reset all the buffers
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171 static void prvResetEverything( void );
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173 /*-----------------------------------------------------------*/
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175 /* Points to the Rx descriptor currently in use. */
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176 static volatile ethfifo *pxCurrentRxDesc = NULL;
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178 /* The buffer used by the uIP stack to both receive and send. This points to
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179 one of the Ethernet buffers when its actually in use. */
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180 unsigned char *uip_buf = NULL;
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182 /*-----------------------------------------------------------*/
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184 void vInitEmac( void )
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186 /* Software reset. */
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189 /* Set the Rx and Tx descriptors into their initial state. */
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190 prvInitialiseDescriptors();
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192 /* Set the MAC address into the ETHERC */
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193 ETHERC.MAHR = ( ( unsigned long ) configMAC_ADDR0 << 24UL ) |
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194 ( ( unsigned long ) configMAC_ADDR1 << 16UL ) |
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195 ( ( unsigned long ) configMAC_ADDR2 << 8UL ) |
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196 ( unsigned long ) configMAC_ADDR3;
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198 ETHERC.MALR.BIT.MA = ( ( unsigned long ) configMAC_ADDR4 << 8UL ) |
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199 ( unsigned long ) configMAC_ADDR5;
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201 /* Perform rest of interface hardware configuration. */
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202 prvConfigureEtherCAndEDMAC();
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204 /* Nothing received yet, so uip_buf points nowhere. */
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207 /* Initialize the PHY */
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210 /*-----------------------------------------------------------*/
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212 void vEMACWrite( void )
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216 /* Wait until the second transmission of the last packet has completed. */
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217 for( x = 0; x < emacTX_WAIT_ATTEMPTS; x++ )
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219 if( ( xTxDescriptors[ 1 ].status & ACT ) != 0 )
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221 /* Descriptor is still active. */
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222 vTaskDelay( emacTX_WAIT_DELAY_ms );
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230 /* Is the descriptor free after waiting for it? */
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231 if( ( xTxDescriptors[ 1 ].status & ACT ) != 0 )
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233 /* Something has gone wrong. */
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234 prvResetEverything();
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237 /* Setup both descriptors to transmit the frame. */
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238 xTxDescriptors[ 0 ].buf_p = ( char * ) uip_buf;
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239 xTxDescriptors[ 0 ].bufsize = uip_len;
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240 xTxDescriptors[ 1 ].buf_p = ( char * ) uip_buf;
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241 xTxDescriptors[ 1 ].bufsize = uip_len;
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243 /* uip_buf is being sent by the Tx descriptor. Allocate a new buffer
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244 for use by the stack. */
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245 uip_buf = prvGetNextBuffer();
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247 /* Clear previous settings and go. */
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248 xTxDescriptors[0].status &= ~( FP1 | FP0 );
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249 xTxDescriptors[0].status |= ( FP1 | FP0 | ACT );
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250 xTxDescriptors[1].status &= ~( FP1 | FP0 );
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251 xTxDescriptors[1].status |= ( FP1 | FP0 | ACT );
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253 EDMAC.EDTRR.LONG = 0x00000001;
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255 /*-----------------------------------------------------------*/
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257 unsigned long ulEMACRead( void )
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259 unsigned long ulBytesReceived;
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261 ulBytesReceived = prvCheckRxFifoStatus();
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263 if( ulBytesReceived > 0 )
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265 /* Mark the pxDescriptor buffer as free as uip_buf is going to be set to
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266 the buffer that contains the received data. */
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267 prvReturnBuffer( uip_buf );
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269 /* Point uip_buf to the data about ot be processed. */
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270 uip_buf = ( void * ) pxCurrentRxDesc->buf_p;
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272 /* Allocate a new buffer to the descriptor, as uip_buf is now using it's
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274 pxCurrentRxDesc->buf_p = ( char * ) prvGetNextBuffer();
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276 /* Prepare the descriptor to go again. */
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277 pxCurrentRxDesc->status &= ~( FP1 | FP0 );
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278 pxCurrentRxDesc->status |= ACT;
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280 /* Move onto the next buffer in the ring. */
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281 pxCurrentRxDesc = pxCurrentRxDesc->next;
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283 if( EDMAC.EDRRR.LONG == 0x00000000L )
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285 /* Restart Ethernet if it has stopped */
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286 EDMAC.EDRRR.LONG = 0x00000001L;
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290 return ulBytesReceived;
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292 /*-----------------------------------------------------------*/
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294 long lEMACWaitForLink( void )
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298 /* Set the link status. */
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299 switch( phy_set_autonegotiate() )
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301 /* Half duplex link */
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302 case PHY_LINK_100H:
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303 ETHERC.ECMR.BIT.DM = 0;
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304 ETHERC.ECMR.BIT.RTM = 1;
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309 ETHERC.ECMR.BIT.DM = 0;
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310 ETHERC.ECMR.BIT.RTM = 0;
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315 /* Full duplex link */
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316 case PHY_LINK_100F:
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317 ETHERC.ECMR.BIT.DM = 1;
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318 ETHERC.ECMR.BIT.RTM = 1;
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323 ETHERC.ECMR.BIT.DM = 1;
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324 ETHERC.ECMR.BIT.RTM = 0;
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333 if( lReturn == pdPASS )
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335 /* Enable receive and transmit. */
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336 ETHERC.ECMR.BIT.RE = 1;
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337 ETHERC.ECMR.BIT.TE = 1;
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339 /* Enable EDMAC receive */
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340 EDMAC.EDRRR.LONG = 0x1;
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345 /*-----------------------------------------------------------*/
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347 static void prvInitialiseDescriptors( void )
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349 volatile ethfifo *pxDescriptor;
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352 for( x = 0; x < emacNUM_BUFFERS; x++ )
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354 /* Ensure none of the buffers are shown as in use at the start. */
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355 ucBufferInUse[ x ] = pdFALSE;
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358 /* Initialise the Rx descriptors. */
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359 for( x = 0; x < emacNUM_RX_DESCRIPTORS; x++ )
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361 pxDescriptor = &( xRxDescriptors[ x ] );
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362 pxDescriptor->buf_p = &( xEthernetBuffers[ x ][ 0 ] );
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364 pxDescriptor->bufsize = UIP_BUFSIZE;
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365 pxDescriptor->size = 0;
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366 pxDescriptor->status = ACT;
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367 pxDescriptor->next = ( ethfifo * ) &xRxDescriptors[ x + 1 ];
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369 /* Mark this buffer as in use. */
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370 ucBufferInUse[ x ] = pdTRUE;
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373 /* The last descriptor points back to the start. */
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374 pxDescriptor->status |= DL;
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375 pxDescriptor->next = ( ethfifo * ) &xRxDescriptors[ 0 ];
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377 /* Initialise the Tx descriptors. */
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378 for( x = 0; x < emacNUM_TX_BUFFERS; x++ )
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380 pxDescriptor = &( xTxDescriptors[ x ] );
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382 /* A buffer is not allocated to the Tx descriptor until a send is
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383 actually required. */
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384 pxDescriptor->buf_p = NULL;
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386 pxDescriptor->bufsize = UIP_BUFSIZE;
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387 pxDescriptor->size = 0;
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388 pxDescriptor->status = 0;
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389 pxDescriptor->next = ( ethfifo * ) &xTxDescriptors[ x + 1 ];
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392 /* The last descriptor points back to the start. */
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393 pxDescriptor->status |= DL;
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394 pxDescriptor->next = ( ethfifo * ) &( xTxDescriptors[ 0 ] );
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396 /* Use the first Rx descriptor to start with. */
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397 pxCurrentRxDesc = &( xRxDescriptors[ 0 ] );
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399 /*-----------------------------------------------------------*/
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401 static unsigned char *prvGetNextBuffer( void )
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404 unsigned char *pucReturn = NULL;
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405 unsigned long ulAttempts = 0;
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407 while( pucReturn == NULL )
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409 /* Look through the buffers to find one that is not in use by
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411 for( x = 0; x < emacNUM_BUFFERS; x++ )
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413 if( ucBufferInUse[ x ] == pdFALSE )
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415 ucBufferInUse[ x ] = pdTRUE;
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416 pucReturn = ( unsigned char * ) &( xEthernetBuffers[ x ][ 0 ] );
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421 /* Was a buffer found? */
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422 if( pucReturn == NULL )
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426 if( ulAttempts >= emacBUFFER_WAIT_ATTEMPTS )
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431 /* Wait then look again. */
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432 vTaskDelay( emacBUFFER_WAIT_DELAY_ms );
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438 /*-----------------------------------------------------------*/
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440 static void prvReturnBuffer( unsigned char *pucBuffer )
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444 /* Return a buffer to the pool of free buffers. */
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445 for( ul = 0; ul < emacNUM_BUFFERS; ul++ )
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447 if( &( xEthernetBuffers[ ul ][ 0 ] ) == ( void * ) pucBuffer )
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449 ucBufferInUse[ ul ] = pdFALSE;
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454 /*-----------------------------------------------------------*/
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456 static void prvResetEverything( void )
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458 /* Temporary code just to see if this gets called. This function has not
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459 been implemented. */
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460 portDISABLE_INTERRUPTS();
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463 /*-----------------------------------------------------------*/
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465 static unsigned long prvCheckRxFifoStatus( void )
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467 unsigned long ulReturn = 0;
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469 if( ( pxCurrentRxDesc->status & ACT ) != 0 )
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471 /* Current descriptor is still active. */
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473 else if( ( pxCurrentRxDesc->status & FE ) != 0 )
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475 /* Frame error. Clear the error. */
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476 pxCurrentRxDesc->status &= ~( FP1 | FP0 | FE );
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477 pxCurrentRxDesc->status &= ~( RMAF | RRF | RTLF | RTSF | PRE | CERF );
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478 pxCurrentRxDesc->status |= ACT;
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479 pxCurrentRxDesc = pxCurrentRxDesc->next;
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481 if( EDMAC.EDRRR.LONG == 0x00000000UL )
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483 /* Restart Ethernet if it has stopped. */
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484 EDMAC.EDRRR.LONG = 0x00000001UL;
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489 /* The descriptor contains a frame. Because of the size of the buffers
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490 the frame should always be complete. */
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491 if( ( pxCurrentRxDesc->status & FP0 ) == FP0 )
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493 ulReturn = pxCurrentRxDesc->size;
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497 /* Do not expect to get here. */
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498 prvResetEverything();
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504 /*-----------------------------------------------------------*/
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506 static void prvResetMAC( void )
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508 /* Ensure the EtherC and EDMAC are enabled. */
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509 SYSTEM.MSTPCRB.BIT.MSTPB15 = 0;
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510 vTaskDelay( 100 / portTICK_RATE_MS );
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512 EDMAC.EDMR.BIT.SWR = 1;
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514 /* Crude wait for reset to complete. */
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515 vTaskDelay( 500 / portTICK_RATE_MS );
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517 /*-----------------------------------------------------------*/
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519 static void prvConfigureEtherCAndEDMAC( void )
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521 /* Initialisation code taken from Renesas example project. */
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523 /* TODO: Check bit 5 */
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524 ETHERC.ECSR.LONG = 0x00000037; /* Clear all ETHERC statuS BFR, PSRTO, LCHNG, MPD, ICD */
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526 /* Set the EDMAC interrupt priority. */
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527 _IPR( _ETHER_EINT ) = configKERNEL_INTERRUPT_PRIORITY;
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529 /* TODO: Check bit 5 */
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530 /* Enable interrupts of interest only. */
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531 EDMAC.EESIPR.LONG = emacTX_END_INTERRUPT | emacRX_END_INTERRUPT;
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532 ETHERC.RFLR.LONG = 1518; /* Ether payload is 1500+ CRC */
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533 ETHERC.IPGR.LONG = 0x00000014; /* Intergap is 96-bit time */
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536 EDMAC.EESR.LONG = 0x47FF0F9F; /* Clear all ETHERC and EDMAC status bits */
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537 #if __LITTLE_ENDIAN__ == 1
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538 EDMAC.EDMR.BIT.DE = 1;
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540 EDMAC.RDLAR = ( void * ) pxCurrentRxDesc; /* Initialaize Rx Descriptor List Address */
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541 EDMAC.TDLAR = ( void * ) &( xTxDescriptors[ 0 ] );/* Initialaize Tx Descriptor List Address */
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542 EDMAC.TRSCER.LONG = 0x00000000; /* Copy-back status is RFE & TFE only */
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543 EDMAC.TFTR.LONG = 0x00000000; /* Threshold of Tx_FIFO */
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544 EDMAC.FDR.LONG = 0x00000000; /* Transmit fifo & receive fifo is 256 bytes */
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545 EDMAC.RMCR.LONG = 0x00000003; /* Receive function is normal mode(continued) */
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546 ETHERC.ECMR.BIT.PRM = 0; /* Ensure promiscuous mode is off. */
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548 /* Enable the interrupt... */
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549 _IEN( _ETHER_EINT ) = 1;
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551 /*-----------------------------------------------------------*/
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553 #pragma vector = VECT_ETHER_EINT
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554 __interrupt void vEMAC_ISR_Handler( void )
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556 unsigned long ul = EDMAC.EESR.LONG;
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557 long lHigherPriorityTaskWoken = pdFALSE;
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558 extern xQueueHandle xEMACEventQueue;
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559 const unsigned long ulRxEvent = uipETHERNET_RX_EVENT;
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561 __enable_interrupt();
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563 /* Has a Tx end occurred? */
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564 if( ul & emacTX_END_INTERRUPT )
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566 /* Only return the buffer to the pool once both Txes have completed. */
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567 prvReturnBuffer( ( void * ) xTxDescriptors[ 0 ].buf_p );
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568 EDMAC.EESR.LONG = emacTX_END_INTERRUPT;
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571 /* Has an Rx end occurred? */
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572 if( ul & emacRX_END_INTERRUPT )
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574 /* Make sure the Ethernet task is not blocked waiting for a packet. */
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575 xQueueSendFromISR( xEMACEventQueue, &ulRxEvent, &lHigherPriorityTaskWoken );
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576 portYIELD_FROM_ISR( lHigherPriorityTaskWoken );
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577 EDMAC.EESR.LONG = emacRX_END_INTERRUPT;
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