2 FreeRTOS V7.3.0 - Copyright (C) 2012 Real Time Engineers Ltd.
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4 FEATURES AND PORTS ARE ADDED TO FREERTOS ALL THE TIME. PLEASE VISIT
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5 http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
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7 ***************************************************************************
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9 * FreeRTOS tutorial books are available in pdf and paperback. *
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10 * Complete, revised, and edited pdf reference manuals are also *
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13 * Purchasing FreeRTOS documentation will not only help you, by *
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14 * ensuring you get running as quickly as possible and with an *
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15 * in-depth knowledge of how to use FreeRTOS, it will also help *
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16 * the FreeRTOS project to continue with its mission of providing *
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17 * professional grade, cross platform, de facto standard solutions *
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18 * for microcontrollers - completely free of charge! *
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20 * >>> See http://www.FreeRTOS.org/Documentation for details. <<< *
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22 * Thank you for using FreeRTOS, and thank you for your support! *
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24 ***************************************************************************
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27 This file is part of the FreeRTOS distribution.
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29 FreeRTOS is free software; you can redistribute it and/or modify it under
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30 the terms of the GNU General Public License (version 2) as published by the
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31 Free Software Foundation AND MODIFIED BY the FreeRTOS exception.
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32 >>>NOTE<<< The modification to the GPL is included to allow you to
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33 distribute a combined work that includes FreeRTOS without being obliged to
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34 provide the source code for proprietary components outside of the FreeRTOS
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35 kernel. FreeRTOS is distributed in the hope that it will be useful, but
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36 WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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37 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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38 more details. You should have received a copy of the GNU General Public
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39 License and the FreeRTOS license exception along with FreeRTOS; if not it
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40 can be viewed here: http://www.freertos.org/a00114.html and also obtained
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41 by writing to Richard Barry, contact details for whom are available on the
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46 ***************************************************************************
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48 * Having a problem? Start by reading the FAQ "My application does *
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49 * not run, what could be wrong?" *
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51 * http://www.FreeRTOS.org/FAQHelp.html *
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53 ***************************************************************************
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56 http://www.FreeRTOS.org - Documentation, training, latest versions, license
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57 and contact details.
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59 http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
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60 including FreeRTOS+Trace - an indispensable productivity tool.
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62 Real Time Engineers ltd license FreeRTOS to High Integrity Systems, who sell
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63 the code with commercial support, indemnification, and middleware, under
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64 the OpenRTOS brand: http://www.OpenRTOS.com. High Integrity Systems also
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65 provide a safety engineered and independently SIL3 certified version under
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66 the SafeRTOS brand: http://www.SafeRTOS.com.
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69 /* Hardware specific includes. */
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70 #include "iodefine.h"
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71 #include "typedefine.h"
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72 #include "r_ether.h"
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75 /* FreeRTOS includes. */
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76 #include "FreeRTOS.h"
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81 #include "net/uip.h"
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83 /* The time to wait between attempts to obtain a free buffer. */
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84 #define emacBUFFER_WAIT_DELAY_ms ( 3 / portTICK_RATE_MS )
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86 /* The number of times emacBUFFER_WAIT_DELAY_ms should be waited before giving
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87 up on attempting to obtain a free buffer all together. */
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88 #define emacBUFFER_WAIT_ATTEMPTS ( 30 )
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90 /* The number of Rx descriptors. */
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91 #define emacNUM_RX_DESCRIPTORS 8
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93 /* The number of Tx descriptors. When using uIP there is not point in having
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95 #define emacNUM_TX_BUFFERS 2
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97 /* The total number of EMAC buffers to allocate. */
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98 #define emacNUM_BUFFERS ( emacNUM_RX_DESCRIPTORS + emacNUM_TX_BUFFERS )
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100 /* The time to wait for the Tx descriptor to become free. */
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101 #define emacTX_WAIT_DELAY_ms ( 10 / portTICK_RATE_MS )
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103 /* The total number of times to wait emacTX_WAIT_DELAY_ms for the Tx descriptor to
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105 #define emacTX_WAIT_ATTEMPTS ( 50 )
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107 /* Only Rx end and Tx end interrupts are used by this driver. */
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108 #define emacTX_END_INTERRUPT ( 1UL << 21UL )
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109 #define emacRX_END_INTERRUPT ( 1UL << 18UL )
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111 /*-----------------------------------------------------------*/
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113 /* The buffers and descriptors themselves. */
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114 #pragma section _RX_DESC
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115 volatile ethfifo xRxDescriptors[ emacNUM_RX_DESCRIPTORS ];
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116 #pragma section _TX_DESC
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117 volatile ethfifo xTxDescriptors[ emacNUM_TX_BUFFERS ];
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118 #pragma section _ETHERNET_BUFFERS
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121 unsigned long ulAlignmentVariable;
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122 char cBuffer[ emacNUM_BUFFERS ][ UIP_BUFSIZE ];
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123 } xEthernetBuffers;
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129 /* Used to indicate which buffers are free and which are in use. If an index
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130 contains 0 then the corresponding buffer in xEthernetBuffers is free, otherwise
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131 the buffer is in use or about to be used. */
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132 static unsigned char ucBufferInUse[ emacNUM_BUFFERS ];
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134 /*-----------------------------------------------------------*/
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137 * Initialise both the Rx and Tx descriptors.
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139 static void prvInitialiseDescriptors( void );
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142 * Return a pointer to a free buffer within xEthernetBuffers.
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144 static unsigned char *prvGetNextBuffer( void );
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147 * Return a buffer to the list of free buffers.
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149 static void prvReturnBuffer( unsigned char *pucBuffer );
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152 * Examine the status of the next Rx FIFO to see if it contains new data.
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154 static unsigned long prvCheckRxFifoStatus( void );
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157 * Setup the microcontroller for communication with the PHY.
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159 static void prvResetMAC( void );
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162 * Configure the Ethernet interface peripherals.
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164 static void prvConfigureEtherCAndEDMAC( void );
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167 * Something has gone wrong with the descriptor usage. Reset all the buffers
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170 static void prvResetEverything( void );
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172 /*-----------------------------------------------------------*/
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174 /* Points to the Rx descriptor currently in use. */
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175 static ethfifo *pxCurrentRxDesc = NULL;
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177 /* The buffer used by the uIP stack to both receive and send. This points to
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178 one of the Ethernet buffers when its actually in use. */
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179 unsigned char *uip_buf = NULL;
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181 /*-----------------------------------------------------------*/
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183 void vInitEmac( void )
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185 /* Software reset. */
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188 /* Set the Rx and Tx descriptors into their initial state. */
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189 prvInitialiseDescriptors();
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191 /* Set the MAC address into the ETHERC */
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192 ETHERC.MAHR = ( ( unsigned long ) configMAC_ADDR0 << 24UL ) |
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193 ( ( unsigned long ) configMAC_ADDR1 << 16UL ) |
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194 ( ( unsigned long ) configMAC_ADDR2 << 8UL ) |
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195 ( unsigned long ) configMAC_ADDR3;
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197 ETHERC.MALR.BIT.MA = ( ( unsigned long ) configMAC_ADDR4 << 8UL ) |
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198 ( unsigned long ) configMAC_ADDR5;
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200 /* Perform rest of interface hardware configuration. */
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201 prvConfigureEtherCAndEDMAC();
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203 /* Nothing received yet, so uip_buf points nowhere. */
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206 /* Initialize the PHY */
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209 /*-----------------------------------------------------------*/
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211 void vEMACWrite( void )
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215 /* Wait until the second transmission of the last packet has completed. */
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216 for( x = 0; x < emacTX_WAIT_ATTEMPTS; x++ )
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218 if( ( xTxDescriptors[ 1 ].status & ACT ) != 0 )
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220 /* Descriptor is still active. */
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221 vTaskDelay( emacTX_WAIT_DELAY_ms );
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229 /* Is the descriptor free after waiting for it? */
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230 if( ( xTxDescriptors[ 1 ].status & ACT ) != 0 )
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232 /* Something has gone wrong. */
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233 prvResetEverything();
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236 /* Setup both descriptors to transmit the frame. */
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237 xTxDescriptors[ 0 ].buf_p = ( char * ) uip_buf;
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238 xTxDescriptors[ 0 ].bufsize = uip_len;
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239 xTxDescriptors[ 1 ].buf_p = ( char * ) uip_buf;
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240 xTxDescriptors[ 1 ].bufsize = uip_len;
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242 /* uip_buf is being sent by the Tx descriptor. Allocate a new buffer
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243 for use by the stack. */
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244 uip_buf = prvGetNextBuffer();
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246 /* Clear previous settings and go. */
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247 xTxDescriptors[0].status &= ~( FP1 | FP0 );
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248 xTxDescriptors[0].status |= ( FP1 | FP0 | ACT );
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249 xTxDescriptors[1].status &= ~( FP1 | FP0 );
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250 xTxDescriptors[1].status |= ( FP1 | FP0 | ACT );
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252 EDMAC.EDTRR.LONG = 0x00000001;
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254 /*-----------------------------------------------------------*/
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256 unsigned long ulEMACRead( void )
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258 unsigned long ulBytesReceived;
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260 ulBytesReceived = prvCheckRxFifoStatus();
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262 if( ulBytesReceived > 0 )
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264 /* Mark the pxDescriptor buffer as free as uip_buf is going to be set to
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265 the buffer that contains the received data. */
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266 prvReturnBuffer( uip_buf );
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268 /* Point uip_buf to the data about ot be processed. */
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269 uip_buf = ( void * ) pxCurrentRxDesc->buf_p;
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271 /* Allocate a new buffer to the descriptor, as uip_buf is now using it's
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273 pxCurrentRxDesc->buf_p = prvGetNextBuffer();
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275 /* Prepare the descriptor to go again. */
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276 pxCurrentRxDesc->status &= ~( FP1 | FP0 );
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277 pxCurrentRxDesc->status |= ACT;
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279 /* Move onto the next buffer in the ring. */
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280 pxCurrentRxDesc = pxCurrentRxDesc->next;
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282 if( EDMAC.EDRRR.LONG == 0x00000000L )
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284 /* Restart Ethernet if it has stopped */
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285 EDMAC.EDRRR.LONG = 0x00000001L;
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289 return ulBytesReceived;
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291 /*-----------------------------------------------------------*/
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293 long lEMACWaitForLink( void )
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297 /* Set the link status. */
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298 switch( phy_set_autonegotiate() )
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300 /* Half duplex link */
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301 case PHY_LINK_100H:
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302 ETHERC.ECMR.BIT.DM = 0;
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303 ETHERC.ECMR.BIT.RTM = 1;
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308 ETHERC.ECMR.BIT.DM = 0;
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309 ETHERC.ECMR.BIT.RTM = 0;
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314 /* Full duplex link */
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315 case PHY_LINK_100F:
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316 ETHERC.ECMR.BIT.DM = 1;
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317 ETHERC.ECMR.BIT.RTM = 1;
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322 ETHERC.ECMR.BIT.DM = 1;
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323 ETHERC.ECMR.BIT.RTM = 0;
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332 if( lReturn == pdPASS )
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334 /* Enable receive and transmit. */
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335 ETHERC.ECMR.BIT.RE = 1;
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336 ETHERC.ECMR.BIT.TE = 1;
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338 /* Enable EDMAC receive */
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339 EDMAC.EDRRR.LONG = 0x1;
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344 /*-----------------------------------------------------------*/
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346 static void prvInitialiseDescriptors( void )
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348 ethfifo *pxDescriptor;
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351 for( x = 0; x < emacNUM_BUFFERS; x++ )
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353 /* Ensure none of the buffers are shown as in use at the start. */
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354 ucBufferInUse[ x ] = pdFALSE;
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357 /* Initialise the Rx descriptors. */
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358 for( x = 0; x < emacNUM_RX_DESCRIPTORS; x++ )
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360 pxDescriptor = &( xRxDescriptors[ x ] );
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361 pxDescriptor->buf_p = &( xEthernetBuffers.cBuffer[ x ][ 0 ] );
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363 pxDescriptor->bufsize = UIP_BUFSIZE;
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364 pxDescriptor->size = 0;
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365 pxDescriptor->status = ACT;
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366 pxDescriptor->next = &xRxDescriptors[ x + 1 ];
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368 /* Mark this buffer as in use. */
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369 ucBufferInUse[ x ] = pdTRUE;
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372 /* The last descriptor points back to the start. */
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373 pxDescriptor->status |= DL;
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374 pxDescriptor->next = &xRxDescriptors[ 0 ];
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376 /* Initialise the Tx descriptors. */
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377 for( x = 0; x < emacNUM_TX_BUFFERS; x++ )
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379 pxDescriptor = &( xTxDescriptors[ x ] );
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381 /* A buffer is not allocated to the Tx descriptor until a send is
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382 actually required. */
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383 pxDescriptor->buf_p = NULL;
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385 pxDescriptor->bufsize = UIP_BUFSIZE;
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386 pxDescriptor->size = 0;
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387 pxDescriptor->status = 0;
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388 pxDescriptor->next = &xTxDescriptors[ x + 1 ];
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391 /* The last descriptor points back to the start. */
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392 pxDescriptor->status |= DL;
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393 pxDescriptor->next = &( xTxDescriptors[ 0 ] );
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395 /* Use the first Rx descriptor to start with. */
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396 pxCurrentRxDesc = &( xRxDescriptors[ 0 ] );
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398 /*-----------------------------------------------------------*/
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400 static unsigned char *prvGetNextBuffer( void )
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403 unsigned char *pucReturn = NULL;
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404 unsigned long ulAttempts = 0;
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406 while( pucReturn == NULL )
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408 /* Look through the buffers to find one that is not in use by
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410 for( x = 0; x < emacNUM_BUFFERS; x++ )
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412 if( ucBufferInUse[ x ] == pdFALSE )
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414 ucBufferInUse[ x ] = pdTRUE;
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415 pucReturn = ( unsigned char * ) &( xEthernetBuffers.cBuffer[ x ][ 0 ] );
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420 /* Was a buffer found? */
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421 if( pucReturn == NULL )
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425 if( ulAttempts >= emacBUFFER_WAIT_ATTEMPTS )
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430 /* Wait then look again. */
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431 vTaskDelay( emacBUFFER_WAIT_DELAY_ms );
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437 /*-----------------------------------------------------------*/
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439 static void prvReturnBuffer( unsigned char *pucBuffer )
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443 /* Return a buffer to the pool of free buffers. */
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444 for( ul = 0; ul < emacNUM_BUFFERS; ul++ )
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446 if( &( xEthernetBuffers.cBuffer[ ul ][ 0 ] ) == ( void * ) pucBuffer )
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448 ucBufferInUse[ ul ] = pdFALSE;
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453 /*-----------------------------------------------------------*/
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455 static void prvResetEverything( void )
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457 /* Temporary code just to see if this gets called. This function has not
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458 been implemented. */
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459 portDISABLE_INTERRUPTS();
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462 /*-----------------------------------------------------------*/
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464 static unsigned long prvCheckRxFifoStatus( void )
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466 unsigned long ulReturn = 0;
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468 if( ( pxCurrentRxDesc->status & ACT ) != 0 )
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470 /* Current descriptor is still active. */
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472 else if( ( pxCurrentRxDesc->status & FE ) != 0 )
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474 /* Frame error. Clear the error. */
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475 pxCurrentRxDesc->status &= ~( FP1 | FP0 | FE );
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476 pxCurrentRxDesc->status &= ~( RMAF | RRF | RTLF | RTSF | PRE | CERF );
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477 pxCurrentRxDesc->status |= ACT;
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478 pxCurrentRxDesc = pxCurrentRxDesc->next;
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480 if( EDMAC.EDRRR.LONG == 0x00000000UL )
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482 /* Restart Ethernet if it has stopped. */
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483 EDMAC.EDRRR.LONG = 0x00000001UL;
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488 /* The descriptor contains a frame. Because of the size of the buffers
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489 the frame should always be complete. */
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490 if( ( pxCurrentRxDesc->status & FP0 ) == FP0 )
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492 ulReturn = pxCurrentRxDesc->size;
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496 /* Do not expect to get here. */
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497 prvResetEverything();
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503 /*-----------------------------------------------------------*/
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505 static void prvResetMAC( void )
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507 /* Ensure the EtherC and EDMAC are enabled. */
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508 SYSTEM.MSTPCRB.BIT.MSTPB15 = 0;
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509 vTaskDelay( 100 / portTICK_RATE_MS );
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511 EDMAC.EDMR.BIT.SWR = 1;
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513 /* Crude wait for reset to complete. */
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514 vTaskDelay( 500 / portTICK_RATE_MS );
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516 /*-----------------------------------------------------------*/
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518 static void prvConfigureEtherCAndEDMAC( void )
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520 /* Initialisation code taken from Renesas example project. */
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522 /* TODO: Check bit 5 */
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523 ETHERC.ECSR.LONG = 0x00000037; /* Clear all ETHERC statuS BFR, PSRTO, LCHNG, MPD, ICD */
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525 /* Set the EDMAC interrupt priority. */
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526 _IPR( _ETHER_EINT ) = configKERNEL_INTERRUPT_PRIORITY;
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528 /* Enable interrupts of interest only. */
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529 EDMAC.EESIPR.LONG = emacTX_END_INTERRUPT | emacRX_END_INTERRUPT;
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530 ETHERC.RFLR.LONG = 1518; /* Ether payload is 1500+ CRC */
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531 ETHERC.IPGR.LONG = 0x00000014; /* Intergap is 96-bit time */
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534 EDMAC.EESR.LONG = 0x47FF0F9F; /* Clear all ETHERC and EDMAC status bits */
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536 EDMAC.EDMR.BIT.DE = 1;
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538 EDMAC.RDLAR = ( void * ) pxCurrentRxDesc; /* Initialaize Rx Descriptor List Address */
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539 EDMAC.TDLAR = &( xTxDescriptors[ 0 ] ); /* Initialaize Tx Descriptor List Address */
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540 EDMAC.TRSCER.LONG = 0x00000000; /* Copy-back status is RFE & TFE only */
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541 EDMAC.TFTR.LONG = 0x00000000; /* Threshold of Tx_FIFO */
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542 EDMAC.FDR.LONG = 0x00000000; /* Transmit fifo & receive fifo is 256 bytes */
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543 EDMAC.RMCR.LONG = 0x00000003; /* Receive function is normal mode(continued) */
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544 ETHERC.ECMR.BIT.PRM = 0; /* Ensure promiscuous mode is off. */
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546 /* Enable the interrupt... */
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547 _IEN( _ETHER_EINT ) = 1;
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549 /*-----------------------------------------------------------*/
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551 #pragma interrupt ( vEMAC_ISR_Handler( vect = VECT_ETHER_EINT, enable ) )
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552 void vEMAC_ISR_Handler( void )
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554 unsigned long ul = EDMAC.EESR.LONG;
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555 long lHigherPriorityTaskWoken = pdFALSE;
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556 extern xQueueHandle xEMACEventQueue;
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557 const unsigned long ulRxEvent = uipETHERNET_RX_EVENT;
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559 /* Has a Tx end occurred? */
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560 if( ul & emacTX_END_INTERRUPT )
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562 /* Only return the buffer to the pool once both Txes have completed. */
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563 prvReturnBuffer( ( void * ) xTxDescriptors[ 0 ].buf_p );
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564 EDMAC.EESR.LONG = emacTX_END_INTERRUPT;
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567 /* Has an Rx end occurred? */
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568 if( ul & emacRX_END_INTERRUPT )
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570 /* Make sure the Ethernet task is not blocked waiting for a packet. */
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571 xQueueSendFromISR( xEMACEventQueue, &ulRxEvent, &lHigherPriorityTaskWoken );
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572 portYIELD_FROM_ISR( lHigherPriorityTaskWoken );
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573 EDMAC.EESR.LONG = emacRX_END_INTERRUPT;
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