1 /***********************************************************************/
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4 /* DATE :Wed, Aug 25, 2010 */
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5 /* DESCRIPTION :Vector Table */
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6 /* CPU TYPE :Other */
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8 /* This file is generated by KPIT GNU Project Generator. */
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10 /***********************************************************************/
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15 #include "inthandler.h"
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17 typedef void (*fp) (void);
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18 extern void start(void);
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19 extern void stack (void);
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20 extern void vTickISR( void );
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21 extern void vSoftwareInterruptISR( void );
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22 extern void vT0_1_ISR_Handler( void );
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23 extern void vT2_3_ISR_Handler( void );
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24 extern void vEMAC_ISR_Handler( void );
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25 extern void vTimer2_ISR_Handler( void );
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27 #define FVECT_SECT __attribute__ ((section (".fvectors")))
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29 const fp HardwareVectors[] FVECT_SECT = {
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30 //;0xffffff80 Reserved
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32 //;0xffffff84 Reserved
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34 //;0xffffff88 Reserved
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36 //;0xffffff8C Reserved
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38 //;0xffffff90 Reserved
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40 //;0xffffff94 Reserved
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42 //;0xffffff98 Reserved
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44 //;0xffffff9C Reserved
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46 //;0xffffffA0 Reserved
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48 //;0xffffffA4 Reserved
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50 //;0xffffffA8 Reserved
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52 //;0xffffffAC Reserved
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54 //;0xffffffB0 Reserved
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56 //;0xffffffB4 Reserved
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58 //;0xffffffB8 Reserved
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60 //;0xffffffBC Reserved
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62 //;0xffffffC0 Reserved
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64 //;0xffffffC4 Reserved
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66 //;0xffffffC8 Reserved
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68 //;0xffffffCC Reserved
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70 //;0xffffffd0 Exception(Supervisor Instruction)
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71 INT_Excep_SuperVisorInst,
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72 //;0xffffffd4 Reserved
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74 //;0xffffffd8 Reserved
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76 //;0xffffffdc Exception(Undefined Instruction)
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77 INT_Excep_UndefinedInst,
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78 //;0xffffffe0 Reserved
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80 //;0xffffffe4 Exception(Floating Point)
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81 INT_Excep_FloatingPoint,
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82 //;0xffffffe8 Reserved
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84 //;0xffffffec Reserved
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86 //;0xfffffff0 Reserved
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88 //;0xfffffff4 Reserved
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91 INT_NonMaskableInterrupt,
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93 //;<<VECTOR DATA START (POWER ON RESET)>>
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94 //;Power On Reset PC
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96 //;<<VECTOR DATA END (POWER ON RESET)>>
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99 #define RVECT_SECT __attribute__ ((section (".rvectors")))
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101 const fp RelocatableVectors[] RVECT_SECT = {
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135 (fp)INT_Excep_BUSERR,
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145 (fp)INT_Excep_FCU_FCUERR,
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149 (fp)INT_Excep_FCU_FRDYI,
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157 (fp)vSoftwareInterruptISR,
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158 //;0x0070 CMTU0_CMT0
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160 //;0x0074 CMTU0_CMT1
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161 (fp)INT_Excep_CMTU0_CMT1,
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162 //;0x0078 CMTU1_CMT2
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163 (fp)vTimer2_ISR_Handler,
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164 //;0x007C CMTU1_CMT3
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165 (fp)INT_Excep_CMTU1_CMT3,
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167 (fp)vEMAC_ISR_Handler,
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231 (fp)INT_Excep_IRQ0,
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233 (fp)INT_Excep_IRQ1,
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235 (fp)INT_Excep_IRQ2,
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237 (fp)INT_Excep_IRQ3,
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239 (fp)INT_Excep_IRQ4,
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241 (fp)INT_Excep_IRQ5,
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243 (fp)INT_Excep_IRQ6,
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245 (fp)INT_Excep_IRQ7,
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247 (fp)INT_Excep_IRQ8,
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249 (fp)INT_Excep_IRQ9,
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251 (fp)INT_Excep_IRQ10,
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253 (fp)INT_Excep_IRQ11,
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255 (fp)INT_Excep_IRQ12,
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257 (fp)INT_Excep_IRQ13,
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259 (fp)INT_Excep_IRQ14,
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261 (fp)INT_Excep_IRQ15,
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295 (fp)INT_Excep_WDT_WOVI,
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299 (fp)INT_Excep_AD0_ADI0,
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301 (fp)INT_Excep_AD1_ADI1,
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303 (fp)INT_Excep_AD2_ADI2,
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305 (fp)INT_Excep_AD3_ADI3,
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310 //;0x01A0 TPU0_TGI0A
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311 (fp)INT_Excep_TPU0_TGI0A,
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312 //;0x01A4 TPU0_TGI0B
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313 (fp)INT_Excep_TPU0_TGI0B,
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314 //;0x01A8 TPU0_TGI0C
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315 (fp)INT_Excep_TPU0_TGI0C,
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316 //;0x01AC TPU0_TGI0D
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317 (fp)INT_Excep_TPU0_TGI0D,
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318 //;0x01B0 TPU0_TCI0V
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319 (fp)INT_Excep_TPU0_TCI0V,
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324 //;0x01BC TPU1_TGI1A
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325 (fp)INT_Excep_TPU1_TGI1A,
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326 //;0x01C0 TPU1_TGI1B
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327 (fp)INT_Excep_TPU1_TGI1B,
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332 //;0x01CC TPU1_TCI1V
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333 (fp)INT_Excep_TPU1_TCI1V,
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334 //;0x01D0 TPU1_TCI1U
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335 (fp)INT_Excep_TPU1_TCI1U,
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336 //;0x01D4 TPU2_TGI2A
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337 (fp)INT_Excep_TPU2_TGI2A,
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338 //;0x01D8 TPU2_TGI2B
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339 (fp)INT_Excep_TPU2_TGI2B,
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342 //;0x01E0 TPU2_TCI2V
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343 (fp)INT_Excep_TPU2_TCI2V,
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344 //;0x01E4 TPU2_TCI2U
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345 (fp)INT_Excep_TPU2_TCI2U,
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346 //;0x01E8 TPU3_TGI3A
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347 (fp)INT_Excep_TPU3_TGI3A,
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348 //;0x01EC TPU3_TGI3B
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349 (fp)INT_Excep_TPU3_TGI3B,
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350 //;0x01F0 TPU3_TGI3C
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351 (fp)INT_Excep_TPU3_TGI3C,
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352 //;0x01F4 TPU3_TGI3D
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353 (fp)INT_Excep_TPU3_TGI3D,
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354 //;0x01F8 TPU3_TCI3V
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355 (fp)INT_Excep_TPU3_TCI3V,
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356 //;0x01FC TPU4_TGI4A
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357 (fp)INT_Excep_TPU4_TGI4A,
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358 //;0x0200 TPU4_TGI4B
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359 (fp)INT_Excep_TPU4_TGI4B,
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364 //;0x020C TPU4_TCI4V
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365 (fp)INT_Excep_TPU4_TCI4V,
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366 //;0x0210 TPU4_TCI4U
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367 (fp)INT_Excep_TPU4_TCI4U,
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368 //;0x0214 TPU5_TGI5A
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369 (fp)INT_Excep_TPU5_TGI5A,
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370 //;0x0218 TPU5_TGI5B
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371 (fp)INT_Excep_TPU5_TGI5B,
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374 //;0x0220 TPU5_TCI5V
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375 (fp)INT_Excep_TPU5_TCI5V,
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376 //;0x0224 TPU5_TCI5U
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377 (fp)INT_Excep_TPU5_TCI5U,
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378 //;0x0228 TPU6_TGI6A
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379 (fp)INT_Excep_TPU6_TGI6A,
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380 //;0x022C TPU6_TGI6B
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381 (fp)INT_Excep_TPU6_TGI6B,
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382 //;0x0230 TPU6_TGI6C
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383 (fp)INT_Excep_TPU6_TGI6C,
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384 //;0x0234 TPU6_TGI6D
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385 (fp)INT_Excep_TPU6_TGI6D,
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386 //;0x0238 TPU6_TCI6V
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387 (fp)INT_Excep_TPU6_TCI6V,
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392 //;0x0244 TPU7_TGI7A
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393 (fp)INT_Excep_TPU7_TGI7A,
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394 //;0x0248 TPU7_TGI7B
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395 (fp)INT_Excep_TPU7_TGI7B,
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400 //;0x0254 TPU7_TCI7V
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401 (fp)INT_Excep_TPU7_TCI7V,
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402 //;0x0258 TPU7_TCI7U
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403 (fp)INT_Excep_TPU7_TCI7U,
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404 //;0x025C TPU8_TGI8A
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405 (fp)INT_Excep_TPU8_TGI8A,
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406 //;0x0260 TPU8_TGI8B
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407 (fp)INT_Excep_TPU8_TGI8B,
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410 //;0x0268 TPU8_TCI8V
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411 (fp)INT_Excep_TPU8_TCI8V,
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412 //;0x026C TPU8_TCI8U
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413 (fp)INT_Excep_TPU8_TCI8U,
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414 //;0x0270 TPU9_TGI9A
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415 (fp)INT_Excep_TPU9_TGI9A,
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416 //;0x0274 TPU9_TGI9B
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417 (fp)INT_Excep_TPU9_TGI9B,
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418 //;0x0278 TPU9_TGI9C
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419 (fp)INT_Excep_TPU9_TGI9C,
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420 //;0x027C TPU9_TGI9D
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421 (fp)INT_Excep_TPU9_TGI9D,
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422 //;0x0280 TPU9_TCI9V
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423 (fp)INT_Excep_TPU9_TCI9V,
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424 //;0x0284 TPU10_TGI10A
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425 (fp)INT_Excep_TPU10_TGI10A,
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426 //;0x0288 TPU10_TGI10B
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427 (fp)INT_Excep_TPU10_TGI10B,
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432 //;0x0294 TPU10_TCI10V
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433 (fp)INT_Excep_TPU10_TCI10V,
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434 //;0x0298 TPU10_TCI10U
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435 (fp)INT_Excep_TPU10_TCI10U,
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436 //;0x029C TPU11_TGI11A
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437 (fp)INT_Excep_TPU11_TGI11A,
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438 //;0x02A0 TPU11_TGI11B
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439 (fp)INT_Excep_TPU11_TGI11B,
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442 //;0x02A8 TPU11_TCI11V
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443 (fp)INT_Excep_TPU11_TCI11V,
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444 //;0x02AC TPU11_TCI11U
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445 (fp)INT_Excep_TPU11_TCI11U,
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450 //;0x02B8 TMR0_CMI0A
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451 (fp)vT0_1_ISR_Handler,
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452 //;0x02BC TMR0_CMI0B
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453 (fp)INT_Excep_TMR0_CMI0B,
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454 //;0x02C0 TMR0_OV0I
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455 (fp)INT_Excep_TMR0_OV0I,
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456 //;0x02C4 TMR1_CMI1A
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457 (fp)INT_Excep_TMR1_CMI1A,
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458 //;0x02C8 TMR1_CMI1B
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459 (fp)INT_Excep_TMR1_CMI1B,
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460 //;0x02CC TMR1_OV1I
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461 (fp)INT_Excep_TMR1_OV1I,
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462 //;0x02D0 TMR2_CMI2A
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463 (fp)vT2_3_ISR_Handler,
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464 //;0x02D4 TMR2_CMI2B
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465 (fp)INT_Excep_TMR2_CMI2B,
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466 //;0x02D8 TMR2_OV2I
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467 (fp)INT_Excep_TMR2_OV2I,
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468 //;0x02DC TMR3_CMI3A
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469 (fp)INT_Excep_TMR3_CMI3A,
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470 //;0x02E0 TMR3_CMI3B
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471 (fp)INT_Excep_TMR3_CMI3B,
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472 //;0x02E4 TMR3_OV3I
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473 (fp)INT_Excep_TMR3_OV3I,
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498 //;0x0318 DMAC_DMTEND0
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499 (fp)INT_Excep_DMAC_DMTEND0,
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500 //;0x031C DMAC_DMTEND1
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501 (fp)INT_Excep_DMAC_DMTEND1,
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502 //;0x0320 DMAC_DMTEND2
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503 (fp)INT_Excep_DMAC_DMTEND2,
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504 //;0x0324 DMAC_DMTEND3
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505 (fp)INT_Excep_DMAC_DMTEND3,
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530 //;0x0358 SCI0_ERI0
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531 (fp)INT_Excep_SCI0_ERI0,
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532 //;0x035C SCI0_RXI0
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533 (fp)INT_Excep_SCI0_RXI0,
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534 //;0x0360 SCI0_TXI0
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535 (fp)INT_Excep_SCI0_TXI0,
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536 //;0x0364 SCI0_TEI0
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537 (fp)INT_Excep_SCI0_TEI0,
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538 //;0x0368 SCI1_ERI1
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539 (fp)INT_Excep_SCI1_ERI1,
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540 //;0x036C SCI1_RXI1
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541 (fp)INT_Excep_SCI1_RXI1,
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542 //;0x0370 SCI1_TXI1
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543 (fp)INT_Excep_SCI1_TXI1,
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544 //;0x0374 SCI1_TEI1
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545 (fp)INT_Excep_SCI1_TEI1,
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546 //;0x0378 SCI2_ERI2
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547 (fp)INT_Excep_SCI2_ERI2,
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548 //;0x037C SCI2_RXI2
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549 (fp)INT_Excep_SCI2_RXI2,
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550 //;0x0380 SCI2_TXI2
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551 (fp)INT_Excep_SCI2_TXI2,
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552 //;0x0384 SCI2_TEI2
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553 (fp)INT_Excep_SCI2_TEI2,
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554 //;0x0388 SCI3_ERI3
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555 (fp)INT_Excep_SCI3_ERI3,
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556 //;0x038C SCI3_RXI3
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557 (fp)INT_Excep_SCI3_RXI3,
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558 //;0x0390 SCI3_TXI3
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559 (fp)INT_Excep_SCI3_TXI3,
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560 //;0x0394 SCI3_TEI3
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561 (fp)INT_Excep_SCI3_TEI3,
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562 //;0x0398 SCI4_ERI4
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563 (fp)INT_Excep_SCI4_ERI4,
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564 //;0x039C SCI4_RXI4
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565 (fp)INT_Excep_SCI4_RXI4,
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566 //;0x03A0 SCI4_TXI4
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567 (fp)INT_Excep_SCI4_TXI4,
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568 //;0x03A4 SCI4_TEI4
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569 (fp)INT_Excep_SCI4_TEI4,
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570 //;0x03A8 SCI5_ERI5
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571 (fp)INT_Excep_SCI5_ERI5,
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572 //;0x03AC SCI5_RXI5
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573 (fp)INT_Excep_SCI5_RXI5,
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574 //;0x03B0 SCI5_TXI5
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575 (fp)INT_Excep_SCI5_TXI5,
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576 //;0x03B4 SCI5_TEI5
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577 (fp)INT_Excep_SCI5_TEI5,
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578 //;0x03B8 SCI6_ERI6
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579 (fp)INT_Excep_SCI6_ERI6,
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580 //;0x03BC SCI6_RXI6
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581 (fp)INT_Excep_SCI6_RXI6,
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582 //;0x03C0 SCI6_TXI6
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583 (fp)INT_Excep_SCI6_TXI6,
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584 //;0x03C4 SCI6_TEI6
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585 (fp)INT_Excep_SCI6_TEI6,
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594 //;0x03D8 RIIC0_EEI0
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595 (fp)INT_Excep_RIIC0_EEI0,
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596 //;0x03DC RIIC0_RXI0
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597 (fp)INT_Excep_RIIC0_RXI0,
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598 //;0x03E0 RIIC0_TXI0
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599 (fp)INT_Excep_RIIC0_TXI0,
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600 //;0x03E4 RIIC0_TEI0
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601 (fp)INT_Excep_RIIC0_TEI0,
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602 //;0x03E8 RIIC1_EEI1
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603 (fp)INT_Excep_RIIC1_EEI1,
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604 //;0x03EC RIIC1_RXI1
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605 (fp)INT_Excep_RIIC1_RXI1,
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606 //;0x03F0 RIIC1_TXI1
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607 (fp)INT_Excep_RIIC1_TXI1,
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608 //;0x03F4 RIIC1_TEI1
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609 (fp)INT_Excep_RIIC1_TEI1,
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