2 FreeRTOS V7.2.0 - Copyright (C) 2012 Real Time Engineers Ltd.
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5 ***************************************************************************
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7 * FreeRTOS tutorial books are available in pdf and paperback. *
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8 * Complete, revised, and edited pdf reference manuals are also *
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11 * Purchasing FreeRTOS documentation will not only help you, by *
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12 * ensuring you get running as quickly as possible and with an *
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13 * in-depth knowledge of how to use FreeRTOS, it will also help *
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14 * the FreeRTOS project to continue with its mission of providing *
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15 * professional grade, cross platform, de facto standard solutions *
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16 * for microcontrollers - completely free of charge! *
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18 * >>> See http://www.FreeRTOS.org/Documentation for details. <<< *
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20 * Thank you for using FreeRTOS, and thank you for your support! *
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22 ***************************************************************************
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25 This file is part of the FreeRTOS distribution.
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27 FreeRTOS is free software; you can redistribute it and/or modify it under
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28 the terms of the GNU General Public License (version 2) as published by the
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29 Free Software Foundation AND MODIFIED BY the FreeRTOS exception.
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30 >>>NOTE<<< The modification to the GPL is included to allow you to
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31 distribute a combined work that includes FreeRTOS without being obliged to
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32 provide the source code for proprietary components outside of the FreeRTOS
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33 kernel. FreeRTOS is distributed in the hope that it will be useful, but
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34 WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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35 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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36 more details. You should have received a copy of the GNU General Public
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37 License and the FreeRTOS license exception along with FreeRTOS; if not it
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38 can be viewed here: http://www.freertos.org/a00114.html and also obtained
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39 by writing to Richard Barry, contact details for whom are available on the
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44 ***************************************************************************
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46 * Having a problem? Start by reading the FAQ "My application does *
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47 * not run, what could be wrong? *
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49 * http://www.FreeRTOS.org/FAQHelp.html *
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51 ***************************************************************************
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54 http://www.FreeRTOS.org - Documentation, training, latest information,
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55 license and contact details.
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57 http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
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58 including FreeRTOS+Trace - an indispensable productivity tool.
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60 Real Time Engineers ltd license FreeRTOS to High Integrity Systems, who sell
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61 the code with commercial support, indemnification, and middleware, under
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62 the OpenRTOS brand: http://www.OpenRTOS.com. High Integrity Systems also
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63 provide a safety engineered and independently SIL3 certified version under
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64 the SafeRTOS brand: http://www.SafeRTOS.com.
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67 /* Hardware specific includes. */
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68 #include "iodefine.h"
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69 #include "typedefine.h"
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70 #include "r_ether.h"
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73 /* FreeRTOS includes. */
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74 #include "FreeRTOS.h"
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79 #include "net/uip.h"
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81 /* The time to wait between attempts to obtain a free buffer. */
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82 #define emacBUFFER_WAIT_DELAY_ms ( 3 / portTICK_RATE_MS )
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84 /* The number of times emacBUFFER_WAIT_DELAY_ms should be waited before giving
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85 up on attempting to obtain a free buffer all together. */
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86 #define emacBUFFER_WAIT_ATTEMPTS ( 30 )
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88 /* The number of Rx descriptors. */
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89 #define emacNUM_RX_DESCRIPTORS 8
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91 /* The number of Tx descriptors. When using uIP there is not point in having
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93 #define emacNUM_TX_BUFFERS 2
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95 /* The total number of EMAC buffers to allocate. */
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96 #define emacNUM_BUFFERS ( emacNUM_RX_DESCRIPTORS + emacNUM_TX_BUFFERS )
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98 /* The time to wait for the Tx descriptor to become free. */
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99 #define emacTX_WAIT_DELAY_ms ( 10 / portTICK_RATE_MS )
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101 /* The total number of times to wait emacTX_WAIT_DELAY_ms for the Tx descriptor to
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103 #define emacTX_WAIT_ATTEMPTS ( 50 )
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105 /* Only Rx end and Tx end interrupts are used by this driver. */
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106 #define emacTX_END_INTERRUPT ( 1UL << 21UL )
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107 #define emacRX_END_INTERRUPT ( 1UL << 18UL )
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109 /*-----------------------------------------------------------*/
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111 /* The buffers and descriptors themselves. */
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112 static volatile ethfifo xRxDescriptors[ emacNUM_RX_DESCRIPTORS ] __attribute__((aligned(16)));
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113 static volatile ethfifo xTxDescriptors[ emacNUM_TX_BUFFERS ] __attribute__((aligned(16)));
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114 static char xEthernetBuffers[ emacNUM_BUFFERS ][ UIP_BUFSIZE ] __attribute__((aligned(16)));
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116 /* Used to indicate which buffers are free and which are in use. If an index
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117 contains 0 then the corresponding buffer in xEthernetBuffers is free, otherwise
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118 the buffer is in use or about to be used. */
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119 static unsigned char ucBufferInUse[ emacNUM_BUFFERS ];
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121 /*-----------------------------------------------------------*/
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124 * Initialise both the Rx and Tx descriptors.
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126 static void prvInitialiseDescriptors( void );
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129 * Return a pointer to a free buffer within xEthernetBuffers.
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131 static unsigned char *prvGetNextBuffer( void );
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134 * Return a buffer to the list of free buffers.
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136 static void prvReturnBuffer( unsigned char *pucBuffer );
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139 * Examine the status of the next Rx FIFO to see if it contains new data.
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141 static unsigned long prvCheckRxFifoStatus( void );
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144 * Setup the microcontroller for communication with the PHY.
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146 static void prvResetMAC( void );
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149 * Configure the Ethernet interface peripherals.
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151 static void prvConfigureEtherCAndEDMAC( void );
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154 * Something has gone wrong with the descriptor usage. Reset all the buffers
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157 static void prvResetEverything( void );
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160 * Handler for the EMAC peripheral. See the documentation for this
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161 * port on http://www.FreeRTOS.org for more information on defining interrupt
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164 void vEMAC_ISR_Handler( void ) __attribute__((interrupt));
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166 /*-----------------------------------------------------------*/
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168 /* Points to the Rx descriptor currently in use. */
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169 static ethfifo *pxCurrentRxDesc = NULL;
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171 /* The buffer used by the uIP stack to both receive and send. This points to
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172 one of the Ethernet buffers when its actually in use. */
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173 unsigned char *uip_buf = NULL;
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175 /*-----------------------------------------------------------*/
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177 void vInitEmac( void )
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179 /* Software reset. */
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182 /* Set the Rx and Tx descriptors into their initial state. */
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183 prvInitialiseDescriptors();
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185 /* Set the MAC address into the ETHERC */
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186 ETHERC.MAHR = ( ( unsigned long ) configMAC_ADDR0 << 24UL ) |
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187 ( ( unsigned long ) configMAC_ADDR1 << 16UL ) |
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188 ( ( unsigned long ) configMAC_ADDR2 << 8UL ) |
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189 ( unsigned long ) configMAC_ADDR3;
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191 ETHERC.MALR.BIT.MA = ( ( unsigned long ) configMAC_ADDR4 << 8UL ) |
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192 ( unsigned long ) configMAC_ADDR5;
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194 /* Perform rest of interface hardware configuration. */
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195 prvConfigureEtherCAndEDMAC();
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197 /* Nothing received yet, so uip_buf points nowhere. */
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200 /* Initialize the PHY */
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203 /*-----------------------------------------------------------*/
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205 void vEMACWrite( void )
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209 /* Wait until the second transmission of the last packet has completed. */
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210 for( x = 0; x < emacTX_WAIT_ATTEMPTS; x++ )
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212 if( ( xTxDescriptors[ 1 ].status & ACT ) != 0 )
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214 /* Descriptor is still active. */
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215 vTaskDelay( emacTX_WAIT_DELAY_ms );
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223 /* Is the descriptor free after waiting for it? */
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224 if( ( xTxDescriptors[ 1 ].status & ACT ) != 0 )
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226 /* Something has gone wrong. */
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227 prvResetEverything();
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230 /* Setup both descriptors to transmit the frame. */
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231 xTxDescriptors[ 0 ].buf_p = ( char * ) uip_buf;
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232 xTxDescriptors[ 0 ].bufsize = uip_len;
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233 xTxDescriptors[ 1 ].buf_p = ( char * ) uip_buf;
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234 xTxDescriptors[ 1 ].bufsize = uip_len;
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236 /* uip_buf is being sent by the Tx descriptor. Allocate a new buffer
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237 for use by the stack. */
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238 uip_buf = prvGetNextBuffer();
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240 /* Clear previous settings and go. */
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241 xTxDescriptors[0].status &= ~( FP1 | FP0 );
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242 xTxDescriptors[0].status |= ( FP1 | FP0 | ACT );
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243 xTxDescriptors[1].status &= ~( FP1 | FP0 );
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244 xTxDescriptors[1].status |= ( FP1 | FP0 | ACT );
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246 EDMAC.EDTRR.LONG = 0x00000001;
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248 /*-----------------------------------------------------------*/
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250 unsigned long ulEMACRead( void )
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252 unsigned long ulBytesReceived;
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254 ulBytesReceived = prvCheckRxFifoStatus();
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256 if( ulBytesReceived > 0 )
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258 /* Mark the pxDescriptor buffer as free as uip_buf is going to be set to
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259 the buffer that contains the received data. */
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260 prvReturnBuffer( uip_buf );
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262 /* Point uip_buf to the data about ot be processed. */
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263 uip_buf = ( void * ) pxCurrentRxDesc->buf_p;
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265 /* Allocate a new buffer to the descriptor, as uip_buf is now using it's
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267 pxCurrentRxDesc->buf_p = ( char * ) prvGetNextBuffer();
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269 /* Prepare the descriptor to go again. */
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270 pxCurrentRxDesc->status &= ~( FP1 | FP0 );
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271 pxCurrentRxDesc->status |= ACT;
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273 /* Move onto the next buffer in the ring. */
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274 pxCurrentRxDesc = pxCurrentRxDesc->next;
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276 if( EDMAC.EDRRR.LONG == 0x00000000L )
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278 /* Restart Ethernet if it has stopped */
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279 EDMAC.EDRRR.LONG = 0x00000001L;
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283 return ulBytesReceived;
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285 /*-----------------------------------------------------------*/
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287 long lEMACWaitForLink( void )
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291 /* Set the link status. */
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292 switch( phy_set_autonegotiate() )
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294 /* Half duplex link */
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295 case PHY_LINK_100H:
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296 ETHERC.ECMR.BIT.DM = 0;
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297 ETHERC.ECMR.BIT.RTM = 1;
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302 ETHERC.ECMR.BIT.DM = 0;
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303 ETHERC.ECMR.BIT.RTM = 0;
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308 /* Full duplex link */
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309 case PHY_LINK_100F:
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310 ETHERC.ECMR.BIT.DM = 1;
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311 ETHERC.ECMR.BIT.RTM = 1;
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316 ETHERC.ECMR.BIT.DM = 1;
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317 ETHERC.ECMR.BIT.RTM = 0;
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326 if( lReturn == pdPASS )
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328 /* Enable receive and transmit. */
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329 ETHERC.ECMR.BIT.RE = 1;
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330 ETHERC.ECMR.BIT.TE = 1;
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332 /* Enable EDMAC receive */
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333 EDMAC.EDRRR.LONG = 0x1;
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338 /*-----------------------------------------------------------*/
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340 static void prvInitialiseDescriptors( void )
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342 volatile ethfifo *pxDescriptor;
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345 for( x = 0; x < emacNUM_BUFFERS; x++ )
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347 /* Ensure none of the buffers are shown as in use at the start. */
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348 ucBufferInUse[ x ] = pdFALSE;
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351 /* Initialise the Rx descriptors. */
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352 for( x = 0; x < emacNUM_RX_DESCRIPTORS; x++ )
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354 pxDescriptor = &( xRxDescriptors[ x ] );
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355 pxDescriptor->buf_p = &( xEthernetBuffers[ x ][ 0 ] );
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357 pxDescriptor->bufsize = UIP_BUFSIZE;
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358 pxDescriptor->size = 0;
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359 pxDescriptor->status = ACT;
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360 pxDescriptor->next = ( struct Descriptor * ) &xRxDescriptors[ x + 1 ];
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362 /* Mark this buffer as in use. */
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363 ucBufferInUse[ x ] = pdTRUE;
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366 /* The last descriptor points back to the start. */
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367 pxDescriptor->status |= DL;
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368 pxDescriptor->next = ( struct Descriptor * ) &xRxDescriptors[ 0 ];
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370 /* Initialise the Tx descriptors. */
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371 for( x = 0; x < emacNUM_TX_BUFFERS; x++ )
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373 pxDescriptor = &( xTxDescriptors[ x ] );
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375 /* A buffer is not allocated to the Tx descriptor until a send is
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376 actually required. */
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377 pxDescriptor->buf_p = NULL;
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379 pxDescriptor->bufsize = UIP_BUFSIZE;
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380 pxDescriptor->size = 0;
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381 pxDescriptor->status = 0;
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382 pxDescriptor->next = ( struct Descriptor * ) &xTxDescriptors[ x + 1 ];
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385 /* The last descriptor points back to the start. */
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386 pxDescriptor->status |= DL;
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387 pxDescriptor->next = ( struct Descriptor * ) &( xTxDescriptors[ 0 ] );
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389 /* Use the first Rx descriptor to start with. */
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390 pxCurrentRxDesc = ( struct Descriptor * ) &( xRxDescriptors[ 0 ] );
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392 /*-----------------------------------------------------------*/
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394 static unsigned char *prvGetNextBuffer( void )
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397 unsigned char *pucReturn = NULL;
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398 unsigned long ulAttempts = 0;
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400 while( pucReturn == NULL )
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402 /* Look through the buffers to find one that is not in use by
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404 for( x = 0; x < emacNUM_BUFFERS; x++ )
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406 if( ucBufferInUse[ x ] == pdFALSE )
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408 ucBufferInUse[ x ] = pdTRUE;
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409 pucReturn = ( unsigned char * ) &( xEthernetBuffers[ x ][ 0 ] );
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414 /* Was a buffer found? */
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415 if( pucReturn == NULL )
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419 if( ulAttempts >= emacBUFFER_WAIT_ATTEMPTS )
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424 /* Wait then look again. */
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425 vTaskDelay( emacBUFFER_WAIT_DELAY_ms );
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431 /*-----------------------------------------------------------*/
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433 static void prvReturnBuffer( unsigned char *pucBuffer )
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437 /* Return a buffer to the pool of free buffers. */
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438 for( ul = 0; ul < emacNUM_BUFFERS; ul++ )
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440 if( &( xEthernetBuffers[ ul ][ 0 ] ) == ( void * ) pucBuffer )
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442 ucBufferInUse[ ul ] = pdFALSE;
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447 /*-----------------------------------------------------------*/
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449 static void prvResetEverything( void )
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451 /* Temporary code just to see if this gets called. This function has not
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452 been implemented. */
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453 portDISABLE_INTERRUPTS();
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456 /*-----------------------------------------------------------*/
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458 static unsigned long prvCheckRxFifoStatus( void )
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460 unsigned long ulReturn = 0;
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462 if( ( pxCurrentRxDesc->status & ACT ) != 0 )
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464 /* Current descriptor is still active. */
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466 else if( ( pxCurrentRxDesc->status & FE ) != 0 )
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468 /* Frame error. Clear the error. */
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469 pxCurrentRxDesc->status &= ~( FP1 | FP0 | FE );
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470 pxCurrentRxDesc->status &= ~( RMAF | RRF | RTLF | RTSF | PRE | CERF );
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471 pxCurrentRxDesc->status |= ACT;
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472 pxCurrentRxDesc = pxCurrentRxDesc->next;
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474 if( EDMAC.EDRRR.LONG == 0x00000000UL )
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476 /* Restart Ethernet if it has stopped. */
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477 EDMAC.EDRRR.LONG = 0x00000001UL;
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482 /* The descriptor contains a frame. Because of the size of the buffers
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483 the frame should always be complete. */
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484 if( ( pxCurrentRxDesc->status & FP0 ) == FP0 )
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486 ulReturn = pxCurrentRxDesc->size;
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490 /* Do not expect to get here. */
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491 prvResetEverything();
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497 /*-----------------------------------------------------------*/
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499 static void prvResetMAC( void )
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501 /* Ensure the EtherC and EDMAC are enabled. */
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502 SYSTEM.MSTPCRB.BIT.MSTPB15 = 0;
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503 vTaskDelay( 100 / portTICK_RATE_MS );
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505 EDMAC.EDMR.BIT.SWR = 1;
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507 /* Crude wait for reset to complete. */
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508 vTaskDelay( 500 / portTICK_RATE_MS );
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510 /*-----------------------------------------------------------*/
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512 static void prvConfigureEtherCAndEDMAC( void )
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514 /* Initialisation code taken from Renesas example project. */
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516 /* TODO: Check bit 5 */
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517 ETHERC.ECSR.LONG = 0x00000037; /* Clear all ETHERC statuS BFR, PSRTO, LCHNG, MPD, ICD */
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519 /* Set the EDMAC interrupt priority. */
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520 _IPR( _ETHER_EINT ) = configKERNEL_INTERRUPT_PRIORITY;
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522 /* TODO: Check bit 5 */
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523 /* Enable interrupts of interest only. */
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524 EDMAC.EESIPR.LONG = emacTX_END_INTERRUPT | emacRX_END_INTERRUPT;
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525 ETHERC.RFLR.LONG = 1518; /* Ether payload is 1500+ CRC */
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526 ETHERC.IPGR.LONG = 0x00000014; /* Intergap is 96-bit time */
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529 EDMAC.EESR.LONG = 0x47FF0F9F; /* Clear all ETHERC and EDMAC status bits */
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530 #ifdef __RX_LITTLE_ENDIAN__
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531 EDMAC.EDMR.BIT.DE = 1;
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533 EDMAC.RDLAR = ( void * ) pxCurrentRxDesc; /* Initialaize Rx Descriptor List Address */
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534 EDMAC.TDLAR = ( void * ) &( xTxDescriptors[ 0 ] ); /* Initialaize Tx Descriptor List Address */
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535 EDMAC.TRSCER.LONG = 0x00000000; /* Copy-back status is RFE & TFE only */
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536 EDMAC.TFTR.LONG = 0x00000000; /* Threshold of Tx_FIFO */
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537 EDMAC.FDR.LONG = 0x00000000; /* Transmit fifo & receive fifo is 256 bytes */
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538 EDMAC.RMCR.LONG = 0x00000003; /* Receive function is normal mode(continued) */
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539 ETHERC.ECMR.BIT.PRM = 0; /* Ensure promiscuous mode is off. */
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541 /* Enable the interrupt... */
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542 _IEN( _ETHER_EINT ) = 1;
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544 /*-----------------------------------------------------------*/
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546 void vEMAC_ISR_Handler( void )
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548 unsigned long ul = EDMAC.EESR.LONG;
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549 long lHigherPriorityTaskWoken = pdFALSE;
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550 extern xQueueHandle xEMACEventQueue;
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551 const unsigned long ulRxEvent = uipETHERNET_RX_EVENT;
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553 /* Re-enabled interrupts. */
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554 __asm volatile( "SETPSW I" );
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556 /* Has a Tx end occurred? */
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557 if( ul & emacTX_END_INTERRUPT )
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559 /* Only return the buffer to the pool once both Txes have completed. */
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560 prvReturnBuffer( ( void * ) xTxDescriptors[ 0 ].buf_p );
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561 EDMAC.EESR.LONG = emacTX_END_INTERRUPT;
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564 /* Has an Rx end occurred? */
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565 if( ul & emacRX_END_INTERRUPT )
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567 /* Make sure the Ethernet task is not blocked waiting for a packet. */
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568 xQueueSendFromISR( xEMACEventQueue, &ulRxEvent, &lHigherPriorityTaskWoken );
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569 portYIELD_FROM_ISR( lHigherPriorityTaskWoken );
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570 EDMAC.EESR.LONG = emacRX_END_INTERRUPT;
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