2 FreeRTOS V9.0.0 - Copyright (C) 2016 Real Time Engineers Ltd.
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5 VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
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7 This file is part of the FreeRTOS distribution.
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9 FreeRTOS is free software; you can redistribute it and/or modify it under
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10 the terms of the GNU General Public License (version 2) as published by the
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11 Free Software Foundation >>>> AND MODIFIED BY <<<< the FreeRTOS exception.
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13 ***************************************************************************
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14 >>! NOTE: The modification to the GPL is included to allow you to !<<
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15 >>! distribute a combined work that includes FreeRTOS without being !<<
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16 >>! obliged to provide the source code for proprietary components !<<
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17 >>! outside of the FreeRTOS kernel. !<<
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18 ***************************************************************************
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20 FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
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21 WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
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22 FOR A PARTICULAR PURPOSE. Full license text is available on the following
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23 link: http://www.freertos.org/a00114.html
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25 ***************************************************************************
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27 * FreeRTOS provides completely free yet professionally developed, *
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28 * robust, strictly quality controlled, supported, and cross *
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29 * platform software that is more than just the market leader, it *
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30 * is the industry's de facto standard. *
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32 * Help yourself get started quickly while simultaneously helping *
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33 * to support the FreeRTOS project by purchasing a FreeRTOS *
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34 * tutorial book, reference manual, or both: *
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35 * http://www.FreeRTOS.org/Documentation *
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37 ***************************************************************************
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39 http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading
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40 the FAQ page "My application does not run, what could be wrong?". Have you
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41 defined configASSERT()?
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43 http://www.FreeRTOS.org/support - In return for receiving this top quality
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44 embedded software for free we request you assist our global community by
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45 participating in the support forum.
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47 http://www.FreeRTOS.org/training - Investing in training allows your team to
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48 be as productive as possible as early as possible. Now you can receive
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49 FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers
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50 Ltd, and the world's leading authority on the world's leading RTOS.
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52 http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
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53 including FreeRTOS+Trace - an indispensable productivity tool, a DOS
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54 compatible FAT file system, and our tiny thread aware UDP/IP stack.
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56 http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.
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57 Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.
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59 http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High
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60 Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS
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61 licenses offer ticketed support, indemnification and commercial middleware.
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63 http://www.SafeRTOS.com - High Integrity Systems also provide a safety
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64 engineered and independently SIL3 certified version for use in safety and
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65 mission critical applications that require provable dependability.
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70 /* Hardware specific includes. */
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71 #include "iodefine.h"
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72 #include "typedefine.h"
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73 #include "r_ether.h"
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76 /* FreeRTOS includes. */
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77 #include "FreeRTOS.h"
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82 #include "net/uip.h"
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84 /* The time to wait between attempts to obtain a free buffer. */
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85 #define emacBUFFER_WAIT_DELAY_ms ( 3 / portTICK_PERIOD_MS )
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87 /* The number of times emacBUFFER_WAIT_DELAY_ms should be waited before giving
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88 up on attempting to obtain a free buffer all together. */
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89 #define emacBUFFER_WAIT_ATTEMPTS ( 30 )
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91 /* The number of Rx descriptors. */
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92 #define emacNUM_RX_DESCRIPTORS 8
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94 /* The number of Tx descriptors. When using uIP there is not point in having
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96 #define emacNUM_TX_BUFFERS 2
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98 /* The total number of EMAC buffers to allocate. */
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99 #define emacNUM_BUFFERS ( emacNUM_RX_DESCRIPTORS + emacNUM_TX_BUFFERS )
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101 /* The time to wait for the Tx descriptor to become free. */
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102 #define emacTX_WAIT_DELAY_ms ( 10 / portTICK_PERIOD_MS )
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104 /* The total number of times to wait emacTX_WAIT_DELAY_ms for the Tx descriptor to
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106 #define emacTX_WAIT_ATTEMPTS ( 50 )
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108 /* Only Rx end and Tx end interrupts are used by this driver. */
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109 #define emacTX_END_INTERRUPT ( 1UL << 21UL )
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110 #define emacRX_END_INTERRUPT ( 1UL << 18UL )
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112 /*-----------------------------------------------------------*/
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114 /* The buffers and descriptors themselves. */
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115 static volatile ethfifo xRxDescriptors[ emacNUM_RX_DESCRIPTORS ] __attribute__((aligned(16)));
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116 static volatile ethfifo xTxDescriptors[ emacNUM_TX_BUFFERS ] __attribute__((aligned(16)));
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117 static char xEthernetBuffers[ emacNUM_BUFFERS ][ UIP_BUFSIZE ] __attribute__((aligned(16)));
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119 /* Used to indicate which buffers are free and which are in use. If an index
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120 contains 0 then the corresponding buffer in xEthernetBuffers is free, otherwise
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121 the buffer is in use or about to be used. */
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122 static unsigned char ucBufferInUse[ emacNUM_BUFFERS ];
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124 /*-----------------------------------------------------------*/
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127 * Initialise both the Rx and Tx descriptors.
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129 static void prvInitialiseDescriptors( void );
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132 * Return a pointer to a free buffer within xEthernetBuffers.
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134 static unsigned char *prvGetNextBuffer( void );
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137 * Return a buffer to the list of free buffers.
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139 static void prvReturnBuffer( unsigned char *pucBuffer );
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142 * Examine the status of the next Rx FIFO to see if it contains new data.
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144 static unsigned long prvCheckRxFifoStatus( void );
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147 * Setup the microcontroller for communication with the PHY.
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149 static void prvResetMAC( void );
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152 * Configure the Ethernet interface peripherals.
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154 static void prvConfigureEtherCAndEDMAC( void );
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157 * Something has gone wrong with the descriptor usage. Reset all the buffers
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160 static void prvResetEverything( void );
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163 * Handler for the EMAC peripheral. See the documentation for this
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164 * port on http://www.FreeRTOS.org for more information on defining interrupt
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167 void vEMAC_ISR_Handler( void ) __attribute__((interrupt));
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169 /*-----------------------------------------------------------*/
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171 /* Points to the Rx descriptor currently in use. */
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172 static ethfifo *pxCurrentRxDesc = NULL;
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174 /* The buffer used by the uIP stack to both receive and send. This points to
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175 one of the Ethernet buffers when its actually in use. */
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176 unsigned char *uip_buf = NULL;
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178 /*-----------------------------------------------------------*/
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180 void vInitEmac( void )
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182 /* Software reset. */
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185 /* Set the Rx and Tx descriptors into their initial state. */
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186 prvInitialiseDescriptors();
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188 /* Set the MAC address into the ETHERC */
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189 ETHERC.MAHR = ( ( unsigned long ) configMAC_ADDR0 << 24UL ) |
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190 ( ( unsigned long ) configMAC_ADDR1 << 16UL ) |
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191 ( ( unsigned long ) configMAC_ADDR2 << 8UL ) |
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192 ( unsigned long ) configMAC_ADDR3;
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194 ETHERC.MALR.BIT.MA = ( ( unsigned long ) configMAC_ADDR4 << 8UL ) |
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195 ( unsigned long ) configMAC_ADDR5;
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197 /* Perform rest of interface hardware configuration. */
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198 prvConfigureEtherCAndEDMAC();
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200 /* Nothing received yet, so uip_buf points nowhere. */
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203 /* Initialize the PHY */
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206 /*-----------------------------------------------------------*/
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208 void vEMACWrite( void )
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212 /* Wait until the second transmission of the last packet has completed. */
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213 for( x = 0; x < emacTX_WAIT_ATTEMPTS; x++ )
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215 if( ( xTxDescriptors[ 1 ].status & ACT ) != 0 )
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217 /* Descriptor is still active. */
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218 vTaskDelay( emacTX_WAIT_DELAY_ms );
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226 /* Is the descriptor free after waiting for it? */
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227 if( ( xTxDescriptors[ 1 ].status & ACT ) != 0 )
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229 /* Something has gone wrong. */
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230 prvResetEverything();
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233 /* Setup both descriptors to transmit the frame. */
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234 xTxDescriptors[ 0 ].buf_p = ( char * ) uip_buf;
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235 xTxDescriptors[ 0 ].bufsize = uip_len;
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236 xTxDescriptors[ 1 ].buf_p = ( char * ) uip_buf;
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237 xTxDescriptors[ 1 ].bufsize = uip_len;
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239 /* uip_buf is being sent by the Tx descriptor. Allocate a new buffer
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240 for use by the stack. */
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241 uip_buf = prvGetNextBuffer();
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243 /* Clear previous settings and go. */
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244 xTxDescriptors[0].status &= ~( FP1 | FP0 );
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245 xTxDescriptors[0].status |= ( FP1 | FP0 | ACT );
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246 xTxDescriptors[1].status &= ~( FP1 | FP0 );
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247 xTxDescriptors[1].status |= ( FP1 | FP0 | ACT );
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249 EDMAC.EDTRR.LONG = 0x00000001;
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251 /*-----------------------------------------------------------*/
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253 unsigned long ulEMACRead( void )
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255 unsigned long ulBytesReceived;
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257 ulBytesReceived = prvCheckRxFifoStatus();
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259 if( ulBytesReceived > 0 )
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261 /* Mark the pxDescriptor buffer as free as uip_buf is going to be set to
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262 the buffer that contains the received data. */
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263 prvReturnBuffer( uip_buf );
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265 /* Point uip_buf to the data about ot be processed. */
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266 uip_buf = ( void * ) pxCurrentRxDesc->buf_p;
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268 /* Allocate a new buffer to the descriptor, as uip_buf is now using it's
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270 pxCurrentRxDesc->buf_p = ( char * ) prvGetNextBuffer();
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272 /* Prepare the descriptor to go again. */
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273 pxCurrentRxDesc->status &= ~( FP1 | FP0 );
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274 pxCurrentRxDesc->status |= ACT;
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276 /* Move onto the next buffer in the ring. */
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277 pxCurrentRxDesc = pxCurrentRxDesc->next;
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279 if( EDMAC.EDRRR.LONG == 0x00000000L )
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281 /* Restart Ethernet if it has stopped */
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282 EDMAC.EDRRR.LONG = 0x00000001L;
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286 return ulBytesReceived;
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288 /*-----------------------------------------------------------*/
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290 long lEMACWaitForLink( void )
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294 /* Set the link status. */
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295 switch( phy_set_autonegotiate() )
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297 /* Half duplex link */
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298 case PHY_LINK_100H:
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299 ETHERC.ECMR.BIT.DM = 0;
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300 ETHERC.ECMR.BIT.RTM = 1;
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305 ETHERC.ECMR.BIT.DM = 0;
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306 ETHERC.ECMR.BIT.RTM = 0;
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311 /* Full duplex link */
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312 case PHY_LINK_100F:
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313 ETHERC.ECMR.BIT.DM = 1;
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314 ETHERC.ECMR.BIT.RTM = 1;
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319 ETHERC.ECMR.BIT.DM = 1;
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320 ETHERC.ECMR.BIT.RTM = 0;
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329 if( lReturn == pdPASS )
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331 /* Enable receive and transmit. */
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332 ETHERC.ECMR.BIT.RE = 1;
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333 ETHERC.ECMR.BIT.TE = 1;
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335 /* Enable EDMAC receive */
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336 EDMAC.EDRRR.LONG = 0x1;
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341 /*-----------------------------------------------------------*/
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343 static void prvInitialiseDescriptors( void )
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345 volatile ethfifo *pxDescriptor;
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348 for( x = 0; x < emacNUM_BUFFERS; x++ )
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350 /* Ensure none of the buffers are shown as in use at the start. */
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351 ucBufferInUse[ x ] = pdFALSE;
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354 /* Initialise the Rx descriptors. */
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355 for( x = 0; x < emacNUM_RX_DESCRIPTORS; x++ )
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357 pxDescriptor = &( xRxDescriptors[ x ] );
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358 pxDescriptor->buf_p = &( xEthernetBuffers[ x ][ 0 ] );
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360 pxDescriptor->bufsize = UIP_BUFSIZE;
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361 pxDescriptor->size = 0;
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362 pxDescriptor->status = ACT;
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363 pxDescriptor->next = ( struct Descriptor * ) &xRxDescriptors[ x + 1 ];
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365 /* Mark this buffer as in use. */
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366 ucBufferInUse[ x ] = pdTRUE;
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369 /* The last descriptor points back to the start. */
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370 pxDescriptor->status |= DL;
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371 pxDescriptor->next = ( struct Descriptor * ) &xRxDescriptors[ 0 ];
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373 /* Initialise the Tx descriptors. */
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374 for( x = 0; x < emacNUM_TX_BUFFERS; x++ )
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376 pxDescriptor = &( xTxDescriptors[ x ] );
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378 /* A buffer is not allocated to the Tx descriptor until a send is
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379 actually required. */
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380 pxDescriptor->buf_p = NULL;
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382 pxDescriptor->bufsize = UIP_BUFSIZE;
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383 pxDescriptor->size = 0;
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384 pxDescriptor->status = 0;
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385 pxDescriptor->next = ( struct Descriptor * ) &xTxDescriptors[ x + 1 ];
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388 /* The last descriptor points back to the start. */
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389 pxDescriptor->status |= DL;
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390 pxDescriptor->next = ( struct Descriptor * ) &( xTxDescriptors[ 0 ] );
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392 /* Use the first Rx descriptor to start with. */
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393 pxCurrentRxDesc = ( struct Descriptor * ) &( xRxDescriptors[ 0 ] );
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395 /*-----------------------------------------------------------*/
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397 static unsigned char *prvGetNextBuffer( void )
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400 unsigned char *pucReturn = NULL;
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401 unsigned long ulAttempts = 0;
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403 while( pucReturn == NULL )
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405 /* Look through the buffers to find one that is not in use by
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407 for( x = 0; x < emacNUM_BUFFERS; x++ )
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409 if( ucBufferInUse[ x ] == pdFALSE )
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411 ucBufferInUse[ x ] = pdTRUE;
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412 pucReturn = ( unsigned char * ) &( xEthernetBuffers[ x ][ 0 ] );
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417 /* Was a buffer found? */
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418 if( pucReturn == NULL )
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422 if( ulAttempts >= emacBUFFER_WAIT_ATTEMPTS )
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427 /* Wait then look again. */
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428 vTaskDelay( emacBUFFER_WAIT_DELAY_ms );
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434 /*-----------------------------------------------------------*/
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436 static void prvReturnBuffer( unsigned char *pucBuffer )
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440 /* Return a buffer to the pool of free buffers. */
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441 for( ul = 0; ul < emacNUM_BUFFERS; ul++ )
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443 if( &( xEthernetBuffers[ ul ][ 0 ] ) == ( void * ) pucBuffer )
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445 ucBufferInUse[ ul ] = pdFALSE;
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450 /*-----------------------------------------------------------*/
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452 static void prvResetEverything( void )
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454 /* Temporary code just to see if this gets called. This function has not
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455 been implemented. */
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456 portDISABLE_INTERRUPTS();
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459 /*-----------------------------------------------------------*/
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461 static unsigned long prvCheckRxFifoStatus( void )
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463 unsigned long ulReturn = 0;
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465 if( ( pxCurrentRxDesc->status & ACT ) != 0 )
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467 /* Current descriptor is still active. */
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469 else if( ( pxCurrentRxDesc->status & FE ) != 0 )
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471 /* Frame error. Clear the error. */
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472 pxCurrentRxDesc->status &= ~( FP1 | FP0 | FE );
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473 pxCurrentRxDesc->status &= ~( RMAF | RRF | RTLF | RTSF | PRE | CERF );
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474 pxCurrentRxDesc->status |= ACT;
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475 pxCurrentRxDesc = pxCurrentRxDesc->next;
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477 if( EDMAC.EDRRR.LONG == 0x00000000UL )
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479 /* Restart Ethernet if it has stopped. */
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480 EDMAC.EDRRR.LONG = 0x00000001UL;
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485 /* The descriptor contains a frame. Because of the size of the buffers
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486 the frame should always be complete. */
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487 if( ( pxCurrentRxDesc->status & FP0 ) == FP0 )
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489 ulReturn = pxCurrentRxDesc->size;
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493 /* Do not expect to get here. */
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494 prvResetEverything();
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500 /*-----------------------------------------------------------*/
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502 static void prvResetMAC( void )
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504 /* Ensure the EtherC and EDMAC are enabled. */
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505 SYSTEM.MSTPCRB.BIT.MSTPB15 = 0;
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506 vTaskDelay( 100 / portTICK_PERIOD_MS );
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508 EDMAC.EDMR.BIT.SWR = 1;
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510 /* Crude wait for reset to complete. */
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511 vTaskDelay( 500 / portTICK_PERIOD_MS );
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513 /*-----------------------------------------------------------*/
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515 static void prvConfigureEtherCAndEDMAC( void )
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517 /* Initialisation code taken from Renesas example project. */
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519 /* TODO: Check bit 5 */
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520 ETHERC.ECSR.LONG = 0x00000037; /* Clear all ETHERC statuS BFR, PSRTO, LCHNG, MPD, ICD */
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522 /* Set the EDMAC interrupt priority. */
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523 _IPR( _ETHER_EINT ) = configKERNEL_INTERRUPT_PRIORITY;
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525 /* TODO: Check bit 5 */
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526 /* Enable interrupts of interest only. */
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527 EDMAC.EESIPR.LONG = emacTX_END_INTERRUPT | emacRX_END_INTERRUPT;
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528 ETHERC.RFLR.LONG = 1518; /* Ether payload is 1500+ CRC */
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529 ETHERC.IPGR.LONG = 0x00000014; /* Intergap is 96-bit time */
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532 EDMAC.EESR.LONG = 0x47FF0F9F; /* Clear all ETHERC and EDMAC status bits */
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533 #ifdef __RX_LITTLE_ENDIAN__
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534 EDMAC.EDMR.BIT.DE = 1;
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536 EDMAC.RDLAR = ( void * ) pxCurrentRxDesc; /* Initialaize Rx Descriptor List Address */
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537 EDMAC.TDLAR = ( void * ) &( xTxDescriptors[ 0 ] ); /* Initialaize Tx Descriptor List Address */
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538 EDMAC.TRSCER.LONG = 0x00000000; /* Copy-back status is RFE & TFE only */
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539 EDMAC.TFTR.LONG = 0x00000000; /* Threshold of Tx_FIFO */
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540 EDMAC.FDR.LONG = 0x00000000; /* Transmit fifo & receive fifo is 256 bytes */
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541 EDMAC.RMCR.LONG = 0x00000003; /* Receive function is normal mode(continued) */
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542 ETHERC.ECMR.BIT.PRM = 0; /* Ensure promiscuous mode is off. */
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544 /* Enable the interrupt... */
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545 _IEN( _ETHER_EINT ) = 1;
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547 /*-----------------------------------------------------------*/
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549 void vEMAC_ISR_Handler( void )
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551 unsigned long ul = EDMAC.EESR.LONG;
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552 long lHigherPriorityTaskWoken = pdFALSE;
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553 extern QueueHandle_t xEMACEventQueue;
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554 const unsigned long ulRxEvent = uipETHERNET_RX_EVENT;
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556 /* Re-enabled interrupts. */
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557 __asm volatile( "SETPSW I" );
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559 /* Has a Tx end occurred? */
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560 if( ul & emacTX_END_INTERRUPT )
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562 /* Only return the buffer to the pool once both Txes have completed. */
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563 prvReturnBuffer( ( void * ) xTxDescriptors[ 0 ].buf_p );
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564 EDMAC.EESR.LONG = emacTX_END_INTERRUPT;
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567 /* Has an Rx end occurred? */
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568 if( ul & emacRX_END_INTERRUPT )
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570 /* Make sure the Ethernet task is not blocked waiting for a packet. */
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571 xQueueSendFromISR( xEMACEventQueue, &ulRxEvent, &lHigherPriorityTaskWoken );
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572 portYIELD_FROM_ISR( lHigherPriorityTaskWoken );
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573 EDMAC.EESR.LONG = emacRX_END_INTERRUPT;
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