2 * FreeRTOS Kernel V10.2.0
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3 * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.
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5 * Permission is hereby granted, free of charge, to any person obtaining a copy of
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6 * this software and associated documentation files (the "Software"), to deal in
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7 * the Software without restriction, including without limitation the rights to
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8 * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
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9 * the Software, and to permit persons to whom the Software is furnished to do so,
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10 * subject to the following conditions:
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12 * The above copyright notice and this permission notice shall be included in all
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13 * copies or substantial portions of the Software.
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15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
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17 * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
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18 * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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19 * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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20 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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22 * http://www.FreeRTOS.org
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23 * http://aws.amazon.com/freertos
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25 * 1 tab == 4 spaces!
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28 /* Hardware specific includes. */
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29 #include <iorx62n.h>
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30 #include "typedefine.h"
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31 #include "r_ether.h"
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34 /* FreeRTOS includes. */
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35 #include "FreeRTOS.h"
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40 #include "net/uip.h"
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42 /* The time to wait between attempts to obtain a free buffer. */
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43 #define emacBUFFER_WAIT_DELAY_ms ( 3 / portTICK_PERIOD_MS )
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45 /* The number of times emacBUFFER_WAIT_DELAY_ms should be waited before giving
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46 up on attempting to obtain a free buffer all together. */
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47 #define emacBUFFER_WAIT_ATTEMPTS ( 30 )
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49 /* The number of Rx descriptors. */
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50 #define emacNUM_RX_DESCRIPTORS 8
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52 /* The number of Tx descriptors. When using uIP there is not point in having
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54 #define emacNUM_TX_BUFFERS 2
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56 /* The total number of EMAC buffers to allocate. */
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57 #define emacNUM_BUFFERS ( emacNUM_RX_DESCRIPTORS + emacNUM_TX_BUFFERS )
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59 /* The time to wait for the Tx descriptor to become free. */
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60 #define emacTX_WAIT_DELAY_ms ( 10 / portTICK_PERIOD_MS )
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62 /* The total number of times to wait emacTX_WAIT_DELAY_ms for the Tx descriptor to
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64 #define emacTX_WAIT_ATTEMPTS ( 50 )
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66 /* Only Rx end and Tx end interrupts are used by this driver. */
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67 #define emacTX_END_INTERRUPT ( 1UL << 21UL )
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68 #define emacRX_END_INTERRUPT ( 1UL << 18UL )
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70 /*-----------------------------------------------------------*/
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72 /* The buffers and descriptors themselves. */
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73 #pragma data_alignment=32
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74 volatile ethfifo xRxDescriptors[ emacNUM_RX_DESCRIPTORS ];
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76 #pragma data_alignment=32
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77 volatile ethfifo xTxDescriptors[ emacNUM_TX_BUFFERS ];
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79 #pragma data_alignment=32
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80 char xEthernetBuffers[ emacNUM_BUFFERS ][ UIP_BUFSIZE ];
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83 /* Used to indicate which buffers are free and which are in use. If an index
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84 contains 0 then the corresponding buffer in xEthernetBuffers is free, otherwise
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85 the buffer is in use or about to be used. */
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86 static unsigned char ucBufferInUse[ emacNUM_BUFFERS ];
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88 /*-----------------------------------------------------------*/
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91 * Initialise both the Rx and Tx descriptors.
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93 static void prvInitialiseDescriptors( void );
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96 * Return a pointer to a free buffer within xEthernetBuffers.
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98 static unsigned char *prvGetNextBuffer( void );
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101 * Return a buffer to the list of free buffers.
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103 static void prvReturnBuffer( unsigned char *pucBuffer );
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106 * Examine the status of the next Rx FIFO to see if it contains new data.
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108 static unsigned long prvCheckRxFifoStatus( void );
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111 * Setup the microcontroller for communication with the PHY.
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113 static void prvResetMAC( void );
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116 * Configure the Ethernet interface peripherals.
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118 static void prvConfigureEtherCAndEDMAC( void );
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121 * Something has gone wrong with the descriptor usage. Reset all the buffers
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124 static void prvResetEverything( void );
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126 /*-----------------------------------------------------------*/
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128 /* Points to the Rx descriptor currently in use. */
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129 static volatile ethfifo *pxCurrentRxDesc = NULL;
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131 /* The buffer used by the uIP stack to both receive and send. This points to
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132 one of the Ethernet buffers when its actually in use. */
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133 unsigned char *uip_buf = NULL;
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135 /*-----------------------------------------------------------*/
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137 void vInitEmac( void )
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139 /* Software reset. */
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142 /* Set the Rx and Tx descriptors into their initial state. */
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143 prvInitialiseDescriptors();
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145 /* Set the MAC address into the ETHERC */
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146 ETHERC.MAHR = ( ( unsigned long ) configMAC_ADDR0 << 24UL ) |
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147 ( ( unsigned long ) configMAC_ADDR1 << 16UL ) |
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148 ( ( unsigned long ) configMAC_ADDR2 << 8UL ) |
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149 ( unsigned long ) configMAC_ADDR3;
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151 ETHERC.MALR.BIT.MA = ( ( unsigned long ) configMAC_ADDR4 << 8UL ) |
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152 ( unsigned long ) configMAC_ADDR5;
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154 /* Perform rest of interface hardware configuration. */
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155 prvConfigureEtherCAndEDMAC();
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157 /* Nothing received yet, so uip_buf points nowhere. */
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160 /* Initialize the PHY */
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163 /*-----------------------------------------------------------*/
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165 void vEMACWrite( void )
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169 /* Wait until the second transmission of the last packet has completed. */
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170 for( x = 0; x < emacTX_WAIT_ATTEMPTS; x++ )
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172 if( ( xTxDescriptors[ 1 ].status & ACT ) != 0 )
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174 /* Descriptor is still active. */
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175 vTaskDelay( emacTX_WAIT_DELAY_ms );
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183 /* Is the descriptor free after waiting for it? */
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184 if( ( xTxDescriptors[ 1 ].status & ACT ) != 0 )
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186 /* Something has gone wrong. */
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187 prvResetEverything();
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190 /* Setup both descriptors to transmit the frame. */
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191 xTxDescriptors[ 0 ].buf_p = ( char * ) uip_buf;
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192 xTxDescriptors[ 0 ].bufsize = uip_len;
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193 xTxDescriptors[ 1 ].buf_p = ( char * ) uip_buf;
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194 xTxDescriptors[ 1 ].bufsize = uip_len;
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196 /* uip_buf is being sent by the Tx descriptor. Allocate a new buffer
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197 for use by the stack. */
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198 uip_buf = prvGetNextBuffer();
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200 /* Clear previous settings and go. */
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201 xTxDescriptors[0].status &= ~( FP1 | FP0 );
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202 xTxDescriptors[0].status |= ( FP1 | FP0 | ACT );
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203 xTxDescriptors[1].status &= ~( FP1 | FP0 );
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204 xTxDescriptors[1].status |= ( FP1 | FP0 | ACT );
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206 EDMAC.EDTRR.LONG = 0x00000001;
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208 /*-----------------------------------------------------------*/
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210 unsigned long ulEMACRead( void )
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212 unsigned long ulBytesReceived;
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214 ulBytesReceived = prvCheckRxFifoStatus();
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216 if( ulBytesReceived > 0 )
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218 /* Mark the pxDescriptor buffer as free as uip_buf is going to be set to
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219 the buffer that contains the received data. */
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220 prvReturnBuffer( uip_buf );
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222 /* Point uip_buf to the data about ot be processed. */
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223 uip_buf = ( void * ) pxCurrentRxDesc->buf_p;
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225 /* Allocate a new buffer to the descriptor, as uip_buf is now using it's
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227 pxCurrentRxDesc->buf_p = ( char * ) prvGetNextBuffer();
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229 /* Prepare the descriptor to go again. */
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230 pxCurrentRxDesc->status &= ~( FP1 | FP0 );
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231 pxCurrentRxDesc->status |= ACT;
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233 /* Move onto the next buffer in the ring. */
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234 pxCurrentRxDesc = pxCurrentRxDesc->next;
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236 if( EDMAC.EDRRR.LONG == 0x00000000L )
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238 /* Restart Ethernet if it has stopped */
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239 EDMAC.EDRRR.LONG = 0x00000001L;
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243 return ulBytesReceived;
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245 /*-----------------------------------------------------------*/
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247 long lEMACWaitForLink( void )
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251 /* Set the link status. */
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252 switch( phy_set_autonegotiate() )
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254 /* Half duplex link */
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255 case PHY_LINK_100H:
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256 ETHERC.ECMR.BIT.DM = 0;
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257 ETHERC.ECMR.BIT.RTM = 1;
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262 ETHERC.ECMR.BIT.DM = 0;
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263 ETHERC.ECMR.BIT.RTM = 0;
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268 /* Full duplex link */
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269 case PHY_LINK_100F:
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270 ETHERC.ECMR.BIT.DM = 1;
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271 ETHERC.ECMR.BIT.RTM = 1;
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276 ETHERC.ECMR.BIT.DM = 1;
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277 ETHERC.ECMR.BIT.RTM = 0;
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286 if( lReturn == pdPASS )
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288 /* Enable receive and transmit. */
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289 ETHERC.ECMR.BIT.RE = 1;
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290 ETHERC.ECMR.BIT.TE = 1;
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292 /* Enable EDMAC receive */
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293 EDMAC.EDRRR.LONG = 0x1;
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298 /*-----------------------------------------------------------*/
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300 static void prvInitialiseDescriptors( void )
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302 volatile ethfifo *pxDescriptor;
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305 for( x = 0; x < emacNUM_BUFFERS; x++ )
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307 /* Ensure none of the buffers are shown as in use at the start. */
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308 ucBufferInUse[ x ] = pdFALSE;
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311 /* Initialise the Rx descriptors. */
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312 for( x = 0; x < emacNUM_RX_DESCRIPTORS; x++ )
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314 pxDescriptor = &( xRxDescriptors[ x ] );
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315 pxDescriptor->buf_p = &( xEthernetBuffers[ x ][ 0 ] );
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317 pxDescriptor->bufsize = UIP_BUFSIZE;
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318 pxDescriptor->size = 0;
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319 pxDescriptor->status = ACT;
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320 pxDescriptor->next = ( ethfifo * ) &xRxDescriptors[ x + 1 ];
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322 /* Mark this buffer as in use. */
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323 ucBufferInUse[ x ] = pdTRUE;
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326 /* The last descriptor points back to the start. */
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327 pxDescriptor->status |= DL;
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328 pxDescriptor->next = ( ethfifo * ) &xRxDescriptors[ 0 ];
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330 /* Initialise the Tx descriptors. */
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331 for( x = 0; x < emacNUM_TX_BUFFERS; x++ )
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333 pxDescriptor = &( xTxDescriptors[ x ] );
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335 /* A buffer is not allocated to the Tx descriptor until a send is
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336 actually required. */
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337 pxDescriptor->buf_p = NULL;
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339 pxDescriptor->bufsize = UIP_BUFSIZE;
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340 pxDescriptor->size = 0;
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341 pxDescriptor->status = 0;
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342 pxDescriptor->next = ( ethfifo * ) &xTxDescriptors[ x + 1 ];
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345 /* The last descriptor points back to the start. */
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346 pxDescriptor->status |= DL;
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347 pxDescriptor->next = ( ethfifo * ) &( xTxDescriptors[ 0 ] );
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349 /* Use the first Rx descriptor to start with. */
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350 pxCurrentRxDesc = &( xRxDescriptors[ 0 ] );
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352 /*-----------------------------------------------------------*/
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354 static unsigned char *prvGetNextBuffer( void )
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357 unsigned char *pucReturn = NULL;
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358 unsigned long ulAttempts = 0;
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360 while( pucReturn == NULL )
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362 /* Look through the buffers to find one that is not in use by
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364 for( x = 0; x < emacNUM_BUFFERS; x++ )
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366 if( ucBufferInUse[ x ] == pdFALSE )
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368 ucBufferInUse[ x ] = pdTRUE;
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369 pucReturn = ( unsigned char * ) &( xEthernetBuffers[ x ][ 0 ] );
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374 /* Was a buffer found? */
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375 if( pucReturn == NULL )
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379 if( ulAttempts >= emacBUFFER_WAIT_ATTEMPTS )
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384 /* Wait then look again. */
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385 vTaskDelay( emacBUFFER_WAIT_DELAY_ms );
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391 /*-----------------------------------------------------------*/
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393 static void prvReturnBuffer( unsigned char *pucBuffer )
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397 /* Return a buffer to the pool of free buffers. */
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398 for( ul = 0; ul < emacNUM_BUFFERS; ul++ )
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400 if( &( xEthernetBuffers[ ul ][ 0 ] ) == ( void * ) pucBuffer )
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402 ucBufferInUse[ ul ] = pdFALSE;
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407 /*-----------------------------------------------------------*/
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409 static void prvResetEverything( void )
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411 /* Temporary code just to see if this gets called. This function has not
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412 been implemented. */
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413 portDISABLE_INTERRUPTS();
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416 /*-----------------------------------------------------------*/
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418 static unsigned long prvCheckRxFifoStatus( void )
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420 unsigned long ulReturn = 0;
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422 if( ( pxCurrentRxDesc->status & ACT ) != 0 )
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424 /* Current descriptor is still active. */
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426 else if( ( pxCurrentRxDesc->status & FE ) != 0 )
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428 /* Frame error. Clear the error. */
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429 pxCurrentRxDesc->status &= ~( FP1 | FP0 | FE );
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430 pxCurrentRxDesc->status &= ~( RMAF | RRF | RTLF | RTSF | PRE | CERF );
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431 pxCurrentRxDesc->status |= ACT;
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432 pxCurrentRxDesc = pxCurrentRxDesc->next;
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434 if( EDMAC.EDRRR.LONG == 0x00000000UL )
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436 /* Restart Ethernet if it has stopped. */
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437 EDMAC.EDRRR.LONG = 0x00000001UL;
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442 /* The descriptor contains a frame. Because of the size of the buffers
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443 the frame should always be complete. */
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444 if( ( pxCurrentRxDesc->status & FP0 ) == FP0 )
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446 ulReturn = pxCurrentRxDesc->size;
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450 /* Do not expect to get here. */
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451 prvResetEverything();
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457 /*-----------------------------------------------------------*/
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459 static void prvResetMAC( void )
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461 /* Ensure the EtherC and EDMAC are enabled. */
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462 SYSTEM.MSTPCRB.BIT.MSTPB15 = 0;
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463 vTaskDelay( 100 / portTICK_PERIOD_MS );
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465 EDMAC.EDMR.BIT.SWR = 1;
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467 /* Crude wait for reset to complete. */
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468 vTaskDelay( 500 / portTICK_PERIOD_MS );
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470 /*-----------------------------------------------------------*/
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472 static void prvConfigureEtherCAndEDMAC( void )
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474 /* Initialisation code taken from Renesas example project. */
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476 /* TODO: Check bit 5 */
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477 ETHERC.ECSR.LONG = 0x00000037; /* Clear all ETHERC statuS BFR, PSRTO, LCHNG, MPD, ICD */
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479 /* Set the EDMAC interrupt priority. */
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480 _IPR( _ETHER_EINT ) = configKERNEL_INTERRUPT_PRIORITY;
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482 /* TODO: Check bit 5 */
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483 /* Enable interrupts of interest only. */
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484 EDMAC.EESIPR.LONG = emacTX_END_INTERRUPT | emacRX_END_INTERRUPT;
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485 ETHERC.RFLR.LONG = 1518; /* Ether payload is 1500+ CRC */
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486 ETHERC.IPGR.LONG = 0x00000014; /* Intergap is 96-bit time */
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489 EDMAC.EESR.LONG = 0x47FF0F9F; /* Clear all ETHERC and EDMAC status bits */
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490 #if __LITTLE_ENDIAN__ == 1
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491 EDMAC.EDMR.BIT.DE = 1;
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493 EDMAC.RDLAR = ( void * ) pxCurrentRxDesc; /* Initialaize Rx Descriptor List Address */
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494 EDMAC.TDLAR = ( void * ) &( xTxDescriptors[ 0 ] );/* Initialaize Tx Descriptor List Address */
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495 EDMAC.TRSCER.LONG = 0x00000000; /* Copy-back status is RFE & TFE only */
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496 EDMAC.TFTR.LONG = 0x00000000; /* Threshold of Tx_FIFO */
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497 EDMAC.FDR.LONG = 0x00000000; /* Transmit fifo & receive fifo is 256 bytes */
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498 EDMAC.RMCR.LONG = 0x00000003; /* Receive function is normal mode(continued) */
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499 ETHERC.ECMR.BIT.PRM = 0; /* Ensure promiscuous mode is off. */
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501 /* Enable the interrupt... */
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502 _IEN( _ETHER_EINT ) = 1;
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504 /*-----------------------------------------------------------*/
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506 #pragma vector = VECT_ETHER_EINT
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507 __interrupt void vEMAC_ISR_Handler( void )
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509 unsigned long ul = EDMAC.EESR.LONG;
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510 long lHigherPriorityTaskWoken = pdFALSE;
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511 extern QueueHandle_t xEMACEventQueue;
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512 const unsigned long ulRxEvent = uipETHERNET_RX_EVENT;
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514 __enable_interrupt();
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516 /* Has a Tx end occurred? */
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517 if( ul & emacTX_END_INTERRUPT )
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519 /* Only return the buffer to the pool once both Txes have completed. */
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520 prvReturnBuffer( ( void * ) xTxDescriptors[ 0 ].buf_p );
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521 EDMAC.EESR.LONG = emacTX_END_INTERRUPT;
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524 /* Has an Rx end occurred? */
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525 if( ul & emacRX_END_INTERRUPT )
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527 /* Make sure the Ethernet task is not blocked waiting for a packet. */
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528 xQueueSendFromISR( xEMACEventQueue, &ulRxEvent, &lHigherPriorityTaskWoken );
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529 portYIELD_FROM_ISR( lHigherPriorityTaskWoken );
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530 EDMAC.EESR.LONG = emacRX_END_INTERRUPT;
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