git.sur5r.net Git - freertos/blob - FreeRTOS/Demo/RX600_RX630-RSK_Renesas/RTOSDemo/Renesas-Files/cgc.h

   1 \r
   2 \r
   3 /*******************************************************************************\r
   4 * DISCLAIMER\r
   5 * This software is supplied by Renesas Electronics Corporation and is only \r
   6 * intended for use with Renesas products. No other uses are authorized. This \r
   7 * software is owned by Renesas Electronics Corporation and is protected under\r
   8 * all applicable laws, including copyright laws.\r
   9 * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING\r
  10 * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT\r
  11 * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE \r
  12 * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.\r
  13 * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS \r
  14 * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE \r
  15 * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR\r
  16 * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE\r
  17 * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.\r
  18 * Renesas reserves the right, without notice, to make changes to this software\r
  19 * and to discontinue the availability of this software. By using this software,\r
  20 * you agree to the additional terms and conditions found by accessing the \r
  21 * following link:\r
  22 * http://www.renesas.com/disclaimer\r
  23 *******************************************************************************/\r
  24 \r
  25 \r
  26 /*\r
  27  * cgc.h\r
  28  *\r
  29  *  Created on: 01 Oct 2011\r
  30  *      Author: RJW\r
  31  *              Reneses Electronics Europe Ltd\r
  32  */\r
  33  \r
  34 \r
  35 #ifndef CGC_H_\r
  36 #define CGC_H_\r
  37 \r
  38 /******************************************************************************\r
  39  Function Prototypes\r
  40 ******************************************************************************/\r
  41 void InitCGC(void);\r
  42 \r
  43 \r
  44 /*****************************************************************************/\r
  45 /*                                                                           */\r
  46 /* Set the CGC (Clock Generation Circuit of the RX630 using the              */\r
  47 /* following 7 STEPS                                                         */\r
  48 /*                                                                           */\r
  49 /*****************************************************************************/\r
  50 \r
  51 \r
  52 /*****************************************************************************/\r
  53 /*                                                                           */\r
  54 /* STEP 1: System Clock Options                                              */\r
  55 /*                                                                           */\r
  56 /* Enter one of the CLK_SOURCE_ options into the                             */\r
  57 /*                                                                           */\r
  58 /*      #define     CLK_SOURCE          ( xxx )                              */\r
  59 /* below.                                                                    */\r
  60 /* This will be the clock source that the device will switch to as part of   */\r
  61 /* HardwareSetup()                                                           */\r
  62 /* Extra clocks can be enabled in STEP 3.                                    */\r
  63 /*                                                                           */\r
  64 /* For example                                                               */\r
  65 /*      #define         CLK_SOURCE          (CLK_SOURCE_MAIN)                    */\r
  66 /*                                                                           */\r
  67 /*****************************************************************************/\r
  68 #define     CLK_SOURCE_LOCO     0x0000\r
  69 #define     CLK_SOURCE_HOCO     0x0100\r
  70 #define     CLK_SOURCE_MAIN     0x0200\r
  71 #define     CLK_SOURCE_SUB      0x0300\r
  72 #define     CLK_SOURCE_PLL      0x0400\r
  73 \r
  74 #define         CLK_SOURCE          (CLK_SOURCE_PLL)\r
  75 \r
  76 \r
  77 /*****************************************************************************/\r
  78 /*                                                                           */\r
  79 /* STEP 2: External XTAL values                                              */\r
  80 /*                                                                           */\r
  81 /* If using the CLK_SOURCE_MAIN, CLK_SOURCE_SUB, CLK_SOURCE_PLL              */\r
  82 /* enter the MAIN XTAL and SUB XTAL values here.                             */\r
  83 /*                                                                           */\r
  84 /* If using the PLL, enter the PLL multiplier and PLL frequency divder       */\r
  85 /* Use the divider so that the input frequency into the PLL is in            */\r
  86 /* the range of 4 MHz to 16 MHz.                                             */\r
  87 /*                                                                           */\r
  88 /* Use the multiplier so that the output frequency of the PLL is in          */\r
  89 /* the range of 104MHz to 200Mhz                                             */\r
  90 /*                                                                           */\r
  91 /* The PLL frequency divider values are:                                     */\r
  92 /*      /1, /2, /4                                                           */\r
  93 /* The PLL muliplier values are:                                             */\r
  94 /*      x8, x10, x12, x16, x20, x24, x25, x50                                */\r
  95 /*                                                                           */\r
  96 /* Example:                                                                  */\r
  97 /*      XTAL = 12MHz                                                         */\r
  98 /*      PLL Divider = 1                                                      */\r
  99 /*                                                                           */\r
 100 /*      Therefore, input into PLL = 12M / 1                                  */\r
 101 /*                                = 12M                                      */\r
 102 /*      PLL Multipler = 16                                                   */\r
 103 /*                                                                           */\r
 104 /*      Therefore, ouput of PLL = 12M x 16                                   */\r
 105 /*                              = 192M                                       */\r
 106 /*                                                                           */\r
 107 /* NOTE: The maximum XTAL is 20MHz                                           */\r
 108 /*****************************************************************************/\r
 109 #define     XTAL_FREQUENCY      (12000000L)     \r
 110 #define     PLL_MUL             (16)\r
 111 #define     PLL_INPUT_FREQ_DIV  (1)\r
 112 \r
 113 #define     SUB_FREQUENCY       (32768L)        \r
 114 \r
 115 \r
 116 /*****************************************************************************/\r
 117 /*                                                                           */\r
 118 /* STEP 3: Enable the chosen clock source and any extra clock sources        */\r
 119 /* Remeber to enable the clock source chosen in STEP 1.                      */\r
 120 /* Foe example, if CLK_SOURCE_PLL has been chosen, set                       */\r
 121 /* #define     ENABLE_PLL          (1)                                       */\r
 122 /*                                                                           */\r
 123 /*****************************************************************************/\r
 124 #define     ENABLE_HOCO         (1)\r
 125 #define     ENABLE_SUB          (0)\r
 126 #define     ENABLE_MAIN         (0)\r
 127 #define     ENABLE_PLL          (1)\r
 128 \r
 129 \r
 130 \r
 131 /*****************************************************************************/\r
 132 /*                                                                           */\r
 133 /* STEP 4:                                                                   */\r
 134 /*  Enter the Clock Divders for                                              */\r
 135 /*      - FCLK_DIV, ICLK_DIV, BCLK_DIV, PCLKA_DIV, PCLKB_DIV                 */\r
 136 /*  Valid values are 1, 2, 4, 8, 16, 32 and 64                               */\r
 137 /*                                                                           */\r
 138 /* The Clock Value being divided is:                                         */\r
 139 /*  If LOCO, 125kHz                                                          */\r
 140 /*  If HOCO, 50MHz                                                           */\r
 141 /*  If SUB,  the value of SUB specified in STEP 2                            */\r
 142 /*  If MAIN, the value of XTAL specified in STEP 2                           */\r
 143 /*  If PLL,  the result of the XTAL, PLL Div, PLL Mul specified in STEP 2    */\r
 144 /*****************************************************************************/\r
 145 #define     FCLK_DIV            (4)\r
 146 #define     ICLK_DIV            (2)\r
 147 #define     BCLK_DIV            (4)\r
 148 #define     PCLK1215_DIV        (2)             /* Do not change this        */\r
 149 #define     PCLKB_DIV           (4)\r
 150 #define     PCLK47_DIV          (2)             /* Do not change this        */\r
 151 #define     PCLK03_DIV          (2)             /* Do not change this        */\r
 152 \r
 153 \r
 154 /*****************************************************************************/\r
 155 /*                                                                           */\r
 156 /* STEP 5:                                                                   */\r
 157 /*  Enter the Clock Divder for                                               */\r
 158 /*      - IEBCK_DIV                                                          */\r
 159 /*  Valid values are 2, 4, 6, 8, 16, 32 and 64                               */\r
 160 /*                                                                           */\r
 161 /* The Clock Value being divided is:                                         */\r
 162 /*  If LOCO, 125kHz                                                          */\r
 163 /*  If HOCO, 50MHz                                                           */\r
 164 /*  If SUB,  the value of SUB specified in STEP 2                            */\r
 165 /*  If MAIN, the value of XTAL specified in STEP 2                           */\r
 166 /*  If PLL,  the result of the XTAL, PLL Div, PLL Mul specified in STEP 2    */\r
 167 /*****************************************************************************/\r
 168 #define     IEBCK_DIV           (2)\r
 169 \r
 170 \r
 171 /*****************************************************************************/\r
 172 /*                                                                           */\r
 173 /* STEP 6:                                                                   */\r
 174 /*  Enter the Clock Divder for                                               */\r
 175 /*      - UCK_DIV                                                            */\r
 176 /*  Valid values are 3, 4                                                    */\r
 177 /*                                                                           */\r
 178 /* The Clock Value being divided is:                                         */\r
 179 /*  If LOCO, 125kHz                                                          */\r
 180 /*  If HOCO, 50MHz                                                           */\r
 181 /*  If SUB,  the value of SUB specified in STEP 2                            */\r
 182 /*  If MAIN, the value of XTAL specified in STEP 2                           */\r
 183 /*  If PLL,  the result of the XTAL, PLL Div, PLL Mul specified in STEP 2    */\r
 184 /*****************************************************************************/\r
 185 #define     UCK_DIV             (3)\r
 186 \r
 187 \r
 188 /*****************************************************************************/\r
 189 /*                                                                           */\r
 190 /* STEP 7:                                                                   */\r
 191 /*  Specify the use of BCLK pin                                              */\r
 192 /*  To ENABLE,  set to (0)                                                   */\r
 193 /*  To DISABLE, set to (1)                                                   */\r
 194 /*                                                                           */\r
 195 /*****************************************************************************/\r
 196 #define     BCLK_PIN            (1)\r
 197 \r
 198 \r
 199 /*****************************************************************************/\r
 200 /* Clock configuration is now complete.                                      */\r
 201 /*****************************************************************************/\r
 202 #include "cgc_set.h"\r
 203 #include "cgc_error.h"\r
 204 \r
 205 #endif