2 FreeRTOS V8.0.0:rc1 - Copyright (C) 2014 Real Time Engineers Ltd.
\r
5 VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
\r
7 ***************************************************************************
\r
9 * FreeRTOS provides completely free yet professionally developed, *
\r
10 * robust, strictly quality controlled, supported, and cross *
\r
11 * platform software that has become a de facto standard. *
\r
13 * Help yourself get started quickly and support the FreeRTOS *
\r
14 * project by purchasing a FreeRTOS tutorial book, reference *
\r
15 * manual, or both from: http://www.FreeRTOS.org/Documentation *
\r
19 ***************************************************************************
\r
21 This file is part of the FreeRTOS distribution.
\r
23 FreeRTOS is free software; you can redistribute it and/or modify it under
\r
24 the terms of the GNU General Public License (version 2) as published by the
\r
25 Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.
\r
27 >>! NOTE: The modification to the GPL is included to allow you to distribute
\r
28 >>! a combined work that includes FreeRTOS without being obliged to provide
\r
29 >>! the source code for proprietary components outside of the FreeRTOS
\r
32 FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
\r
33 WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
\r
34 FOR A PARTICULAR PURPOSE. Full license text is available from the following
\r
35 link: http://www.freertos.org/a00114.html
\r
39 ***************************************************************************
\r
41 * Having a problem? Start by reading the FAQ "My application does *
\r
42 * not run, what could be wrong?" *
\r
44 * http://www.FreeRTOS.org/FAQHelp.html *
\r
46 ***************************************************************************
\r
48 http://www.FreeRTOS.org - Documentation, books, training, latest versions,
\r
49 license and Real Time Engineers Ltd. contact details.
\r
51 http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
\r
52 including FreeRTOS+Trace - an indispensable productivity tool, a DOS
\r
53 compatible FAT file system, and our tiny thread aware UDP/IP stack.
\r
55 http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High
\r
56 Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS
\r
57 licenses offer ticketed support, indemnification and middleware.
\r
59 http://www.SafeRTOS.com - High Integrity Systems also provide a safety
\r
60 engineered and independently SIL3 certified version for use in safety and
\r
61 mission critical applications that require provable dependability.
\r
66 /* FreeRTOS includes. */
\r
67 #include "FreeRTOS.h"
\r
71 /* Hardware specific includes. */
\r
72 #include "r_ether.h"
\r
76 #include "net/uip.h"
\r
78 /* The time to wait between attempts to obtain a free buffer. */
\r
79 #define emacBUFFER_WAIT_DELAY_ms ( 3 / portTICK_RATE_MS )
\r
81 /* The number of times emacBUFFER_WAIT_DELAY_ms should be waited before giving
\r
82 up on attempting to obtain a free buffer all together. */
\r
83 #define emacBUFFER_WAIT_ATTEMPTS ( 30 )
\r
85 /* The number of Rx descriptors. */
\r
86 #define emacNUM_RX_DESCRIPTORS 8
\r
88 /* The number of Tx descriptors. When using uIP there is not point in having
\r
90 #define emacNUM_TX_BUFFERS 2
\r
92 /* The total number of EMAC buffers to allocate. */
\r
93 #define emacNUM_BUFFERS ( emacNUM_RX_DESCRIPTORS + emacNUM_TX_BUFFERS )
\r
95 /* The time to wait for the Tx descriptor to become free. */
\r
96 #define emacTX_WAIT_DELAY_ms ( 10 / portTICK_RATE_MS )
\r
98 /* The total number of times to wait emacTX_WAIT_DELAY_ms for the Tx descriptor to
\r
100 #define emacTX_WAIT_ATTEMPTS ( 50 )
\r
102 /* Only Rx end and Tx end interrupts are used by this driver. */
\r
103 #define emacTX_END_INTERRUPT ( 1UL << 21UL )
\r
104 #define emacRX_END_INTERRUPT ( 1UL << 18UL )
\r
106 /*-----------------------------------------------------------*/
\r
108 /* The buffers and descriptors themselves. */
\r
109 #pragma section _RX_DESC
\r
110 volatile ethfifo xRxDescriptors[ emacNUM_RX_DESCRIPTORS ];
\r
111 #pragma section _TX_DESC
\r
112 volatile ethfifo xTxDescriptors[ emacNUM_TX_BUFFERS ];
\r
113 #pragma section _ETHERNET_BUFFERS
\r
116 unsigned long ulAlignmentVariable;
\r
117 char cBuffer[ emacNUM_BUFFERS ][ UIP_BUFSIZE ];
\r
118 } xEthernetBuffers;
\r
124 /* Used to indicate which buffers are free and which are in use. If an index
\r
125 contains 0 then the corresponding buffer in xEthernetBuffers is free, otherwise
\r
126 the buffer is in use or about to be used. */
\r
127 static unsigned char ucBufferInUse[ emacNUM_BUFFERS ];
\r
129 /*-----------------------------------------------------------*/
\r
132 * Initialise both the Rx and Tx descriptors.
\r
134 static void prvInitialiseDescriptors( void );
\r
137 * Return a pointer to a free buffer within xEthernetBuffers.
\r
139 static unsigned char *prvGetNextBuffer( void );
\r
142 * Return a buffer to the list of free buffers.
\r
144 static void prvReturnBuffer( unsigned char *pucBuffer );
\r
147 * Examine the status of the next Rx FIFO to see if it contains new data.
\r
149 static unsigned long prvCheckRxFifoStatus( void );
\r
152 * Setup the microcontroller for communication with the PHY.
\r
154 static void prvResetMAC( void );
\r
157 * Configure the Ethernet interface peripherals.
\r
159 static void prvConfigureEtherCAndEDMAC( void );
\r
162 * Something has gone wrong with the descriptor usage. Reset all the buffers
\r
165 static void prvResetEverything( void );
\r
167 /*-----------------------------------------------------------*/
\r
169 /* Points to the Rx descriptor currently in use. */
\r
170 static ethfifo *pxCurrentRxDesc = NULL;
\r
172 /* The buffer used by the uIP stack to both receive and send. This points to
\r
173 one of the Ethernet buffers when its actually in use. */
\r
174 unsigned char *uip_buf = NULL;
\r
176 /*-----------------------------------------------------------*/
\r
178 void vInitEmac( void )
\r
180 /* Software reset. */
\r
183 /* Set the Rx and Tx descriptors into their initial state. */
\r
184 prvInitialiseDescriptors();
\r
186 /* Set the MAC address into the ETHERC */
\r
187 ETHERC.MAHR = ( ( unsigned long ) configMAC_ADDR0 << 24UL ) |
\r
188 ( ( unsigned long ) configMAC_ADDR1 << 16UL ) |
\r
189 ( ( unsigned long ) configMAC_ADDR2 << 8UL ) |
\r
190 ( unsigned long ) configMAC_ADDR3;
\r
192 ETHERC.MALR.BIT.MA = ( ( unsigned long ) configMAC_ADDR4 << 8UL ) |
\r
193 ( unsigned long ) configMAC_ADDR5;
\r
195 /* Perform rest of interface hardware configuration. */
\r
196 prvConfigureEtherCAndEDMAC();
\r
198 /* Nothing received yet, so uip_buf points nowhere. */
\r
201 /* Initialize the PHY */
\r
202 configASSERT( phy_init() == R_PHY_OK );
\r
204 /*-----------------------------------------------------------*/
\r
206 void vEMACWrite( void )
\r
210 /* Wait until the second transmission of the last packet has completed. */
\r
211 for( x = 0; x < emacTX_WAIT_ATTEMPTS; x++ )
\r
213 if( ( xTxDescriptors[ 1 ].status & ACT ) != 0 )
\r
215 /* Descriptor is still active. */
\r
216 vTaskDelay( emacTX_WAIT_DELAY_ms );
\r
224 /* Is the descriptor free after waiting for it? */
\r
225 if( ( xTxDescriptors[ 1 ].status & ACT ) != 0 )
\r
227 /* Something has gone wrong. */
\r
228 prvResetEverything();
\r
231 /* Setup both descriptors to transmit the frame. */
\r
232 xTxDescriptors[ 0 ].buf_p = ( char * ) uip_buf;
\r
233 xTxDescriptors[ 0 ].bufsize = uip_len;
\r
234 xTxDescriptors[ 1 ].buf_p = ( char * ) uip_buf;
\r
235 xTxDescriptors[ 1 ].bufsize = uip_len;
\r
237 /* uip_buf is being sent by the Tx descriptor. Allocate a new buffer
\r
238 for use by the stack. */
\r
239 uip_buf = prvGetNextBuffer();
\r
241 /* Clear previous settings and go. */
\r
242 xTxDescriptors[0].status &= ~( FP1 | FP0 );
\r
243 xTxDescriptors[0].status |= ( FP1 | FP0 | ACT );
\r
244 xTxDescriptors[1].status &= ~( FP1 | FP0 );
\r
245 xTxDescriptors[1].status |= ( FP1 | FP0 | ACT );
\r
247 EDMAC.EDTRR.LONG = 0x00000001;
\r
249 /*-----------------------------------------------------------*/
\r
251 unsigned long ulEMACRead( void )
\r
253 unsigned long ulBytesReceived;
\r
255 ulBytesReceived = prvCheckRxFifoStatus();
\r
257 if( ulBytesReceived > 0 )
\r
259 /* Mark the pxDescriptor buffer as free as uip_buf is going to be set to
\r
260 the buffer that contains the received data. */
\r
261 prvReturnBuffer( uip_buf );
\r
263 /* Point uip_buf to the data about ot be processed. */
\r
264 uip_buf = ( void * ) pxCurrentRxDesc->buf_p;
\r
266 /* Allocate a new buffer to the descriptor, as uip_buf is now using it's
\r
268 pxCurrentRxDesc->buf_p = prvGetNextBuffer();
\r
270 /* Prepare the descriptor to go again. */
\r
271 pxCurrentRxDesc->status &= ~( FP1 | FP0 );
\r
272 pxCurrentRxDesc->status |= ACT;
\r
274 /* Move onto the next buffer in the ring. */
\r
275 pxCurrentRxDesc = pxCurrentRxDesc->next;
\r
277 if( EDMAC.EDRRR.LONG == 0x00000000L )
\r
279 /* Restart Ethernet if it has stopped */
\r
280 EDMAC.EDRRR.LONG = 0x00000001L;
\r
284 return ulBytesReceived;
\r
286 /*-----------------------------------------------------------*/
\r
288 long lEMACWaitForLink( void )
\r
292 /* Set the link status. */
\r
293 switch( phy_set_autonegotiate() )
\r
295 /* Half duplex link */
\r
296 case PHY_LINK_100H:
\r
297 ETHERC.ECMR.BIT.DM = 0;
\r
298 ETHERC.ECMR.BIT.RTM = 1;
\r
303 ETHERC.ECMR.BIT.DM = 0;
\r
304 ETHERC.ECMR.BIT.RTM = 0;
\r
309 /* Full duplex link */
\r
310 case PHY_LINK_100F:
\r
311 ETHERC.ECMR.BIT.DM = 1;
\r
312 ETHERC.ECMR.BIT.RTM = 1;
\r
317 ETHERC.ECMR.BIT.DM = 1;
\r
318 ETHERC.ECMR.BIT.RTM = 0;
\r
327 if( lReturn == pdPASS )
\r
329 /* Enable receive and transmit. */
\r
330 ETHERC.ECMR.BIT.RE = 1;
\r
331 ETHERC.ECMR.BIT.TE = 1;
\r
333 /* Enable EDMAC receive */
\r
334 EDMAC.EDRRR.LONG = 0x1;
\r
339 /*-----------------------------------------------------------*/
\r
341 static void prvInitialiseDescriptors( void )
\r
343 ethfifo *pxDescriptor;
\r
346 for( x = 0; x < emacNUM_BUFFERS; x++ )
\r
348 /* Ensure none of the buffers are shown as in use at the start. */
\r
349 ucBufferInUse[ x ] = pdFALSE;
\r
352 /* Initialise the Rx descriptors. */
\r
353 for( x = 0; x < emacNUM_RX_DESCRIPTORS; x++ )
\r
355 pxDescriptor = &( xRxDescriptors[ x ] );
\r
356 pxDescriptor->buf_p = &( xEthernetBuffers.cBuffer[ x ][ 0 ] );
\r
358 pxDescriptor->bufsize = UIP_BUFSIZE;
\r
359 pxDescriptor->size = 0;
\r
360 pxDescriptor->status = ACT;
\r
361 pxDescriptor->next = &xRxDescriptors[ x + 1 ];
\r
363 /* Mark this buffer as in use. */
\r
364 ucBufferInUse[ x ] = pdTRUE;
\r
367 /* The last descriptor points back to the start. */
\r
368 pxDescriptor->status |= DL;
\r
369 pxDescriptor->next = &xRxDescriptors[ 0 ];
\r
371 /* Initialise the Tx descriptors. */
\r
372 for( x = 0; x < emacNUM_TX_BUFFERS; x++ )
\r
374 pxDescriptor = &( xTxDescriptors[ x ] );
\r
376 /* A buffer is not allocated to the Tx descriptor until a send is
\r
377 actually required. */
\r
378 pxDescriptor->buf_p = NULL;
\r
380 pxDescriptor->bufsize = UIP_BUFSIZE;
\r
381 pxDescriptor->size = 0;
\r
382 pxDescriptor->status = 0;
\r
383 pxDescriptor->next = &xTxDescriptors[ x + 1 ];
\r
386 /* The last descriptor points back to the start. */
\r
387 pxDescriptor->status |= DL;
\r
388 pxDescriptor->next = &( xTxDescriptors[ 0 ] );
\r
390 /* Use the first Rx descriptor to start with. */
\r
391 pxCurrentRxDesc = &( xRxDescriptors[ 0 ] );
\r
393 /*-----------------------------------------------------------*/
\r
395 static unsigned char *prvGetNextBuffer( void )
\r
398 unsigned char *pucReturn = NULL;
\r
399 unsigned long ulAttempts = 0;
\r
401 while( pucReturn == NULL )
\r
403 /* Look through the buffers to find one that is not in use by
\r
405 for( x = 0; x < emacNUM_BUFFERS; x++ )
\r
407 if( ucBufferInUse[ x ] == pdFALSE )
\r
409 ucBufferInUse[ x ] = pdTRUE;
\r
410 pucReturn = ( unsigned char * ) &( xEthernetBuffers.cBuffer[ x ][ 0 ] );
\r
415 /* Was a buffer found? */
\r
416 if( pucReturn == NULL )
\r
420 if( ulAttempts >= emacBUFFER_WAIT_ATTEMPTS )
\r
425 /* Wait then look again. */
\r
426 vTaskDelay( emacBUFFER_WAIT_DELAY_ms );
\r
432 /*-----------------------------------------------------------*/
\r
434 static void prvReturnBuffer( unsigned char *pucBuffer )
\r
438 /* Return a buffer to the pool of free buffers. */
\r
439 for( ul = 0; ul < emacNUM_BUFFERS; ul++ )
\r
441 if( &( xEthernetBuffers.cBuffer[ ul ][ 0 ] ) == ( void * ) pucBuffer )
\r
443 ucBufferInUse[ ul ] = pdFALSE;
\r
448 /*-----------------------------------------------------------*/
\r
450 static void prvResetEverything( void )
\r
452 /* Temporary code just to see if this gets called. This function has not
\r
453 been implemented. */
\r
454 portDISABLE_INTERRUPTS();
\r
457 /*-----------------------------------------------------------*/
\r
459 static unsigned long prvCheckRxFifoStatus( void )
\r
461 unsigned long ulReturn = 0;
\r
463 if( ( pxCurrentRxDesc->status & ACT ) != 0 )
\r
465 /* Current descriptor is still active. */
\r
467 else if( ( pxCurrentRxDesc->status & FE ) != 0 )
\r
469 /* Frame error. Clear the error. */
\r
470 pxCurrentRxDesc->status &= ~( FP1 | FP0 | FE );
\r
471 pxCurrentRxDesc->status &= ~( RMAF | RRF | RTLF | RTSF | PRE | CERF );
\r
472 pxCurrentRxDesc->status |= ACT;
\r
473 pxCurrentRxDesc = pxCurrentRxDesc->next;
\r
475 if( EDMAC.EDRRR.LONG == 0x00000000UL )
\r
477 /* Restart Ethernet if it has stopped. */
\r
478 EDMAC.EDRRR.LONG = 0x00000001UL;
\r
483 /* The descriptor contains a frame. Because of the size of the buffers
\r
484 the frame should always be complete. */
\r
485 if( ( pxCurrentRxDesc->status & FP0 ) == FP0 )
\r
487 ulReturn = pxCurrentRxDesc->size;
\r
491 /* Do not expect to get here. */
\r
492 prvResetEverything();
\r
498 /*-----------------------------------------------------------*/
\r
500 static void prvResetMAC( void )
\r
502 /* Ensure the EtherC and EDMAC are enabled. */
\r
503 SYSTEM.MSTPCRB.BIT.MSTPB15 = 0;
\r
504 vTaskDelay( 100 / portTICK_RATE_MS );
\r
506 EDMAC.EDMR.BIT.SWR = 1;
\r
508 /* Crude wait for reset to complete. */
\r
509 vTaskDelay( 500 / portTICK_RATE_MS );
\r
511 /*-----------------------------------------------------------*/
\r
513 static void prvConfigureEtherCAndEDMAC( void )
\r
515 /* Initialisation code taken from Renesas example project. */
\r
517 /* TODO: Check bit 5 */
\r
518 ETHERC.ECSR.LONG = 0x00000037; /* Clear all ETHERC statuS BFR, PSRTO, LCHNG, MPD, ICD */
\r
520 /* Set the EDMAC interrupt priority. */
\r
521 _IPR( _ETHER_EINT ) = configKERNEL_INTERRUPT_PRIORITY;
\r
523 /* TODO: Check bit 5 */
\r
524 /* Enable interrupts of interest only. */
\r
525 EDMAC.EESIPR.LONG = emacTX_END_INTERRUPT | emacRX_END_INTERRUPT;
\r
526 ETHERC.RFLR.LONG = 1518; /* Ether payload is 1500+ CRC */
\r
527 ETHERC.IPGR.LONG = 0x00000014; /* Intergap is 96-bit time */
\r
530 EDMAC.EESR.LONG = 0x47FF0F9F; /* Clear all ETHERC and EDMAC status bits */
\r
532 EDMAC.EDMR.BIT.DE = 1;
\r
534 EDMAC.RDLAR = ( void * ) pxCurrentRxDesc; /* Initialaize Rx Descriptor List Address */
\r
535 EDMAC.TDLAR = &( xTxDescriptors[ 0 ] ); /* Initialaize Tx Descriptor List Address */
\r
536 EDMAC.TRSCER.LONG = 0x00000000; /* Copy-back status is RFE & TFE only */
\r
537 EDMAC.TFTR.LONG = 0x00000000; /* Threshold of Tx_FIFO */
\r
538 EDMAC.FDR.LONG = 0x00000000; /* Transmit fifo & receive fifo is 256 bytes */
\r
539 EDMAC.RMCR.LONG = 0x00000003; /* Receive function is normal mode(continued) */
\r
540 ETHERC.ECMR.BIT.PRM = 0; /* Ensure promiscuous mode is off. */
\r
542 /* Enable the interrupt... */
\r
543 _IEN( _ETHER_EINT ) = 1;
\r
545 /*-----------------------------------------------------------*/
\r
547 #pragma interrupt ( vEMAC_ISR_Handler( vect = VECT_ETHER_EINT, enable ) )
\r
548 void vEMAC_ISR_Handler( void )
\r
550 unsigned long ul = EDMAC.EESR.LONG;
\r
551 long lHigherPriorityTaskWoken = pdFALSE;
\r
552 extern xQueueHandle xEMACEventQueue;
\r
553 const unsigned long ulRxEvent = uipETHERNET_RX_EVENT;
\r
555 /* Has a Tx end occurred? */
\r
556 if( ul & emacTX_END_INTERRUPT )
\r
558 /* Only return the buffer to the pool once both Txes have completed. */
\r
559 prvReturnBuffer( ( void * ) xTxDescriptors[ 0 ].buf_p );
\r
560 EDMAC.EESR.LONG = emacTX_END_INTERRUPT;
\r
563 /* Has an Rx end occurred? */
\r
564 if( ul & emacRX_END_INTERRUPT )
\r
566 /* Make sure the Ethernet task is not blocked waiting for a packet. */
\r
567 xQueueSendFromISR( xEMACEventQueue, &ulRxEvent, &lHigherPriorityTaskWoken );
\r
568 portYIELD_FROM_ISR( lHigherPriorityTaskWoken );
\r
569 EDMAC.EESR.LONG = emacRX_END_INTERRUPT;
\r