2 FreeRTOS V7.4.2 - Copyright (C) 2013 Real Time Engineers Ltd.
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4 FEATURES AND PORTS ARE ADDED TO FREERTOS ALL THE TIME. PLEASE VISIT
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5 http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
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7 ***************************************************************************
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9 * FreeRTOS tutorial books are available in pdf and paperback. *
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10 * Complete, revised, and edited pdf reference manuals are also *
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13 * Purchasing FreeRTOS documentation will not only help you, by *
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14 * ensuring you get running as quickly as possible and with an *
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15 * in-depth knowledge of how to use FreeRTOS, it will also help *
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16 * the FreeRTOS project to continue with its mission of providing *
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17 * professional grade, cross platform, de facto standard solutions *
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18 * for microcontrollers - completely free of charge! *
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20 * >>> See http://www.FreeRTOS.org/Documentation for details. <<< *
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22 * Thank you for using FreeRTOS, and thank you for your support! *
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24 ***************************************************************************
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27 This file is part of the FreeRTOS distribution.
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29 FreeRTOS is free software; you can redistribute it and/or modify it under
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30 the terms of the GNU General Public License (version 2) as published by the
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31 Free Software Foundation AND MODIFIED BY the FreeRTOS exception.
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33 >>>>>>NOTE<<<<<< The modification to the GPL is included to allow you to
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34 distribute a combined work that includes FreeRTOS without being obliged to
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35 provide the source code for proprietary components outside of the FreeRTOS
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38 FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
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39 WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
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40 FOR A PARTICULAR PURPOSE. See the GNU General Public License for more
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41 details. You should have received a copy of the GNU General Public License
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42 and the FreeRTOS license exception along with FreeRTOS; if not it can be
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43 viewed here: http://www.freertos.org/a00114.html and also obtained by
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44 writing to Real Time Engineers Ltd., contact details for whom are available
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45 on the FreeRTOS WEB site.
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49 ***************************************************************************
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51 * Having a problem? Start by reading the FAQ "My application does *
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52 * not run, what could be wrong?" *
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54 * http://www.FreeRTOS.org/FAQHelp.html *
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56 ***************************************************************************
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59 http://www.FreeRTOS.org - Documentation, books, training, latest versions,
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60 license and Real Time Engineers Ltd. contact details.
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62 http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
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63 including FreeRTOS+Trace - an indispensable productivity tool, and our new
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64 fully thread aware and reentrant UDP/IP stack.
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66 http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High
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67 Integrity Systems, who sell the code with commercial support,
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68 indemnification and middleware, under the OpenRTOS brand.
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70 http://www.SafeRTOS.com - High Integrity Systems also provide a safety
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71 engineered and independently SIL3 certified version for use in safety and
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72 mission critical applications that require provable dependability.
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75 /* FreeRTOS includes. */
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76 #include "FreeRTOS.h"
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80 /* Hardware specific includes. */
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81 #include "r_ether.h"
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85 #include "net/uip.h"
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87 /* The time to wait between attempts to obtain a free buffer. */
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88 #define emacBUFFER_WAIT_DELAY_ms ( 3 / portTICK_RATE_MS )
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90 /* The number of times emacBUFFER_WAIT_DELAY_ms should be waited before giving
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91 up on attempting to obtain a free buffer all together. */
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92 #define emacBUFFER_WAIT_ATTEMPTS ( 30 )
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94 /* The number of Rx descriptors. */
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95 #define emacNUM_RX_DESCRIPTORS 8
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97 /* The number of Tx descriptors. When using uIP there is not point in having
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99 #define emacNUM_TX_BUFFERS 2
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101 /* The total number of EMAC buffers to allocate. */
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102 #define emacNUM_BUFFERS ( emacNUM_RX_DESCRIPTORS + emacNUM_TX_BUFFERS )
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104 /* The time to wait for the Tx descriptor to become free. */
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105 #define emacTX_WAIT_DELAY_ms ( 10 / portTICK_RATE_MS )
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107 /* The total number of times to wait emacTX_WAIT_DELAY_ms for the Tx descriptor to
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109 #define emacTX_WAIT_ATTEMPTS ( 50 )
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111 /* Only Rx end and Tx end interrupts are used by this driver. */
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112 #define emacTX_END_INTERRUPT ( 1UL << 21UL )
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113 #define emacRX_END_INTERRUPT ( 1UL << 18UL )
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115 /*-----------------------------------------------------------*/
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117 /* The buffers and descriptors themselves. */
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118 #pragma section _RX_DESC
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119 volatile ethfifo xRxDescriptors[ emacNUM_RX_DESCRIPTORS ];
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120 #pragma section _TX_DESC
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121 volatile ethfifo xTxDescriptors[ emacNUM_TX_BUFFERS ];
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122 #pragma section _ETHERNET_BUFFERS
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125 unsigned long ulAlignmentVariable;
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126 char cBuffer[ emacNUM_BUFFERS ][ UIP_BUFSIZE ];
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127 } xEthernetBuffers;
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133 /* Used to indicate which buffers are free and which are in use. If an index
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134 contains 0 then the corresponding buffer in xEthernetBuffers is free, otherwise
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135 the buffer is in use or about to be used. */
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136 static unsigned char ucBufferInUse[ emacNUM_BUFFERS ];
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138 /*-----------------------------------------------------------*/
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141 * Initialise both the Rx and Tx descriptors.
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143 static void prvInitialiseDescriptors( void );
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146 * Return a pointer to a free buffer within xEthernetBuffers.
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148 static unsigned char *prvGetNextBuffer( void );
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151 * Return a buffer to the list of free buffers.
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153 static void prvReturnBuffer( unsigned char *pucBuffer );
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156 * Examine the status of the next Rx FIFO to see if it contains new data.
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158 static unsigned long prvCheckRxFifoStatus( void );
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161 * Setup the microcontroller for communication with the PHY.
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163 static void prvResetMAC( void );
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166 * Configure the Ethernet interface peripherals.
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168 static void prvConfigureEtherCAndEDMAC( void );
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171 * Something has gone wrong with the descriptor usage. Reset all the buffers
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174 static void prvResetEverything( void );
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176 /*-----------------------------------------------------------*/
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178 /* Points to the Rx descriptor currently in use. */
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179 static ethfifo *pxCurrentRxDesc = NULL;
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181 /* The buffer used by the uIP stack to both receive and send. This points to
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182 one of the Ethernet buffers when its actually in use. */
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183 unsigned char *uip_buf = NULL;
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185 /*-----------------------------------------------------------*/
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187 void vInitEmac( void )
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189 /* Software reset. */
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192 /* Set the Rx and Tx descriptors into their initial state. */
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193 prvInitialiseDescriptors();
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195 /* Set the MAC address into the ETHERC */
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196 ETHERC.MAHR = ( ( unsigned long ) configMAC_ADDR0 << 24UL ) |
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197 ( ( unsigned long ) configMAC_ADDR1 << 16UL ) |
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198 ( ( unsigned long ) configMAC_ADDR2 << 8UL ) |
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199 ( unsigned long ) configMAC_ADDR3;
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201 ETHERC.MALR.BIT.MA = ( ( unsigned long ) configMAC_ADDR4 << 8UL ) |
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202 ( unsigned long ) configMAC_ADDR5;
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204 /* Perform rest of interface hardware configuration. */
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205 prvConfigureEtherCAndEDMAC();
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207 /* Nothing received yet, so uip_buf points nowhere. */
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210 /* Initialize the PHY */
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211 configASSERT( phy_init() == R_PHY_OK );
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213 /*-----------------------------------------------------------*/
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215 void vEMACWrite( void )
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219 /* Wait until the second transmission of the last packet has completed. */
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220 for( x = 0; x < emacTX_WAIT_ATTEMPTS; x++ )
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222 if( ( xTxDescriptors[ 1 ].status & ACT ) != 0 )
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224 /* Descriptor is still active. */
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225 vTaskDelay( emacTX_WAIT_DELAY_ms );
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233 /* Is the descriptor free after waiting for it? */
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234 if( ( xTxDescriptors[ 1 ].status & ACT ) != 0 )
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236 /* Something has gone wrong. */
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237 prvResetEverything();
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240 /* Setup both descriptors to transmit the frame. */
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241 xTxDescriptors[ 0 ].buf_p = ( char * ) uip_buf;
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242 xTxDescriptors[ 0 ].bufsize = uip_len;
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243 xTxDescriptors[ 1 ].buf_p = ( char * ) uip_buf;
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244 xTxDescriptors[ 1 ].bufsize = uip_len;
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246 /* uip_buf is being sent by the Tx descriptor. Allocate a new buffer
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247 for use by the stack. */
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248 uip_buf = prvGetNextBuffer();
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250 /* Clear previous settings and go. */
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251 xTxDescriptors[0].status &= ~( FP1 | FP0 );
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252 xTxDescriptors[0].status |= ( FP1 | FP0 | ACT );
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253 xTxDescriptors[1].status &= ~( FP1 | FP0 );
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254 xTxDescriptors[1].status |= ( FP1 | FP0 | ACT );
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256 EDMAC.EDTRR.LONG = 0x00000001;
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258 /*-----------------------------------------------------------*/
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260 unsigned long ulEMACRead( void )
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262 unsigned long ulBytesReceived;
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264 ulBytesReceived = prvCheckRxFifoStatus();
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266 if( ulBytesReceived > 0 )
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268 /* Mark the pxDescriptor buffer as free as uip_buf is going to be set to
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269 the buffer that contains the received data. */
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270 prvReturnBuffer( uip_buf );
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272 /* Point uip_buf to the data about ot be processed. */
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273 uip_buf = ( void * ) pxCurrentRxDesc->buf_p;
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275 /* Allocate a new buffer to the descriptor, as uip_buf is now using it's
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277 pxCurrentRxDesc->buf_p = prvGetNextBuffer();
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279 /* Prepare the descriptor to go again. */
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280 pxCurrentRxDesc->status &= ~( FP1 | FP0 );
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281 pxCurrentRxDesc->status |= ACT;
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283 /* Move onto the next buffer in the ring. */
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284 pxCurrentRxDesc = pxCurrentRxDesc->next;
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286 if( EDMAC.EDRRR.LONG == 0x00000000L )
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288 /* Restart Ethernet if it has stopped */
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289 EDMAC.EDRRR.LONG = 0x00000001L;
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293 return ulBytesReceived;
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295 /*-----------------------------------------------------------*/
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297 long lEMACWaitForLink( void )
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301 /* Set the link status. */
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302 switch( phy_set_autonegotiate() )
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304 /* Half duplex link */
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305 case PHY_LINK_100H:
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306 ETHERC.ECMR.BIT.DM = 0;
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307 ETHERC.ECMR.BIT.RTM = 1;
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312 ETHERC.ECMR.BIT.DM = 0;
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313 ETHERC.ECMR.BIT.RTM = 0;
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318 /* Full duplex link */
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319 case PHY_LINK_100F:
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320 ETHERC.ECMR.BIT.DM = 1;
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321 ETHERC.ECMR.BIT.RTM = 1;
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326 ETHERC.ECMR.BIT.DM = 1;
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327 ETHERC.ECMR.BIT.RTM = 0;
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336 if( lReturn == pdPASS )
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338 /* Enable receive and transmit. */
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339 ETHERC.ECMR.BIT.RE = 1;
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340 ETHERC.ECMR.BIT.TE = 1;
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342 /* Enable EDMAC receive */
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343 EDMAC.EDRRR.LONG = 0x1;
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348 /*-----------------------------------------------------------*/
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350 static void prvInitialiseDescriptors( void )
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352 ethfifo *pxDescriptor;
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355 for( x = 0; x < emacNUM_BUFFERS; x++ )
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357 /* Ensure none of the buffers are shown as in use at the start. */
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358 ucBufferInUse[ x ] = pdFALSE;
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361 /* Initialise the Rx descriptors. */
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362 for( x = 0; x < emacNUM_RX_DESCRIPTORS; x++ )
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364 pxDescriptor = &( xRxDescriptors[ x ] );
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365 pxDescriptor->buf_p = &( xEthernetBuffers.cBuffer[ x ][ 0 ] );
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367 pxDescriptor->bufsize = UIP_BUFSIZE;
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368 pxDescriptor->size = 0;
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369 pxDescriptor->status = ACT;
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370 pxDescriptor->next = &xRxDescriptors[ x + 1 ];
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372 /* Mark this buffer as in use. */
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373 ucBufferInUse[ x ] = pdTRUE;
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376 /* The last descriptor points back to the start. */
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377 pxDescriptor->status |= DL;
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378 pxDescriptor->next = &xRxDescriptors[ 0 ];
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380 /* Initialise the Tx descriptors. */
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381 for( x = 0; x < emacNUM_TX_BUFFERS; x++ )
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383 pxDescriptor = &( xTxDescriptors[ x ] );
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385 /* A buffer is not allocated to the Tx descriptor until a send is
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386 actually required. */
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387 pxDescriptor->buf_p = NULL;
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389 pxDescriptor->bufsize = UIP_BUFSIZE;
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390 pxDescriptor->size = 0;
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391 pxDescriptor->status = 0;
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392 pxDescriptor->next = &xTxDescriptors[ x + 1 ];
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395 /* The last descriptor points back to the start. */
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396 pxDescriptor->status |= DL;
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397 pxDescriptor->next = &( xTxDescriptors[ 0 ] );
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399 /* Use the first Rx descriptor to start with. */
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400 pxCurrentRxDesc = &( xRxDescriptors[ 0 ] );
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402 /*-----------------------------------------------------------*/
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404 static unsigned char *prvGetNextBuffer( void )
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407 unsigned char *pucReturn = NULL;
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408 unsigned long ulAttempts = 0;
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410 while( pucReturn == NULL )
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412 /* Look through the buffers to find one that is not in use by
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414 for( x = 0; x < emacNUM_BUFFERS; x++ )
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416 if( ucBufferInUse[ x ] == pdFALSE )
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418 ucBufferInUse[ x ] = pdTRUE;
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419 pucReturn = ( unsigned char * ) &( xEthernetBuffers.cBuffer[ x ][ 0 ] );
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424 /* Was a buffer found? */
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425 if( pucReturn == NULL )
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429 if( ulAttempts >= emacBUFFER_WAIT_ATTEMPTS )
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434 /* Wait then look again. */
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435 vTaskDelay( emacBUFFER_WAIT_DELAY_ms );
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441 /*-----------------------------------------------------------*/
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443 static void prvReturnBuffer( unsigned char *pucBuffer )
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447 /* Return a buffer to the pool of free buffers. */
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448 for( ul = 0; ul < emacNUM_BUFFERS; ul++ )
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450 if( &( xEthernetBuffers.cBuffer[ ul ][ 0 ] ) == ( void * ) pucBuffer )
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452 ucBufferInUse[ ul ] = pdFALSE;
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457 /*-----------------------------------------------------------*/
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459 static void prvResetEverything( void )
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461 /* Temporary code just to see if this gets called. This function has not
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462 been implemented. */
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463 portDISABLE_INTERRUPTS();
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466 /*-----------------------------------------------------------*/
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468 static unsigned long prvCheckRxFifoStatus( void )
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470 unsigned long ulReturn = 0;
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472 if( ( pxCurrentRxDesc->status & ACT ) != 0 )
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474 /* Current descriptor is still active. */
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476 else if( ( pxCurrentRxDesc->status & FE ) != 0 )
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478 /* Frame error. Clear the error. */
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479 pxCurrentRxDesc->status &= ~( FP1 | FP0 | FE );
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480 pxCurrentRxDesc->status &= ~( RMAF | RRF | RTLF | RTSF | PRE | CERF );
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481 pxCurrentRxDesc->status |= ACT;
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482 pxCurrentRxDesc = pxCurrentRxDesc->next;
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484 if( EDMAC.EDRRR.LONG == 0x00000000UL )
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486 /* Restart Ethernet if it has stopped. */
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487 EDMAC.EDRRR.LONG = 0x00000001UL;
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492 /* The descriptor contains a frame. Because of the size of the buffers
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493 the frame should always be complete. */
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494 if( ( pxCurrentRxDesc->status & FP0 ) == FP0 )
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496 ulReturn = pxCurrentRxDesc->size;
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500 /* Do not expect to get here. */
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501 prvResetEverything();
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507 /*-----------------------------------------------------------*/
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509 static void prvResetMAC( void )
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511 /* Ensure the EtherC and EDMAC are enabled. */
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512 SYSTEM.MSTPCRB.BIT.MSTPB15 = 0;
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513 vTaskDelay( 100 / portTICK_RATE_MS );
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515 EDMAC.EDMR.BIT.SWR = 1;
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517 /* Crude wait for reset to complete. */
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518 vTaskDelay( 500 / portTICK_RATE_MS );
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520 /*-----------------------------------------------------------*/
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522 static void prvConfigureEtherCAndEDMAC( void )
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524 /* Initialisation code taken from Renesas example project. */
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526 /* TODO: Check bit 5 */
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527 ETHERC.ECSR.LONG = 0x00000037; /* Clear all ETHERC statuS BFR, PSRTO, LCHNG, MPD, ICD */
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529 /* Set the EDMAC interrupt priority. */
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530 _IPR( _ETHER_EINT ) = configKERNEL_INTERRUPT_PRIORITY;
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532 /* TODO: Check bit 5 */
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533 /* Enable interrupts of interest only. */
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534 EDMAC.EESIPR.LONG = emacTX_END_INTERRUPT | emacRX_END_INTERRUPT;
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535 ETHERC.RFLR.LONG = 1518; /* Ether payload is 1500+ CRC */
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536 ETHERC.IPGR.LONG = 0x00000014; /* Intergap is 96-bit time */
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539 EDMAC.EESR.LONG = 0x47FF0F9F; /* Clear all ETHERC and EDMAC status bits */
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541 EDMAC.EDMR.BIT.DE = 1;
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543 EDMAC.RDLAR = ( void * ) pxCurrentRxDesc; /* Initialaize Rx Descriptor List Address */
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544 EDMAC.TDLAR = &( xTxDescriptors[ 0 ] ); /* Initialaize Tx Descriptor List Address */
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545 EDMAC.TRSCER.LONG = 0x00000000; /* Copy-back status is RFE & TFE only */
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546 EDMAC.TFTR.LONG = 0x00000000; /* Threshold of Tx_FIFO */
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547 EDMAC.FDR.LONG = 0x00000000; /* Transmit fifo & receive fifo is 256 bytes */
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548 EDMAC.RMCR.LONG = 0x00000003; /* Receive function is normal mode(continued) */
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549 ETHERC.ECMR.BIT.PRM = 0; /* Ensure promiscuous mode is off. */
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551 /* Enable the interrupt... */
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552 _IEN( _ETHER_EINT ) = 1;
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554 /*-----------------------------------------------------------*/
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556 #pragma interrupt ( vEMAC_ISR_Handler( vect = VECT_ETHER_EINT, enable ) )
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557 void vEMAC_ISR_Handler( void )
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559 unsigned long ul = EDMAC.EESR.LONG;
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560 long lHigherPriorityTaskWoken = pdFALSE;
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561 extern xQueueHandle xEMACEventQueue;
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562 const unsigned long ulRxEvent = uipETHERNET_RX_EVENT;
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564 /* Has a Tx end occurred? */
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565 if( ul & emacTX_END_INTERRUPT )
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567 /* Only return the buffer to the pool once both Txes have completed. */
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568 prvReturnBuffer( ( void * ) xTxDescriptors[ 0 ].buf_p );
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569 EDMAC.EESR.LONG = emacTX_END_INTERRUPT;
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572 /* Has an Rx end occurred? */
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573 if( ul & emacRX_END_INTERRUPT )
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575 /* Make sure the Ethernet task is not blocked waiting for a packet. */
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576 xQueueSendFromISR( xEMACEventQueue, &ulRxEvent, &lHigherPriorityTaskWoken );
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577 portYIELD_FROM_ISR( lHigherPriorityTaskWoken );
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578 EDMAC.EESR.LONG = emacRX_END_INTERRUPT;
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