2 * FreeRTOS Kernel V10.3.0
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3 * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
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5 * Permission is hereby granted, free of charge, to any person obtaining a copy of
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6 * this software and associated documentation files (the "Software"), to deal in
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7 * the Software without restriction, including without limitation the rights to
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8 * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
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9 * the Software, and to permit persons to whom the Software is furnished to do so,
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10 * subject to the following conditions:
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12 * The above copyright notice and this permission notice shall be included in all
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13 * copies or substantial portions of the Software.
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15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
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17 * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
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18 * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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19 * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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20 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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22 * http://www.FreeRTOS.org
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23 * http://aws.amazon.com/freertos
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25 * 1 tab == 4 spaces!
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29 * This file contains the non-portable and therefore RX64M specific parts of
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30 * the IntQueue standard demo task - namely the configuration of the timers
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31 * that generate the interrupts and the interrupt entry points.
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34 /* Scheduler includes. */
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35 #include "FreeRTOS.h"
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38 /* Demo includes. */
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39 #include "IntQueueTimer.h"
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40 #include "IntQueue.h"
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42 /* Hardware specifics. */
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43 #include "iodefine.h"
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44 #include "rskrx64mdef.h"
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46 #define IPR_PERIB_INTB128 128
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47 #define IPR_PERIB_INTB129 129
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48 #define IER_PERIB_INTB128 0x10
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49 #define IER_PERIB_INTB129 0x10
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50 #define IEN_PERIB_INTB128 IEN0
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51 #define IEN_PERIB_INTB129 IEN1
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52 #define IR_PERIB_INTB128 128
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53 #define IR_PERIB_INTB129 129
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55 void vIntQTimerISR0( void ) __attribute__ ((interrupt));
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56 void vIntQTimerISR1( void ) __attribute__ ((interrupt));
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58 #define tmrTIMER_0_1_FREQUENCY ( 2000UL )
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59 #define tmrTIMER_2_3_FREQUENCY ( 2001UL )
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61 void vInitialiseTimerForIntQueueTest( void )
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63 /* Ensure interrupts do not start until full configuration is complete. */
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64 portENTER_CRITICAL();
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66 /* Give write access. */
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67 SYSTEM.PRCR.WORD = 0xa502;
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69 /* Cascade two 8bit timer channels to generate the interrupts.
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70 8bit timer unit 1 (TMR0 and TMR1) and 8bit timer unit 2 (TMR2 and TMR3 are
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71 utilised for this test. */
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73 /* Enable the timers. */
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74 SYSTEM.MSTPCRA.BIT.MSTPA5 = 0;
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75 SYSTEM.MSTPCRA.BIT.MSTPA4 = 0;
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77 /* Enable compare match A interrupt request. */
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78 TMR0.TCR.BIT.CMIEA = 1;
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79 TMR2.TCR.BIT.CMIEA = 1;
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81 /* Clear the timer on compare match A. */
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82 TMR0.TCR.BIT.CCLR = 1;
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83 TMR2.TCR.BIT.CCLR = 1;
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85 /* Set the compare match value. */
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86 TMR01.TCORA = ( unsigned short ) ( ( ( configPERIPHERAL_CLOCK_HZ / tmrTIMER_0_1_FREQUENCY ) -1 ) / 8 );
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87 TMR23.TCORA = ( unsigned short ) ( ( ( configPERIPHERAL_CLOCK_HZ / tmrTIMER_0_1_FREQUENCY ) -1 ) / 8 );
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89 /* 16 bit operation ( count from timer 1,2 ). */
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90 TMR0.TCCR.BIT.CSS = 3;
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91 TMR2.TCCR.BIT.CSS = 3;
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93 /* Use PCLK as the input. */
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94 TMR1.TCCR.BIT.CSS = 1;
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95 TMR3.TCCR.BIT.CSS = 1;
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97 /* Divide PCLK by 8. */
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98 TMR1.TCCR.BIT.CKS = 2;
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99 TMR3.TCCR.BIT.CKS = 2;
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101 /* Enable TMR 0, 2 interrupts. */
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102 TMR0.TCR.BIT.CMIEA = 1;
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103 TMR2.TCR.BIT.CMIEA = 1;
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105 /* Map TMR0 CMIA0 interrupt to vector slot B number 128 and set
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106 priority above the kernel's priority, but below the max syscall
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108 ICU.SLIBXR128.BYTE = 3; /* Three is TMR0 compare match A. */
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109 IPR( PERIB, INTB128 ) = configMAX_SYSCALL_INTERRUPT_PRIORITY - 1;
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110 IEN( PERIB, INTB128 ) = 1;
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112 /* Ensure that the flag is set to 0, otherwise the interrupt will not be
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114 IR( PERIB, INTB128 ) = 0;
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116 /* Do the same for TMR2, but to vector 129. */
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117 ICU.SLIBXR129.BYTE = 9; /* Nine is TMR2 compare match A. */
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118 IPR( PERIB, INTB129 ) = configMAX_SYSCALL_INTERRUPT_PRIORITY - 2;
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119 IEN( PERIB, INTB129 ) = 1;
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120 IR( PERIB, INTB129 ) = 0;
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122 portEXIT_CRITICAL();
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124 /*-----------------------------------------------------------*/
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126 /* On vector 128. */
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127 void vIntQTimerISR0( void )
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129 /* Enable interrupts to allow interrupt nesting. */
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130 __asm volatile( "setpsw i" );
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132 portYIELD_FROM_ISR( xFirstTimerHandler() );
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134 /*-----------------------------------------------------------*/
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136 /* On vector 129. */
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137 void vIntQTimerISR1( void )
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139 /* Enable interrupts to allow interrupt nesting. */
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140 __asm volatile( "setpsw i" );
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142 portYIELD_FROM_ISR( xSecondTimerHandler() );
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