2 * FreeRTOS Kernel V10.2.1
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3 * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.
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5 * Permission is hereby granted, free of charge, to any person obtaining a copy of
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6 * this software and associated documentation files (the "Software"), to deal in
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7 * the Software without restriction, including without limitation the rights to
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8 * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
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9 * the Software, and to permit persons to whom the Software is furnished to do so,
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10 * subject to the following conditions:
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12 * The above copyright notice and this permission notice shall be included in all
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13 * copies or substantial portions of the Software.
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15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
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17 * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
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18 * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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19 * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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20 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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22 * http://www.FreeRTOS.org
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23 * http://aws.amazon.com/freertos
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25 * 1 tab == 4 spaces!
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29 * This file contains the non-portable and therefore RX specific parts of the
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30 * IntQueue standard demo task - namely the configuration of the timers that
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31 * generate the interrupts and the interrupt entry points.
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34 /* Scheduler includes. */
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35 #include "FreeRTOS.h"
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38 /* Demo includes. */
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39 #include "IntQueueTimer.h"
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40 #include "IntQueue.h"
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42 #define tmrTIMER_0_1_FREQUENCY ( 2000UL )
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43 #define tmrTIMER_2_3_FREQUENCY ( 2301UL )
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45 void vInitialiseTimerForIntQueueTest( void )
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47 /* Ensure interrupts do not start until full configuration is complete. */
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48 portENTER_CRITICAL();
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50 /* Give write access. */
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51 SYSTEM.PRCR.WORD = 0xa502;
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53 /* Cascade two 8bit timer channels to generate the interrupts.
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54 8bit timer unit 1 (TMR0 and TMR1) and 8bit timer unit 2 (TMR2 and TMR3 are
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55 utilised for this test. */
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57 /* Enable the timers. */
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58 SYSTEM.MSTPCRA.BIT.MSTPA5 = 0;
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59 SYSTEM.MSTPCRA.BIT.MSTPA4 = 0;
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61 /* Enable compare match A interrupt request. */
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62 TMR0.TCR.BIT.CMIEA = 1;
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63 TMR2.TCR.BIT.CMIEA = 1;
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65 /* Clear the timer on compare match A. */
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66 TMR0.TCR.BIT.CCLR = 1;
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67 TMR2.TCR.BIT.CCLR = 1;
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69 /* Set the compare match value. */
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70 TMR01.TCORA = ( unsigned short ) ( ( ( configPERIPHERAL_CLOCK_HZ / tmrTIMER_0_1_FREQUENCY ) -1 ) / 8 );
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71 TMR23.TCORA = ( unsigned short ) ( ( ( configPERIPHERAL_CLOCK_HZ / tmrTIMER_0_1_FREQUENCY ) -1 ) / 8 );
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73 /* 16 bit operation ( count from timer 1,2 ). */
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74 TMR0.TCCR.BIT.CSS = 3;
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75 TMR2.TCCR.BIT.CSS = 3;
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77 /* Use PCLK as the input. */
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78 TMR1.TCCR.BIT.CSS = 1;
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79 TMR3.TCCR.BIT.CSS = 1;
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81 /* Divide PCLK by 8. */
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82 TMR1.TCCR.BIT.CKS = 2;
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83 TMR3.TCCR.BIT.CKS = 2;
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85 /* Enable TMR 0, 2 interrupts. */
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86 TMR0.TCR.BIT.CMIEA = 1;
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87 TMR2.TCR.BIT.CMIEA = 1;
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89 /* Set priority and enable interrupt. */
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90 ICU.SLIBXR128.BYTE = 3; /* Three is TMR0 compare match A. */
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91 IPR( PERIB, INTB128 ) = configMAX_SYSCALL_INTERRUPT_PRIORITY - 1;
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92 IEN( PERIB, INTB128 ) = 1;
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94 /* Ensure that the flag is set to 0, otherwise the interrupt will not be
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96 IR( PERIB, INTB128 ) = 0;
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98 /* Do the same for TMR2, but to vector 129. */
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99 ICU.SLIBXR129.BYTE = 9; /* Nine is TMR2 compare match A. */
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100 IPR( PERIB, INTB129 ) = configMAX_SYSCALL_INTERRUPT_PRIORITY - 2;
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101 IEN( PERIB, INTB129 ) = 1;
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102 IR( PERIB, INTB129 ) = 0;
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104 portEXIT_CRITICAL();
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106 /*-----------------------------------------------------------*/
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110 void vIntQTimerISR0( void ) __attribute__ ((interrupt));
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111 void vIntQTimerISR1( void ) __attribute__ ((interrupt));
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113 void vIntQTimerISR0( void )
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115 /* Enable interrupts to allow interrupt nesting. */
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116 __asm volatile( "setpsw i" );
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118 portYIELD_FROM_ISR( xFirstTimerHandler() );
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120 /*-----------------------------------------------------------*/
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122 void vIntQTimerISR1( void )
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124 /* Enable interrupts to allow interrupt nesting. */
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125 __asm volatile( "setpsw i" );
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127 portYIELD_FROM_ISR( xSecondTimerHandler() );
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130 #endif /* __GNUC__ */
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131 /*-----------------------------------------------------------*/
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135 #pragma vector = VECT_PERIB_INTB128
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136 __interrupt void vT0_1InterruptHandler( void )
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138 __enable_interrupt();
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139 portYIELD_FROM_ISR( xFirstTimerHandler() );
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141 /*-----------------------------------------------------------*/
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143 #pragma vector = VECT_PERIB_INTB129
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144 __interrupt void vT2_3InterruptHandler( void )
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146 __enable_interrupt();
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147 portYIELD_FROM_ISR( xSecondTimerHandler() );
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150 #endif /* __ICCRX__ */
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