2 FreeRTOS V8.2.2 - Copyright (C) 2015 Real Time Engineers Ltd.
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5 VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
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7 This file is part of the FreeRTOS distribution.
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9 FreeRTOS is free software; you can redistribute it and/or modify it under
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10 the terms of the GNU General Public License (version 2) as published by the
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11 Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.
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13 ***************************************************************************
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14 >>! NOTE: The modification to the GPL is included to allow you to !<<
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15 >>! distribute a combined work that includes FreeRTOS without being !<<
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16 >>! obliged to provide the source code for proprietary components !<<
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17 >>! outside of the FreeRTOS kernel. !<<
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18 ***************************************************************************
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20 FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
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21 WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
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22 FOR A PARTICULAR PURPOSE. Full license text is available on the following
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23 link: http://www.freertos.org/a00114.html
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25 ***************************************************************************
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27 * FreeRTOS provides completely free yet professionally developed, *
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28 * robust, strictly quality controlled, supported, and cross *
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29 * platform software that is more than just the market leader, it *
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30 * is the industry's de facto standard. *
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32 * Help yourself get started quickly while simultaneously helping *
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33 * to support the FreeRTOS project by purchasing a FreeRTOS *
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34 * tutorial book, reference manual, or both: *
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35 * http://www.FreeRTOS.org/Documentation *
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37 ***************************************************************************
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39 http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading
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40 the FAQ page "My application does not run, what could be wrong?". Have you
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41 defined configASSERT()?
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43 http://www.FreeRTOS.org/support - In return for receiving this top quality
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44 embedded software for free we request you assist our global community by
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45 participating in the support forum.
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47 http://www.FreeRTOS.org/training - Investing in training allows your team to
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48 be as productive as possible as early as possible. Now you can receive
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49 FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers
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50 Ltd, and the world's leading authority on the world's leading RTOS.
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52 http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
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53 including FreeRTOS+Trace - an indispensable productivity tool, a DOS
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54 compatible FAT file system, and our tiny thread aware UDP/IP stack.
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56 http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.
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57 Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.
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59 http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High
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60 Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS
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61 licenses offer ticketed support, indemnification and commercial middleware.
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63 http://www.SafeRTOS.com - High Integrity Systems also provide a safety
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64 engineered and independently SIL3 certified version for use in safety and
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65 mission critical applications that require provable dependability.
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71 * This file contains the non-portable and therefore RX62N specific parts of
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72 * the IntQueue standard demo task - namely the configuration of the timers
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73 * that generate the interrupts and the interrupt entry points.
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76 /* Scheduler includes. */
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77 #include "FreeRTOS.h"
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80 /* Demo includes. */
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81 #include "IntQueueTimer.h"
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82 #include "IntQueue.h"
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84 /* Hardware specifics. */
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85 #include "iodefine.h"
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87 #define IPR_PERIB_INTB128 128
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88 #define IPR_PERIB_INTB129 129
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89 #define IER_PERIB_INTB128 0x10
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90 #define IER_PERIB_INTB129 0x10
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91 #define IEN_PERIB_INTB128 IEN0
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92 #define IEN_PERIB_INTB129 IEN1
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93 #define IR_PERIB_INTB128 128
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94 #define IR_PERIB_INTB129 129
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96 void vIntQTimerISR0( void ) __attribute__ ((interrupt));
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97 void vIntQTimerISR1( void ) __attribute__ ((interrupt));
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99 #define tmrTIMER_0_1_FREQUENCY ( 2000UL )
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100 #define tmrTIMER_2_3_FREQUENCY ( 2001UL )
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102 void vInitialiseTimerForIntQueueTest( void )
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104 /* Ensure interrupts do not start until full configuration is complete. */
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105 portENTER_CRITICAL();
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107 /* Give write access. */
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108 SYSTEM.PRCR.WORD = 0xa502;
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110 /* Cascade two 8bit timer channels to generate the interrupts.
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111 8bit timer unit 1 (TMR0 and TMR1) and 8bit timer unit 2 (TMR2 and TMR3 are
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112 utilised for this test. */
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114 /* Enable the timers. */
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115 SYSTEM.MSTPCRA.BIT.MSTPA5 = 0;
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116 SYSTEM.MSTPCRA.BIT.MSTPA4 = 0;
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118 /* Enable compare match A interrupt request. */
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119 TMR0.TCR.BIT.CMIEA = 1;
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120 TMR2.TCR.BIT.CMIEA = 1;
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122 /* Clear the timer on compare match A. */
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123 TMR0.TCR.BIT.CCLR = 1;
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124 TMR2.TCR.BIT.CCLR = 1;
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126 /* Set the compare match value. */
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127 TMR01.TCORA = ( unsigned short ) ( ( ( configPERIPHERAL_CLOCK_HZ / tmrTIMER_0_1_FREQUENCY ) -1 ) / 8 );
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128 TMR23.TCORA = ( unsigned short ) ( ( ( configPERIPHERAL_CLOCK_HZ / tmrTIMER_0_1_FREQUENCY ) -1 ) / 8 );
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130 /* 16 bit operation ( count from timer 1,2 ). */
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131 TMR0.TCCR.BIT.CSS = 3;
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132 TMR2.TCCR.BIT.CSS = 3;
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134 /* Use PCLK as the input. */
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135 TMR1.TCCR.BIT.CSS = 1;
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136 TMR3.TCCR.BIT.CSS = 1;
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138 /* Divide PCLK by 8. */
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139 TMR1.TCCR.BIT.CKS = 2;
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140 TMR3.TCCR.BIT.CKS = 2;
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142 /* Enable TMR 0, 2 interrupts. */
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143 TMR0.TCR.BIT.CMIEA = 1;
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144 TMR2.TCR.BIT.CMIEA = 1;
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146 /* Map TMR0 CMIA0 interrupt to vector slot B number 128 and set
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147 priority above the kernel's priority, but below the max syscall
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149 ICU.SLIBXR128.BYTE = 3; /* Three is TMR0 compare match A. */
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150 IPR( PERIB, INTB128 ) = configMAX_SYSCALL_INTERRUPT_PRIORITY - 1;
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151 IEN( PERIB, INTB128 ) = 1;
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153 /* Ensure that the flag is set to 0, otherwise the interrupt will not be
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155 IR( PERIB, INTB128 ) = 0;
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157 /* Do the same for TMR2, but to vector 129. */
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158 ICU.SLIBXR129.BYTE = 9; /* Nine is TMR2 compare match A. */
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159 IPR( PERIB, INTB129 ) = configMAX_SYSCALL_INTERRUPT_PRIORITY - 2;
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160 IEN( PERIB, INTB129 ) = 1;
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161 IR( PERIB, INTB129 ) = 0;
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163 portEXIT_CRITICAL();
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165 /*-----------------------------------------------------------*/
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167 /* On vector 128. */
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168 void vIntQTimerISR0( void )
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170 /* Enable interrupts to allow interrupt nesting. */
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171 __asm volatile( "setpsw i" );
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173 portYIELD_FROM_ISR( xFirstTimerHandler() );
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175 /*-----------------------------------------------------------*/
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177 /* On vector 129. */
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178 void vIntQTimerISR1( void )
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180 /* Enable interrupts to allow interrupt nesting. */
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181 __asm volatile( "setpsw i" );
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183 portYIELD_FROM_ISR( xSecondTimerHandler() );
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