1 /******************************************************************************
\r
4 * This software is supplied by Renesas Technology Corp. and is only
\r
5 * intended for use with Renesas products. No other uses are authorized.
\r
7 * This software is owned by Renesas Technology Corp. and is protected under
\r
8 * all applicable laws, including copyright laws.
\r
10 * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES
\r
11 * REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY,
\r
12 * INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
\r
13 * PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY
\r
16 * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
\r
17 * TECHNOLOGY CORP. NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
\r
18 * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES
\r
19 * FOR ANY REASON RELATED TO THE THIS SOFTWARE, EVEN IF RENESAS OR ITS
\r
20 * AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
\r
22 * Renesas reserves the right, without notice, to make changes to this
\r
23 * software and to discontinue the availability of this software.
\r
24 * By using this software, you agree to the additional terms and
\r
25 * conditions found by accessing the following link:
\r
26 * http://www.renesas.com/disclaimer
\r
27 ********************************************************************************
\r
28 * Copyright (C) 2009. Renesas Technology Corp., All Rights Reserved.
\r
29 *""FILE COMMENT""*********** Technical reference data **************************
\r
30 * System Name : SH7216 Sample Program
\r
31 * File Name : vect.h
\r
32 * Abstract : Definition of Vector
\r
35 * Tool-Chain : High-performance Embedded Workshop (Ver.4.05.01).
\r
36 * : C/C++ compiler package for the SuperH RISC engine family
\r
37 * : (Ver.9.03 Release00).
\r
39 * H/W Platform: R0K572167 (CPU board)
\r
41 ********************************************************************************
\r
42 * History : Mar.30,2009 Ver.0.02.00
\r
43 *""FILE COMMENT END""**********************************************************/
\r
48 //;<<VECTOR DATA START (POWER ON RESET)>>
\r
49 // 0 Power On Reset PC
\r
50 extern void PowerON_Reset_PC(void);
\r
52 //;<<VECTOR DATA END (POWER ON RESET)>>
\r
53 // 1 Power On Reset SP
\r
55 //;<<VECTOR DATA START (MANUAL RESET)>>
\r
56 // 2 Manual Reset PC
\r
57 extern void Manual_Reset_PC(void);
\r
59 //;<<VECTOR DATA END (MANUAL RESET)>>
\r
60 // 3 Manual Reset SP
\r
63 #pragma interrupt INT_Illegal_code
\r
64 extern void INT_Illegal_code(void);
\r
69 #pragma interrupt INT_Illegal_slot
\r
70 extern void INT_Illegal_slot(void);
\r
76 // 9 CPU Address error
\r
77 #pragma interrupt INT_CPU_Address
\r
78 extern void INT_CPU_Address(void);
\r
80 // 10 DMAC Address error
\r
81 #pragma interrupt INT_DMAC_Address
\r
82 extern void INT_DMAC_Address(void);
\r
85 #pragma interrupt INT_NMI
\r
86 extern void INT_NMI(void);
\r
88 // 12 User breakpoint trap
\r
89 #pragma interrupt INT_User_Break
\r
90 extern void INT_User_Break(void);
\r
95 #pragma interrupt INT_HUDI
\r
96 extern void INT_HUDI(void);
\r
98 // 15 Register bank over
\r
99 #pragma interrupt INT_Bank_Overflow
\r
100 extern void INT_Bank_Overflow(void);
\r
102 // 16 Register bank under
\r
103 #pragma interrupt INT_Bank_Underflow
\r
104 extern void INT_Bank_Underflow(void);
\r
107 #pragma interrupt INT_Divide_by_Zero
\r
108 extern void INT_Divide_by_Zero(void);
\r
111 #pragma interrupt INT_Divide_Overflow
\r
112 extern void INT_Divide_Overflow(void);
\r
140 // 32 TRAPA (User Vecter)
\r
141 #pragma interrupt INT_TRAPA32
\r
142 extern void INT_TRAPA32(void);
\r
144 // 33 TRAPA (User Vecter)
\r
145 #pragma interrupt INT_TRAPA33
\r
146 extern void INT_TRAPA33(void);
\r
148 // 34 TRAPA (User Vecter)
\r
149 #pragma interrupt INT_TRAPA34
\r
150 extern void INT_TRAPA34(void);
\r
152 // 35 TRAPA (User Vecter)
\r
153 #pragma interrupt INT_TRAPA35
\r
154 extern void INT_TRAPA35(void);
\r
156 // 36 TRAPA (User Vecter)
\r
157 #pragma interrupt INT_TRAPA36
\r
158 extern void INT_TRAPA36(void);
\r
160 // 37 TRAPA (User Vecter)
\r
161 #pragma interrupt INT_TRAPA37
\r
162 extern void INT_TRAPA37(void);
\r
164 // 38 TRAPA (User Vecter)
\r
165 #pragma interrupt INT_TRAPA38
\r
166 extern void INT_TRAPA38(void);
\r
168 // 39 TRAPA (User Vecter)
\r
169 #pragma interrupt INT_TRAPA39
\r
170 extern void INT_TRAPA39(void);
\r
172 // 40 TRAPA (User Vecter)
\r
173 #pragma interrupt INT_TRAPA40
\r
174 extern void INT_TRAPA40(void);
\r
176 // 41 TRAPA (User Vecter)
\r
177 #pragma interrupt INT_TRAPA41
\r
178 extern void INT_TRAPA41(void);
\r
180 // 42 TRAPA (User Vecter)
\r
181 #pragma interrupt INT_TRAPA42
\r
182 extern void INT_TRAPA42(void);
\r
184 // 43 TRAPA (User Vecter)
\r
185 #pragma interrupt INT_TRAPA43
\r
186 extern void INT_TRAPA43(void);
\r
188 // 44 TRAPA (User Vecter)
\r
189 #pragma interrupt INT_TRAPA44
\r
190 extern void INT_TRAPA44(void);
\r
192 // 45 TRAPA (User Vecter)
\r
193 #pragma interrupt INT_TRAPA45
\r
194 extern void INT_TRAPA45(void);
\r
196 // 46 TRAPA (User Vecter)
\r
197 #pragma interrupt INT_TRAPA46
\r
198 extern void INT_TRAPA46(void);
\r
200 // 47 TRAPA (User Vecter)
\r
201 #pragma interrupt INT_TRAPA47
\r
202 extern void INT_TRAPA47(void);
\r
204 // 48 TRAPA (User Vecter)
\r
205 #pragma interrupt INT_TRAPA48
\r
206 extern void INT_TRAPA48(void);
\r
208 // 49 TRAPA (User Vecter)
\r
209 #pragma interrupt INT_TRAPA49
\r
210 extern void INT_TRAPA49(void);
\r
212 // 50 TRAPA (User Vecter)
\r
213 #pragma interrupt INT_TRAPA50
\r
214 extern void INT_TRAPA50(void);
\r
216 // 51 TRAPA (User Vecter)
\r
217 #pragma interrupt INT_TRAPA51
\r
218 extern void INT_TRAPA51(void);
\r
220 // 52 TRAPA (User Vecter)
\r
221 #pragma interrupt INT_TRAPA52
\r
222 extern void INT_TRAPA52(void);
\r
224 // 53 TRAPA (User Vecter)
\r
225 #pragma interrupt INT_TRAPA53
\r
226 extern void INT_TRAPA53(void);
\r
228 // 54 TRAPA (User Vecter)
\r
229 #pragma interrupt INT_TRAPA54
\r
230 extern void INT_TRAPA54(void);
\r
232 // 55 TRAPA (User Vecter)
\r
233 #pragma interrupt INT_TRAPA55
\r
234 extern void INT_TRAPA55(void);
\r
236 // 56 TRAPA (User Vecter)
\r
237 #pragma interrupt INT_TRAPA56
\r
238 extern void INT_TRAPA56(void);
\r
240 // 57 TRAPA (User Vecter)
\r
241 #pragma interrupt INT_TRAPA57
\r
242 extern void INT_TRAPA57(void);
\r
244 // 58 TRAPA (User Vecter)
\r
245 #pragma interrupt INT_TRAPA58
\r
246 extern void INT_TRAPA58(void);
\r
248 // 59 TRAPA (User Vecter)
\r
249 #pragma interrupt INT_TRAPA59
\r
250 extern void INT_TRAPA59(void);
\r
252 // 60 TRAPA (User Vecter)
\r
253 #pragma interrupt INT_TRAPA60
\r
254 extern void INT_TRAPA60(void);
\r
256 // 61 TRAPA (User Vecter)
\r
257 #pragma interrupt INT_TRAPA61
\r
258 extern void INT_TRAPA61(void);
\r
260 // 62 TRAPA (User Vecter)
\r
261 #pragma interrupt INT_TRAPA62
\r
262 extern void INT_TRAPA62(void);
\r
264 // 63 TRAPA (User Vecter)
\r
265 #pragma interrupt INT_TRAPA63
\r
266 extern void INT_TRAPA63(void);
\r
268 // 64 Interrupt IRQ0
\r
269 #pragma interrupt INT_IRQ0(resbank)
\r
270 extern void INT_IRQ0(void);
\r
272 // 65 Interrupt IRQ1
\r
273 #pragma interrupt INT_IRQ1(resbank)
\r
274 extern void INT_IRQ1(void);
\r
276 // 66 Interrupt IRQ2
\r
277 #pragma interrupt INT_IRQ2(resbank)
\r
278 extern void INT_IRQ2(void);
\r
280 // 67 Interrupt IRQ3
\r
281 #pragma interrupt INT_IRQ3(resbank)
\r
282 extern void INT_IRQ3(void);
\r
284 // 68 Interrupt IRQ4
\r
285 #pragma interrupt INT_IRQ4(resbank)
\r
286 extern void INT_IRQ4(void);
\r
288 // 69 Interrupt IRQ5
\r
289 #pragma interrupt INT_IRQ5(resbank)
\r
290 extern void INT_IRQ5(void);
\r
292 // 70 Interrupt IRQ6
\r
293 #pragma interrupt INT_IRQ6(resbank)
\r
294 extern void INT_IRQ6(void);
\r
296 // 71 Interrupt IRQ7
\r
297 #pragma interrupt INT_IRQ7(resbank)
\r
298 extern void INT_IRQ7(void);
\r
316 // 80 Interrupt PINT0
\r
317 #pragma interrupt INT_PINT0(resbank)
\r
318 extern void INT_PINT0(void);
\r
320 // 81 Interrupt PINT1
\r
321 #pragma interrupt INT_PINT1(resbank)
\r
322 extern void INT_PINT1(void);
\r
324 // 82 Interrupt PINT2
\r
325 #pragma interrupt INT_PINT2(resbank)
\r
326 extern void INT_PINT2(void);
\r
328 // 83 Interrupt PINT3
\r
329 #pragma interrupt INT_PINT3(resbank)
\r
330 extern void INT_PINT3(void);
\r
332 // 84 Interrupt PINT4
\r
333 #pragma interrupt INT_PINT4(resbank)
\r
334 extern void INT_PINT4(void);
\r
336 // 85 Interrupt PINT5
\r
337 #pragma interrupt INT_PINT5(resbank)
\r
338 extern void INT_PINT5(void);
\r
340 // 86 Interrupt PINT6
\r
341 #pragma interrupt INT_PINT6(resbank)
\r
342 extern void INT_PINT6(void);
\r
344 // 87 Interrupt PINT7
\r
345 #pragma interrupt INT_PINT7(resbank)
\r
346 extern void INT_PINT7(void);
\r
355 #pragma interrupt INT_ROM_FIFE(resbank)
\r
356 extern void INT_ROM_FIFE(void);
\r
359 #pragma interrupt INT_AD_ADI0(resbank)
\r
360 extern void INT_AD_ADI0(void);
\r
369 #pragma interrupt INT_AD_ADI1(resbank)
\r
370 extern void INT_AD_ADI1(void);
\r
386 // 104 RCANET0 ERS_0
\r
387 #pragma interrupt INT_RCANET0_ERS_0
\r
388 extern void INT_RCANET0_ERS_0(void);
\r
390 // 105 RCANET0 OVR_0
\r
391 #pragma interrupt INT_RCANET0_OVR_0
\r
392 extern void INT_RCANET0_OVR_0(void);
\r
394 // 106 RCANET0 RM01_0
\r
395 #pragma interrupt INT_RCANET0_RM01_0
\r
396 extern void INT_RCANET0_RM01_0(void);
\r
398 // 107 RCANET0 SLE_0
\r
399 #pragma interrupt INT_RCANET0_SLE_0
\r
400 extern void INT_RCANET0_SLE_0(void);
\r
403 #pragma interrupt INT_DMAC0_DEI0(resbank)
\r
404 extern void INT_DMAC0_DEI0(void);
\r
407 #pragma interrupt INT_DMAC0_HEI0(resbank)
\r
408 extern void INT_DMAC0_HEI0(void);
\r
415 #pragma interrupt INT_DMAC1_DEI1(resbank)
\r
416 extern void INT_DMAC1_DEI1(void);
\r
419 #pragma interrupt INT_DMAC1_HEI1(resbank)
\r
420 extern void INT_DMAC1_HEI1(void);
\r
427 #pragma interrupt INT_DMAC2_DEI2(resbank)
\r
428 extern void INT_DMAC2_DEI2(void);
\r
431 #pragma interrupt INT_DMAC2_HEI2(resbank)
\r
432 extern void INT_DMAC2_HEI2(void);
\r
439 #pragma interrupt INT_DMAC3_DEI3(resbank)
\r
440 extern void INT_DMAC3_DEI3(void);
\r
443 #pragma interrupt INT_DMAC3_HEI3(resbank)
\r
444 extern void INT_DMAC3_HEI3(void);
\r
451 #pragma interrupt INT_DMAC4_DEI4(resbank)
\r
452 extern void INT_DMAC4_DEI4(void);
\r
455 #pragma interrupt INT_DMAC4_HEI4(resbank)
\r
456 extern void INT_DMAC4_HEI4(void);
\r
463 #pragma interrupt INT_DMAC5_DEI5(resbank)
\r
464 extern void INT_DMAC5_DEI5(void);
\r
467 #pragma interrupt INT_DMAC5_HEI5(resbank)
\r
468 extern void INT_DMAC5_HEI5(void);
\r
475 #pragma interrupt INT_DMAC6_DEI6(resbank)
\r
476 extern void INT_DMAC6_DEI6(void);
\r
479 #pragma interrupt INT_DMAC6_HEI6(resbank)
\r
480 extern void INT_DMAC6_HEI6(void);
\r
487 #pragma interrupt INT_DMAC7_DEI7(resbank)
\r
488 extern void INT_DMAC7_DEI7(void);
\r
491 #pragma interrupt INT_DMAC7_HEI7(resbank)
\r
492 extern void INT_DMAC7_HEI7(void);
\r
499 #pragma interrupt INT_CMT_CMI0(resbank)
\r
500 extern void INT_CMT_CMI0(void);
\r
509 #pragma interrupt INT_CMT_CMI1(resbank)
\r
510 extern void INT_CMT_CMI1(void);
\r
519 #pragma interrupt INT_BSC_CMTI(resbank)
\r
520 extern void INT_BSC_CMTI(void);
\r
525 #pragma interrupt INT_USB_EP4FULL(resbank)
\r
526 extern void INT_USB_EP4FULL(void);
\r
528 // 151 USB EP5EMPTY
\r
529 #pragma interrupt INT_USB_EP5EMPTY(resbank)
\r
530 extern void INT_USB_EP5EMPTY(void);
\r
533 #pragma interrupt INT_WDT_ITI(resbank)
\r
534 extern void INT_WDT_ITI(void);
\r
536 // 153 E-DMAC EINT0
\r
537 #pragma interrupt INT_EDMAC_EINT0(resbank)
\r
538 extern void INT_EDMAC_EINT0(void);
\r
541 #pragma interrupt INT_USB_EP1FULL(resbank)
\r
542 extern void INT_USB_EP1FULL(void);
\r
544 // 155 USB EP2EMPTY
\r
545 #pragma interrupt INT_USB_EP2EMPTY(resbank)
\r
546 extern void INT_USB_EP2EMPTY(void);
\r
548 // 156 MTU2 MTU0 TGI0A
\r
549 #pragma interrupt INT_MTU2_MTU0_TGI0A(resbank)
\r
550 extern void INT_MTU2_MTU0_TGI0A(void);
\r
552 // 157 MTU2 MTU0 TGI0B
\r
553 #pragma interrupt INT_MTU2_MTU0_TGI0B(resbank)
\r
554 extern void INT_MTU2_MTU0_TGI0B(void);
\r
556 // 158 MTU2 MTU0 TGI0C
\r
557 #pragma interrupt INT_MTU2_MTU0_TGI0C(resbank)
\r
558 extern void INT_MTU2_MTU0_TGI0C(void);
\r
560 // 159 MTU2 MTU0 TGI0D
\r
561 #pragma interrupt INT_MTU2_MTU0_TGI0D(resbank)
\r
562 extern void INT_MTU2_MTU0_TGI0D(void);
\r
564 // 160 MTU2 MTU0 TGI0V
\r
565 #pragma interrupt INT_MTU2_MTU0_TGI0V(resbank)
\r
566 extern void INT_MTU2_MTU0_TGI0V(void);
\r
568 // 161 MTU2 MTU0 TGI0E
\r
569 #pragma interrupt INT_MTU2_MTU0_TGI0E(resbank)
\r
570 extern void INT_MTU2_MTU0_TGI0E(void);
\r
572 // 162 MTU2 MTU0 TGI0F
\r
573 #pragma interrupt INT_MTU2_MTU0_TGI0F(resbank)
\r
574 extern void INT_MTU2_MTU0_TGI0F(void);
\r
578 // 164 MTU2 MTU1 TGI1A
\r
579 #pragma interrupt INT_MTU2_MTU1_TGI1A(resbank)
\r
580 extern void INT_MTU2_MTU1_TGI1A(void);
\r
582 // 165 MTU2 MTU1 TGI1B
\r
583 #pragma interrupt INT_MTU2_MTU1_TGI1B(resbank)
\r
584 extern void INT_MTU2_MTU1_TGI1B(void);
\r
590 // 168 MTU2 MTU1 TGI1V
\r
591 #pragma interrupt INT_MTU2_MTU1_TGI1V(resbank)
\r
592 extern void INT_MTU2_MTU1_TGI1V(void);
\r
594 // 169 MTU2 MTU1 TGI1U
\r
595 #pragma interrupt INT_MTU2_MTU1_TGI1U(resbank)
\r
596 extern void INT_MTU2_MTU1_TGI1U(void);
\r
602 // 172 MTU2 MTU2 TGI2A
\r
603 #pragma interrupt INT_MTU2_MTU2_TGI2A(resbank)
\r
604 extern void INT_MTU2_MTU2_TGI2A(void);
\r
606 // 173 MTU2 MTU2 TGI2B
\r
607 #pragma interrupt INT_MTU2_MTU2_TGI2B(resbank)
\r
608 extern void INT_MTU2_MTU2_TGI2B(void);
\r
614 // 176 MTU2 MTU2 TGI2V
\r
615 #pragma interrupt INT_MTU2_MTU2_TGI2V(resbank)
\r
616 extern void INT_MTU2_MTU2_TGI2V(void);
\r
618 // 177 MTU2 MTU2 TGI2U
\r
619 #pragma interrupt INT_MTU2_MTU2_TGI2U(resbank)
\r
620 extern void INT_MTU2_MTU2_TGI2U(void);
\r
626 // 180 MTU2 MTU3 TGI3A
\r
627 #pragma interrupt INT_MTU2_MTU3_TGI3A(resbank)
\r
628 extern void INT_MTU2_MTU3_TGI3A(void);
\r
630 // 181 MTU2 MTU3 TGI3B
\r
631 #pragma interrupt INT_MTU2_MTU3_TGI3B(resbank)
\r
632 extern void INT_MTU2_MTU3_TGI3B(void);
\r
634 // 182 MTU2 MTU3 TGI3C
\r
635 #pragma interrupt INT_MTU2_MTU3_TGI3C(resbank)
\r
636 extern void INT_MTU2_MTU3_TGI3C(void);
\r
638 // 183 MTU2 MTU3 TGI3D
\r
639 #pragma interrupt INT_MTU2_MTU3_TGI3D(resbank)
\r
640 extern void INT_MTU2_MTU3_TGI3D(void);
\r
642 // 184 MTU2 MTU3 TGI3V
\r
643 #pragma interrupt INT_MTU2_MTU3_TGI3V(resbank)
\r
644 extern void INT_MTU2_MTU3_TGI3V(void);
\r
652 // 188 MTU2 MTU4 TGI4A
\r
653 #pragma interrupt INT_MTU2_MTU4_TGI4A(resbank)
\r
654 extern void INT_MTU2_MTU4_TGI4A(void);
\r
656 // 189 MTU2 MTU4 TGI4B
\r
657 #pragma interrupt INT_MTU2_MTU4_TGI4B(resbank)
\r
658 extern void INT_MTU2_MTU4_TGI4B(void);
\r
660 // 190 MTU2 MTU4 TGI4C
\r
661 #pragma interrupt INT_MTU2_MTU4_TGI4C(resbank)
\r
662 extern void INT_MTU2_MTU4_TGI4C(void);
\r
664 // 191 MTU2 MTU4 TGI4D
\r
665 #pragma interrupt INT_MTU2_MTU4_TGI4D(resbank)
\r
666 extern void INT_MTU2_MTU4_TGI4D(void);
\r
668 // 192 MTU2 MTU4 TGI4V
\r
669 #pragma interrupt INT_MTU2_MTU4_TGI4V(resbank)
\r
670 extern void INT_MTU2_MTU4_TGI4V(void);
\r
678 // 196 MTU2 MTU5 TGI5U
\r
679 #pragma interrupt INT_MTU2_MTU5_TGI5U(resbank)
\r
680 extern void INT_MTU2_MTU5_TGI5U(void);
\r
682 // 197 MTU2 MTU5 TGI5V
\r
683 #pragma interrupt INT_MTU2_MTU5_TGI5V(resbank)
\r
684 extern void INT_MTU2_MTU5_TGI5V(void);
\r
686 // 198 MTU2 MTU5 TGI5W
\r
687 #pragma interrupt INT_MTU2_MTU5_TGI5W(resbank)
\r
688 extern void INT_MTU2_MTU5_TGI5W(void);
\r
693 #pragma interrupt INT_POE2_OEI1(resbank)
\r
694 extern void INT_POE2_OEI1(void);
\r
697 #pragma interrupt INT_POE2_OEI2(resbank)
\r
698 extern void INT_POE2_OEI2(void);
\r
704 // 204 MTU2S MTU3S TGI3A
\r
705 #pragma interrupt INT_MTU2S_MTU3S_TGI3A(resbank)
\r
706 extern void INT_MTU2S_MTU3S_TGI3A(void);
\r
708 // 205 MTU2S MTU3S TGI3B
\r
709 #pragma interrupt INT_MTU2S_MTU3S_TGI3B(resbank)
\r
710 extern void INT_MTU2S_MTU3S_TGI3B(void);
\r
712 // 206 MTU2S MTU3S TGI3C
\r
713 #pragma interrupt INT_MTU2S_MTU3S_TGI3C(resbank)
\r
714 extern void INT_MTU2S_MTU3S_TGI3C(void);
\r
716 // 207 MTU2S MTU3S TGI3D
\r
717 #pragma interrupt INT_MTU2S_MTU3S_TGI3D(resbank)
\r
718 extern void INT_MTU2S_MTU3S_TGI3D(void);
\r
720 // 208 MTU2S MTU3S TGI3V
\r
721 #pragma interrupt INT_MTU2S_MTU3S_TGI3V(resbank)
\r
722 extern void INT_MTU2S_MTU3S_TGI3V(void);
\r
730 // 212 MTU2S MTU4S TGI4A
\r
731 #pragma interrupt INT_MTU2S_MTU4S_TGI4A(resbank)
\r
732 extern void INT_MTU2S_MTU4S_TGI4A(void);
\r
734 // 213 MTU2S MTU4S TGI4B
\r
735 #pragma interrupt INT_MTU2S_MTU4S_TGI4B(resbank)
\r
736 extern void INT_MTU2S_MTU4S_TGI4B(void);
\r
738 // 214 MTU2S MTU4S TGI4C
\r
739 #pragma interrupt INT_MTU2S_MTU4S_TGI4C(resbank)
\r
740 extern void INT_MTU2S_MTU4S_TGI4C(void);
\r
742 // 215 MTU2S MTU4S TGI4D
\r
743 #pragma interrupt INT_MTU2S_MTU4S_TGI4D(resbank)
\r
744 extern void INT_MTU2S_MTU4S_TGI4D(void);
\r
746 // 216 MTU2S MTU4S TGI4V
\r
747 #pragma interrupt INT_MTU2S_MTU4S_TGI4V(resbank)
\r
748 extern void INT_MTU2S_MTU4S_TGI4V(void);
\r
756 // 220 MTU2S MTU5S TGI5U
\r
757 #pragma interrupt INT_MTU2S_MTU5S_TGI5U(resbank)
\r
758 extern void INT_MTU2S_MTU5S_TGI5U(void);
\r
760 // 221 MTU2S MTU5S TGI5V
\r
761 #pragma interrupt INT_MTU2S_MTU5S_TGI5V(resbank)
\r
762 extern void INT_MTU2S_MTU5S_TGI5V(void);
\r
764 // 222 MTU2S MTU5S TGI5W
\r
765 #pragma interrupt INT_MTU2S_MTU5S_TGI5W(resbank)
\r
766 extern void INT_MTU2S_MTU5S_TGI5W(void);
\r
771 #pragma interrupt INT_POE2_OEI3(resbank)
\r
772 extern void INT_POE2_OEI3(void);
\r
777 #pragma interrupt INT_USB_USI0(resbank)
\r
778 extern void INT_USB_USI0(void);
\r
781 #pragma interrupt INT_USB_USI1(resbank)
\r
782 extern void INT_USB_USI1(void);
\r
785 #pragma interrupt INT_IIC3_STPI(resbank)
\r
786 extern void INT_IIC3_STPI(void);
\r
789 #pragma interrupt INT_IIC3_NAKI(resbank)
\r
790 extern void INT_IIC3_NAKI(void);
\r
793 #pragma interrupt INT_IIC3_RXI(resbank)
\r
794 extern void INT_IIC3_RXI(void);
\r
797 #pragma interrupt INT_IIC3_TXI(resbank)
\r
798 extern void INT_IIC3_TXI(void);
\r
801 #pragma interrupt INT_IIC3_TEI(resbank)
\r
802 extern void INT_IIC3_TEI(void);
\r
805 #pragma interrupt INT_RSPI_SPERI(resbank)
\r
806 extern void INT_RSPI_SPERI(void);
\r
809 #pragma interrupt INT_RSPI_SPRXI(resbank)
\r
810 extern void INT_RSPI_SPRXI(void);
\r
813 #pragma interrupt INT_RSPI_SPTXI(resbank)
\r
814 extern void INT_RSPI_SPTXI(void);
\r
816 // 236 SCI SCI4 ERI4
\r
817 #pragma interrupt INT_SCI_SCI4_ERI4(resbank)
\r
818 extern void INT_SCI_SCI4_ERI4(void);
\r
820 // 237 SCI SCI4 RXI4
\r
821 #pragma interrupt INT_SCI_SCI4_RXI4(resbank)
\r
822 extern void INT_SCI_SCI4_RXI4(void);
\r
824 // 238 SCI SCI4 TXI4
\r
825 #pragma interrupt INT_SCI_SCI4_TXI4(resbank)
\r
826 extern void INT_SCI_SCI4_TXI4(void);
\r
828 // 239 SCI SCI4 TEI4
\r
829 #pragma interrupt INT_SCI_SCI4_TEI4(resbank)
\r
830 extern void INT_SCI_SCI4_TEI4(void);
\r
832 // 240 SCI SCI0 ERI0
\r
833 #pragma interrupt INT_SCI_SCI0_ERI0(resbank)
\r
834 extern void INT_SCI_SCI0_ERI0(void);
\r
836 // 241 SCI SCI0 RXI0
\r
837 #pragma interrupt INT_SCI_SCI0_RXI0(resbank)
\r
838 extern void INT_SCI_SCI0_RXI0(void);
\r
840 // 242 SCI SCI0 TXI0
\r
841 #pragma interrupt INT_SCI_SCI0_TXI0(resbank)
\r
842 extern void INT_SCI_SCI0_TXI0(void);
\r
844 // 243 SCI SCI0 TEI0
\r
845 #pragma interrupt INT_SCI_SCI0_TEI0(resbank)
\r
846 extern void INT_SCI_SCI0_TEI0(void);
\r
848 // 244 SCI SCI1 ERI1
\r
849 #pragma interrupt INT_SCI_SCI1_ERI1(resbank)
\r
850 extern void INT_SCI_SCI1_ERI1(void);
\r
852 // 245 SCI SCI1 RXI1
\r
853 #pragma interrupt INT_SCI_SCI1_RXI1(resbank)
\r
854 extern void INT_SCI_SCI1_RXI1(void);
\r
856 // 246 SCI SCI1 TXI1
\r
857 #pragma interrupt INT_SCI_SCI1_TXI1(resbank)
\r
858 extern void INT_SCI_SCI1_TXI1(void);
\r
860 // 247 SCI SCI1 TEI1
\r
861 #pragma interrupt INT_SCI_SCI1_TEI1(resbank)
\r
862 extern void INT_SCI_SCI1_TEI1(void);
\r
864 // 248 SCI SCI2 ERI2
\r
865 #pragma interrupt INT_SCI_SCI2_ERI2(resbank)
\r
866 extern void INT_SCI_SCI2_ERI2(void);
\r
868 // 249 SCI SCI2 RXI2
\r
869 #pragma interrupt INT_SCI_SCI2_RXI2(resbank)
\r
870 extern void INT_SCI_SCI2_RXI2(void);
\r
872 // 250 SCI SCI2 TXI2
\r
873 #pragma interrupt INT_SCI_SCI2_TXI2(resbank)
\r
874 extern void INT_SCI_SCI2_TXI2(void);
\r
876 // 251 SCI SCI2 TEI2
\r
877 #pragma interrupt INT_SCI_SCI2_TEI2(resbank)
\r
878 extern void INT_SCI_SCI2_TEI2(void);
\r
880 // 252 SCIF SCIF3 BRI3
\r
881 #pragma interrupt INT_SCIF_SCIF3_BRI3(resbank)
\r
882 extern void INT_SCIF_SCIF3_BRI3(void);
\r
884 // 253 SCIF SCIF3 ERI3
\r
885 #pragma interrupt INT_SCIF_SCIF3_ERI3(resbank)
\r
886 extern void INT_SCIF_SCIF3_ERI3(void);
\r
888 // 254 SCIF SCIF3 RXI3
\r
889 #pragma interrupt INT_SCIF_SCIF3_RXI3(resbank)
\r
890 extern void INT_SCIF_SCIF3_RXI3(void);
\r
892 // 255 SCIF SCIF3 TXI3
\r
893 #pragma interrupt INT_SCIF_SCIF3_TXI3(resbank)
\r
894 extern void INT_SCIF_SCIF3_TXI3(void);
\r
897 #pragma interrupt Dummy(resbank)
\r
898 extern void Dummy(void);
\r
900 #endif /* VECT_H */
\r