2 FreeRTOS V8.1.1 - Copyright (C) 2014 Real Time Engineers Ltd.
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5 VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
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7 ***************************************************************************
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9 * FreeRTOS provides completely free yet professionally developed, *
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10 * robust, strictly quality controlled, supported, and cross *
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11 * platform software that has become a de facto standard. *
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13 * Help yourself get started quickly and support the FreeRTOS *
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14 * project by purchasing a FreeRTOS tutorial book, reference *
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15 * manual, or both from: http://www.FreeRTOS.org/Documentation *
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19 ***************************************************************************
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21 This file is part of the FreeRTOS distribution.
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23 FreeRTOS is free software; you can redistribute it and/or modify it under
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24 the terms of the GNU General Public License (version 2) as published by the
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25 Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.
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27 >>! NOTE: The modification to the GPL is included to allow you to !<<
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28 >>! distribute a combined work that includes FreeRTOS without being !<<
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29 >>! obliged to provide the source code for proprietary components !<<
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30 >>! outside of the FreeRTOS kernel. !<<
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32 FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
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33 WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
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34 FOR A PARTICULAR PURPOSE. Full license text is available from the following
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35 link: http://www.freertos.org/a00114.html
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39 ***************************************************************************
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41 * Having a problem? Start by reading the FAQ "My application does *
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42 * not run, what could be wrong?" *
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44 * http://www.FreeRTOS.org/FAQHelp.html *
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46 ***************************************************************************
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48 http://www.FreeRTOS.org - Documentation, books, training, latest versions,
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49 license and Real Time Engineers Ltd. contact details.
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51 http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
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52 including FreeRTOS+Trace - an indispensable productivity tool, a DOS
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53 compatible FAT file system, and our tiny thread aware UDP/IP stack.
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55 http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High
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56 Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS
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57 licenses offer ticketed support, indemnification and middleware.
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59 http://www.SafeRTOS.com - High Integrity Systems also provide a safety
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60 engineered and independently SIL3 certified version for use in safety and
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61 mission critical applications that require provable dependability.
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66 /* Hardware specific includes. */
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67 #include "iodefine.h"
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68 #include "typedefine.h"
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69 #include "hwEthernet.h"
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70 #include "hwEthernetPhy.h"
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72 /* FreeRTOS includes. */
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73 #include "FreeRTOS.h"
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78 #include "net/uip.h"
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80 /* The time to wait between attempts to obtain a free buffer. */
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81 #define emacBUFFER_WAIT_DELAY_ms ( 3 / portTICK_PERIOD_MS )
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83 /* The number of times emacBUFFER_WAIT_DELAY_ms should be waited before giving
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84 up on attempting to obtain a free buffer all together. */
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85 #define emacBUFFER_WAIT_ATTEMPTS ( 30 )
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87 /* The number of Rx descriptors. */
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88 #define emacNUM_RX_DESCRIPTORS 3
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90 /* The number of Tx descriptors. When using uIP there is not point in having
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92 #define emacNUM_TX_BUFFERS 2
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94 /* The total number of EMAC buffers to allocate. */
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95 #define emacNUM_BUFFERS ( emacNUM_RX_DESCRIPTORS + emacNUM_TX_BUFFERS )
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97 /* The time to wait for the Tx descriptor to become free. */
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98 #define emacTX_WAIT_DELAY_ms ( 10 / portTICK_PERIOD_MS )
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100 /* The total number of times to wait emacTX_WAIT_DELAY_ms for the Tx descriptor to
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102 #define emacTX_WAIT_ATTEMPTS ( 5 )
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104 /* Only Rx end and Tx end interrupts are used by this driver. */
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105 #define emacTX_END_INTERRUPT ( 1UL << 21UL )
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106 #define emacRX_END_INTERRUPT ( 1UL << 18UL )
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108 /*-----------------------------------------------------------*/
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110 /* The buffers and descriptors themselves. */
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111 #pragma section RX_DESCR
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112 ethfifo xRxDescriptors[ emacNUM_RX_DESCRIPTORS ];
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113 #pragma section TX_DESCR
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114 ethfifo xTxDescriptors[ emacNUM_TX_BUFFERS ];
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115 #pragma section _ETHERNET_BUFFERS
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116 char xEthernetBuffers[ emacNUM_BUFFERS ][ UIP_BUFSIZE ];
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119 /* Used to indicate which buffers are free and which are in use. If an index
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120 contains 0 then the corresponding buffer in xEthernetBuffers is free, otherwise
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121 the buffer is in use or about to be used. */
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122 static unsigned char ucBufferInUse[ emacNUM_BUFFERS ];
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124 /*-----------------------------------------------------------*/
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127 * Initialise both the Rx and Tx descriptors.
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129 static void prvInitialiseDescriptors( void );
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132 * Return a pointer to a free buffer within xEthernetBuffers.
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134 static unsigned char *prvGetNextBuffer( void );
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137 * Return a buffer to the list of free buffers.
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139 static void prvReturnBuffer( unsigned char *pucBuffer );
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142 * Examine the status of the next Rx FIFO to see if it contains new data.
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144 static unsigned long prvCheckRxFifoStatus( void );
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147 * Setup the microcontroller for communication with the PHY.
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149 static void prvSetupPortPinsAndReset( void );
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152 * Configure the Ethernet interface peripherals.
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154 static void prvConfigureEtherCAndEDMAC( void );
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157 * Something has gone wrong with the descriptor usage. Reset all the buffers
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160 static void prvResetEverything( void );
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162 /*-----------------------------------------------------------*/
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164 /* Points to the Rx descriptor currently in use. */
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165 static ethfifo *xCurrentRxDesc = NULL;
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167 /* The buffer used by the uIP stack to both receive and send. This points to
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168 one of the Ethernet buffers when its actually in use. */
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169 unsigned char *uip_buf = NULL;
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171 /*-----------------------------------------------------------*/
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173 void vInitEmac( void )
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175 /* Setup the SH hardware for MII communications. */
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176 prvSetupPortPinsAndReset();
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178 /* Set the Rx and Tx descriptors into their initial state. */
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179 prvInitialiseDescriptors();
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181 /* Set the MAC address into the ETHERC */
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182 EtherC.MAHR = ( ( unsigned long ) configMAC_ADDR0 << 24UL ) |
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183 ( ( unsigned long ) configMAC_ADDR1 << 16UL ) |
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184 ( ( unsigned long ) configMAC_ADDR2 << 8UL ) |
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185 ( unsigned long ) configMAC_ADDR3;
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187 EtherC.MALR.BIT.MA = ( ( unsigned long ) configMAC_ADDR4 << 8UL ) |
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188 ( unsigned long ) configMAC_ADDR5;
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190 /* Perform rest of interface hardware configuration. */
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191 prvConfigureEtherCAndEDMAC();
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193 /* Nothing received yet, so uip_buf points nowhere. */
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196 /* Initialize the PHY */
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199 /*-----------------------------------------------------------*/
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201 void vEMACWrite( void )
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205 /* Wait until the second transmission of the last packet has completed. */
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206 for( x = 0; x < emacTX_WAIT_ATTEMPTS; x++ )
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208 if( ( xTxDescriptors[ 1 ].status & ACT ) != 0 )
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210 /* Descriptor is still active. */
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211 vTaskDelay( emacTX_WAIT_DELAY_ms );
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219 /* Is the descriptor free after waiting for it? */
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220 if( ( xTxDescriptors[ 1 ].status & ACT ) != 0 )
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222 /* Something has gone wrong. */
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223 prvResetEverything();
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226 /* Setup both descriptors to transmit the frame. */
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227 xTxDescriptors[ 0 ].buf_p = ( char * ) uip_buf;
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228 xTxDescriptors[ 0 ].bufsize = uip_len;
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229 xTxDescriptors[ 1 ].buf_p = ( char * ) uip_buf;
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230 xTxDescriptors[ 1 ].bufsize = uip_len;
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232 /* uip_buf is being sent by the Tx descriptor. Allocate a new buffer
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233 for use by the stack. */
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234 uip_buf = prvGetNextBuffer();
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236 /* Clear previous settings and go. */
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237 xTxDescriptors[0].status &= ~( FP1 | FP0 );
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238 xTxDescriptors[0].status |= ( FP1 | FP0 | ACT );
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239 xTxDescriptors[1].status &= ~( FP1 | FP0 );
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240 xTxDescriptors[1].status |= ( FP1 | FP0 | ACT );
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242 EDMAC.EDTRR.LONG = 0x00000001;
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244 /*-----------------------------------------------------------*/
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246 unsigned long ulEMACRead( void )
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248 unsigned long ulBytesReceived;
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250 ulBytesReceived = prvCheckRxFifoStatus();
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252 if( ulBytesReceived > 0 )
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254 xCurrentRxDesc->status &= ~( FP1 | FP0 );
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255 xCurrentRxDesc->status |= ACT;
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257 if( EDMAC.EDRRR.LONG == 0x00000000L )
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259 /* Restart Ethernet if it has stopped */
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260 EDMAC.EDRRR.LONG = 0x00000001L;
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263 /* Mark the pxDescriptor buffer as free as uip_buf is going to be set to
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264 the buffer that contains the received data. */
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265 prvReturnBuffer( uip_buf );
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267 uip_buf = ( void * ) xCurrentRxDesc->buf_p;
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269 /* Move onto the next buffer in the ring. */
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270 xCurrentRxDesc = xCurrentRxDesc->next;
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273 return ulBytesReceived;
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275 /*-----------------------------------------------------------*/
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277 long lEMACWaitForLink( void )
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281 /* Set the link status. */
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282 switch( phyStatus() )
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284 /* Half duplex link */
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285 case PHY_LINK_100H:
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287 EtherC.ECMR.BIT.DM = 0;
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291 /* Full duplex link */
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292 case PHY_LINK_100F:
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294 EtherC.ECMR.BIT.DM = 1;
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303 if( lReturn == pdPASS )
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305 /* Enable receive and transmit. */
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306 EtherC.ECMR.BIT.RE = 1;
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307 EtherC.ECMR.BIT.TE = 1;
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309 /* Enable EDMAC receive */
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310 EDMAC.EDRRR.LONG = 0x1;
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315 /*-----------------------------------------------------------*/
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317 static void prvInitialiseDescriptors( void )
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319 ethfifo *pxDescriptor;
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322 for( x = 0; x < emacNUM_BUFFERS; x++ )
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324 /* Ensure none of the buffers are shown as in use at the start. */
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325 ucBufferInUse[ x ] = pdFALSE;
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328 /* Initialise the Rx descriptors. */
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329 for( x = 0; x < emacNUM_RX_DESCRIPTORS; x++ )
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331 pxDescriptor = &( xRxDescriptors[ x ] );
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332 pxDescriptor->buf_p = &( xEthernetBuffers[ x ][ 0 ] );
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334 pxDescriptor->bufsize = UIP_BUFSIZE;
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335 pxDescriptor->size = 0;
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336 pxDescriptor->status = ACT;
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337 pxDescriptor->next = &xRxDescriptors[ x + 1 ];
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339 /* Mark this buffer as in use. */
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340 ucBufferInUse[ x ] = pdTRUE;
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343 /* The last descriptor points back to the start. */
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344 pxDescriptor->status |= DL;
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345 pxDescriptor->next = &xRxDescriptors[ 0 ];
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347 /* Initialise the Tx descriptors. */
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348 for( x = 0; x < emacNUM_TX_BUFFERS; x++ )
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350 pxDescriptor = &( xTxDescriptors[ x ] );
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352 /* A buffer is not allocated to the Tx descriptor until a send is
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353 actually required. */
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354 pxDescriptor->buf_p = NULL;
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356 pxDescriptor->bufsize = UIP_BUFSIZE;
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357 pxDescriptor->size = 0;
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358 pxDescriptor->status = 0;
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359 pxDescriptor->next = &xTxDescriptors[ x + 1 ];
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362 /* The last descriptor points back to the start. */
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363 pxDescriptor->status |= DL;
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364 pxDescriptor->next = &( xTxDescriptors[ 0 ] );
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366 /* Use the first Rx descriptor to start with. */
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367 xCurrentRxDesc = &( xRxDescriptors[ 0 ] );
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369 /*-----------------------------------------------------------*/
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371 static unsigned char *prvGetNextBuffer( void )
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374 unsigned char *pucReturn = NULL;
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375 unsigned long ulAttempts = 0;
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377 while( pucReturn == NULL )
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379 /* Look through the buffers to find one that is not in use by
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381 for( x = 0; x < emacNUM_BUFFERS; x++ )
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383 if( ucBufferInUse[ x ] == pdFALSE )
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385 ucBufferInUse[ x ] = pdTRUE;
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386 pucReturn = ( unsigned char * ) &( xEthernetBuffers[ x ][ 0 ] );
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391 /* Was a buffer found? */
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392 if( pucReturn == NULL )
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396 if( ulAttempts >= emacBUFFER_WAIT_ATTEMPTS )
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401 /* Wait then look again. */
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402 vTaskDelay( emacBUFFER_WAIT_DELAY_ms );
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408 /*-----------------------------------------------------------*/
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410 static void prvReturnBuffer( unsigned char *pucBuffer )
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414 /* Return a buffer to the pool of free buffers. */
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415 for( ul = 0; ul < emacNUM_BUFFERS; ul++ )
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417 if( &( xEthernetBuffers[ ul ][ 0 ] ) == ( void * ) pucBuffer )
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419 ucBufferInUse[ ul ] = pdFALSE;
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424 /*-----------------------------------------------------------*/
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426 static void prvResetEverything( void )
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428 /* Temporary code just to see if this gets called. This function has not
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429 been implemented. */
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430 portDISABLE_INTERRUPTS();
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433 /*-----------------------------------------------------------*/
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435 static unsigned long prvCheckRxFifoStatus( void )
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437 unsigned long ulReturn = 0;
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439 if( ( xCurrentRxDesc->status & ACT ) != 0 )
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441 /* Current descriptor is still active. */
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443 else if( ( xCurrentRxDesc->status & FE ) != 0 )
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445 /* Frame error. Clear the error. */
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446 xCurrentRxDesc->status &= ~( FP1 | FP0 | FE );
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447 xCurrentRxDesc->status &= ~( RMAF | RRF | RTLF | RTSF | PRE | CERF );
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448 xCurrentRxDesc->status |= ACT;
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449 xCurrentRxDesc = xCurrentRxDesc->next;
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451 if( EDMAC.EDRRR.LONG == 0x00000000UL )
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453 /* Restart Ethernet if it has stopped. */
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454 EDMAC.EDRRR.LONG = 0x00000001UL;
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459 /* The descriptor contains a frame. Because of the size of the buffers
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460 the frame should always be complete. */
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461 if( (xCurrentRxDesc->status & FP0) == FP0 )
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463 ulReturn = xCurrentRxDesc->size;
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467 /* Do not expect to get here. */
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468 prvResetEverything();
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474 /*-----------------------------------------------------------*/
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476 static void prvSetupPortPinsAndReset( void )
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478 /* Initialisation code taken from Renesas example project. */
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480 PFC.PACRL4.BIT.PA12MD = 0x7; /* Set TX_CLK input (EtherC) */
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481 PFC.PACRL3.BIT.PA11MD = 0x7; /* Set TX_EN output (EtherC) */
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482 PFC.PACRL3.BIT.PA10MD = 0x7; /* Set MII_TXD0 output (EtherC) */
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483 PFC.PACRL3.BIT.PA9MD = 0x7; /* Set MII_TXD1 output (EtherC) */
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484 PFC.PACRL3.BIT.PA8MD = 0x7; /* Set MII_TXD2 output (EtherC) */
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485 PFC.PACRL2.BIT.PA7MD = 0x7; /* Set MII_TXD3 output (EtherC) */
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486 PFC.PACRL2.BIT.PA6MD = 0x7; /* Set TX_ER output (EtherC) */
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487 PFC.PDCRH4.BIT.PD31MD = 0x7; /* Set RX_DV input (EtherC) */
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488 PFC.PDCRH4.BIT.PD30MD = 0x7; /* Set RX_ER input (EtherC) */
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489 PFC.PDCRH4.BIT.PD29MD = 0x7; /* Set MII_RXD3 input (EtherC) */
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490 PFC.PDCRH4.BIT.PD28MD = 0x7; /* Set MII_RXD2 input (EtherC) */
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491 PFC.PDCRH3.BIT.PD27MD = 0x7; /* Set MII_RXD1 input (EtherC) */
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492 PFC.PDCRH3.BIT.PD26MD = 0x7; /* Set MII_RXD0 input (EtherC) */
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493 PFC.PDCRH3.BIT.PD25MD = 0x7; /* Set RX_CLK input (EtherC) */
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494 PFC.PDCRH3.BIT.PD24MD = 0x7; /* Set CRS input (EtherC) */
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495 PFC.PDCRH2.BIT.PD23MD = 0x7; /* Set COL input (EtherC) */
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496 PFC.PDCRH2.BIT.PD22MD = 0x7; /* Set WOL output (EtherC) */
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497 PFC.PDCRH2.BIT.PD21MD = 0x7; /* Set EXOUT output (EtherC) */
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498 PFC.PDCRH2.BIT.PD20MD = 0x7; /* Set MDC output (EtherC) */
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499 PFC.PDCRH1.BIT.PD19MD = 0x7; /* Set LINKSTA input (EtherC) */
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500 PFC.PDCRH1.BIT.PD18MD = 0x7; /* Set MDIO input/output (EtherC) */
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502 STB.CR4.BIT._ETHER = 0x0;
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503 EDMAC.EDMR.BIT.SWR = 1;
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505 /* Crude wait for reset to complete. */
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506 vTaskDelay( 500 / portTICK_PERIOD_MS );
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508 /*-----------------------------------------------------------*/
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510 static void prvConfigureEtherCAndEDMAC( void )
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512 /* Initialisation code taken from Renesas example project. */
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514 /* TODO: Check bit 5 */
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515 EtherC.ECSR.LONG = 0x00000037; /* Clear all EtherC statuS BFR, PSRTO, LCHNG, MPD, ICD */
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517 /* TODO: Check bit 5 */
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518 EtherC.ECSIPR.LONG = 0x00000020; /* Disable EtherC status change interrupt */
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519 EtherC.RFLR.LONG = 1518; /* Ether payload is 1500+ CRC */
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520 EtherC.IPGR.LONG = 0x00000014; /* Intergap is 96-bit time */
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523 EDMAC.EESR.LONG = 0x47FF0F9F; /* Clear all EtherC and EDMAC status bits */
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524 EDMAC.RDLAR = ( void * ) xCurrentRxDesc; /* Initialaize Rx Descriptor List Address */
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525 EDMAC.TDLAR = &( xTxDescriptors[ 0 ] ); /* Initialaize Tx Descriptor List Address */
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526 EDMAC.TRSCER.LONG = 0x00000000; /* Copy-back status is RFE & TFE only */
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527 EDMAC.TFTR.LONG = 0x00000000; /* Threshold of Tx_FIFO */
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528 EDMAC.FDR.LONG = 0x00000000; /* Transmit fifo & receive fifo is 256 bytes */
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529 EDMAC.RMCR.LONG = 0x00000003; /* Receive function is normal mode(continued) */
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531 /* Set the EDMAC interrupt priority - the interrupt priority must be
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532 configKERNEL_INTERRUPT_PRIORITY no matter which peripheral is used to
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533 generate the tick interrupt. */
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534 INTC.IPR19.BIT._EDMAC = portKERNEL_INTERRUPT_PRIORITY;
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535 EDMAC.EESIPR.LONG = emacTX_END_INTERRUPT | emacRX_END_INTERRUPT; /* Enable Rx and Tx end interrupts. */
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537 /* Clear the interrupt flag. */
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538 CMT0.CMCSR.BIT.CMF = 0;
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540 /*-----------------------------------------------------------*/
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542 void vEMAC_ISR_Handler( void )
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544 unsigned long ul = EDMAC.EESR.LONG;
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545 long lHigherPriorityTaskWoken = pdFALSE;
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546 extern SemaphoreHandle_t xEMACSemaphore;
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547 static long ulTxEndInts = 0;
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549 /* Has a Tx end occurred? */
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550 if( ul & emacTX_END_INTERRUPT )
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553 if( ulTxEndInts >= 2 )
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555 /* Only return the buffer to the pool once both Txes have completed. */
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556 prvReturnBuffer( ( void * ) xTxDescriptors[ 0 ].buf_p );
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559 EDMAC.EESR.LONG = emacTX_END_INTERRUPT;
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562 /* Has an Rx end occurred? */
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563 if( ul & emacRX_END_INTERRUPT )
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565 /* Make sure the Ethernet task is not blocked waiting for a packet. */
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566 xSemaphoreGiveFromISR( xEMACSemaphore, &lHigherPriorityTaskWoken );
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567 portYIELD_FROM_ISR( lHigherPriorityTaskWoken );
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568 EDMAC.EESR.LONG = emacRX_END_INTERRUPT;
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