2 FreeRTOS V7.5.2 - Copyright (C) 2013 Real Time Engineers Ltd.
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4 VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
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6 ***************************************************************************
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8 * FreeRTOS provides completely free yet professionally developed, *
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9 * robust, strictly quality controlled, supported, and cross *
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10 * platform software that has become a de facto standard. *
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12 * Help yourself get started quickly and support the FreeRTOS *
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13 * project by purchasing a FreeRTOS tutorial book, reference *
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14 * manual, or both from: http://www.FreeRTOS.org/Documentation *
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18 ***************************************************************************
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20 This file is part of the FreeRTOS distribution.
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22 FreeRTOS is free software; you can redistribute it and/or modify it under
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23 the terms of the GNU General Public License (version 2) as published by the
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24 Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.
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26 >>! NOTE: The modification to the GPL is included to allow you to distribute
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27 >>! a combined work that includes FreeRTOS without being obliged to provide
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28 >>! the source code for proprietary components outside of the FreeRTOS
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31 FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
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32 WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
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33 FOR A PARTICULAR PURPOSE. Full license text is available from the following
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34 link: http://www.freertos.org/a00114.html
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38 ***************************************************************************
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40 * Having a problem? Start by reading the FAQ "My application does *
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41 * not run, what could be wrong?" *
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43 * http://www.FreeRTOS.org/FAQHelp.html *
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45 ***************************************************************************
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47 http://www.FreeRTOS.org - Documentation, books, training, latest versions,
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48 license and Real Time Engineers Ltd. contact details.
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50 http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
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51 including FreeRTOS+Trace - an indispensable productivity tool, a DOS
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52 compatible FAT file system, and our tiny thread aware UDP/IP stack.
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54 http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High
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55 Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS
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56 licenses offer ticketed support, indemnification and middleware.
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58 http://www.SafeRTOS.com - High Integrity Systems also provide a safety
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59 engineered and independently SIL3 certified version for use in safety and
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60 mission critical applications that require provable dependability.
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65 /* Hardware specific includes. */
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66 #include "iodefine.h"
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67 #include "typedefine.h"
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68 #include "hwEthernet.h"
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69 #include "hwEthernetPhy.h"
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71 /* FreeRTOS includes. */
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72 #include "FreeRTOS.h"
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77 #include "net/uip.h"
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79 /* The time to wait between attempts to obtain a free buffer. */
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80 #define emacBUFFER_WAIT_DELAY_ms ( 3 / portTICK_RATE_MS )
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82 /* The number of times emacBUFFER_WAIT_DELAY_ms should be waited before giving
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83 up on attempting to obtain a free buffer all together. */
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84 #define emacBUFFER_WAIT_ATTEMPTS ( 30 )
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86 /* The number of Rx descriptors. */
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87 #define emacNUM_RX_DESCRIPTORS 3
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89 /* The number of Tx descriptors. When using uIP there is not point in having
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91 #define emacNUM_TX_BUFFERS 2
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93 /* The total number of EMAC buffers to allocate. */
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94 #define emacNUM_BUFFERS ( emacNUM_RX_DESCRIPTORS + emacNUM_TX_BUFFERS )
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96 /* The time to wait for the Tx descriptor to become free. */
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97 #define emacTX_WAIT_DELAY_ms ( 10 / portTICK_RATE_MS )
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99 /* The total number of times to wait emacTX_WAIT_DELAY_ms for the Tx descriptor to
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101 #define emacTX_WAIT_ATTEMPTS ( 5 )
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103 /* Only Rx end and Tx end interrupts are used by this driver. */
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104 #define emacTX_END_INTERRUPT ( 1UL << 21UL )
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105 #define emacRX_END_INTERRUPT ( 1UL << 18UL )
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107 /*-----------------------------------------------------------*/
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109 /* The buffers and descriptors themselves. */
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110 #pragma section RX_DESCR
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111 ethfifo xRxDescriptors[ emacNUM_RX_DESCRIPTORS ];
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112 #pragma section TX_DESCR
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113 ethfifo xTxDescriptors[ emacNUM_TX_BUFFERS ];
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114 #pragma section _ETHERNET_BUFFERS
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115 char xEthernetBuffers[ emacNUM_BUFFERS ][ UIP_BUFSIZE ];
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118 /* Used to indicate which buffers are free and which are in use. If an index
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119 contains 0 then the corresponding buffer in xEthernetBuffers is free, otherwise
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120 the buffer is in use or about to be used. */
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121 static unsigned char ucBufferInUse[ emacNUM_BUFFERS ];
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123 /*-----------------------------------------------------------*/
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126 * Initialise both the Rx and Tx descriptors.
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128 static void prvInitialiseDescriptors( void );
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131 * Return a pointer to a free buffer within xEthernetBuffers.
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133 static unsigned char *prvGetNextBuffer( void );
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136 * Return a buffer to the list of free buffers.
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138 static void prvReturnBuffer( unsigned char *pucBuffer );
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141 * Examine the status of the next Rx FIFO to see if it contains new data.
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143 static unsigned long prvCheckRxFifoStatus( void );
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146 * Setup the microcontroller for communication with the PHY.
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148 static void prvSetupPortPinsAndReset( void );
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151 * Configure the Ethernet interface peripherals.
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153 static void prvConfigureEtherCAndEDMAC( void );
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156 * Something has gone wrong with the descriptor usage. Reset all the buffers
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159 static void prvResetEverything( void );
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161 /*-----------------------------------------------------------*/
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163 /* Points to the Rx descriptor currently in use. */
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164 static ethfifo *xCurrentRxDesc = NULL;
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166 /* The buffer used by the uIP stack to both receive and send. This points to
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167 one of the Ethernet buffers when its actually in use. */
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168 unsigned char *uip_buf = NULL;
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170 /*-----------------------------------------------------------*/
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172 void vInitEmac( void )
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174 /* Setup the SH hardware for MII communications. */
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175 prvSetupPortPinsAndReset();
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177 /* Set the Rx and Tx descriptors into their initial state. */
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178 prvInitialiseDescriptors();
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180 /* Set the MAC address into the ETHERC */
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181 EtherC.MAHR = ( ( unsigned long ) configMAC_ADDR0 << 24UL ) |
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182 ( ( unsigned long ) configMAC_ADDR1 << 16UL ) |
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183 ( ( unsigned long ) configMAC_ADDR2 << 8UL ) |
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184 ( unsigned long ) configMAC_ADDR3;
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186 EtherC.MALR.BIT.MA = ( ( unsigned long ) configMAC_ADDR4 << 8UL ) |
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187 ( unsigned long ) configMAC_ADDR5;
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189 /* Perform rest of interface hardware configuration. */
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190 prvConfigureEtherCAndEDMAC();
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192 /* Nothing received yet, so uip_buf points nowhere. */
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195 /* Initialize the PHY */
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198 /*-----------------------------------------------------------*/
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200 void vEMACWrite( void )
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204 /* Wait until the second transmission of the last packet has completed. */
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205 for( x = 0; x < emacTX_WAIT_ATTEMPTS; x++ )
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207 if( ( xTxDescriptors[ 1 ].status & ACT ) != 0 )
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209 /* Descriptor is still active. */
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210 vTaskDelay( emacTX_WAIT_DELAY_ms );
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218 /* Is the descriptor free after waiting for it? */
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219 if( ( xTxDescriptors[ 1 ].status & ACT ) != 0 )
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221 /* Something has gone wrong. */
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222 prvResetEverything();
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225 /* Setup both descriptors to transmit the frame. */
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226 xTxDescriptors[ 0 ].buf_p = ( char * ) uip_buf;
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227 xTxDescriptors[ 0 ].bufsize = uip_len;
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228 xTxDescriptors[ 1 ].buf_p = ( char * ) uip_buf;
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229 xTxDescriptors[ 1 ].bufsize = uip_len;
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231 /* uip_buf is being sent by the Tx descriptor. Allocate a new buffer
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232 for use by the stack. */
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233 uip_buf = prvGetNextBuffer();
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235 /* Clear previous settings and go. */
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236 xTxDescriptors[0].status &= ~( FP1 | FP0 );
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237 xTxDescriptors[0].status |= ( FP1 | FP0 | ACT );
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238 xTxDescriptors[1].status &= ~( FP1 | FP0 );
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239 xTxDescriptors[1].status |= ( FP1 | FP0 | ACT );
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241 EDMAC.EDTRR.LONG = 0x00000001;
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243 /*-----------------------------------------------------------*/
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245 unsigned long ulEMACRead( void )
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247 unsigned long ulBytesReceived;
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249 ulBytesReceived = prvCheckRxFifoStatus();
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251 if( ulBytesReceived > 0 )
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253 xCurrentRxDesc->status &= ~( FP1 | FP0 );
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254 xCurrentRxDesc->status |= ACT;
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256 if( EDMAC.EDRRR.LONG == 0x00000000L )
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258 /* Restart Ethernet if it has stopped */
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259 EDMAC.EDRRR.LONG = 0x00000001L;
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262 /* Mark the pxDescriptor buffer as free as uip_buf is going to be set to
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263 the buffer that contains the received data. */
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264 prvReturnBuffer( uip_buf );
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266 uip_buf = ( void * ) xCurrentRxDesc->buf_p;
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268 /* Move onto the next buffer in the ring. */
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269 xCurrentRxDesc = xCurrentRxDesc->next;
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272 return ulBytesReceived;
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274 /*-----------------------------------------------------------*/
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276 long lEMACWaitForLink( void )
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280 /* Set the link status. */
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281 switch( phyStatus() )
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283 /* Half duplex link */
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284 case PHY_LINK_100H:
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286 EtherC.ECMR.BIT.DM = 0;
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290 /* Full duplex link */
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291 case PHY_LINK_100F:
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293 EtherC.ECMR.BIT.DM = 1;
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302 if( lReturn == pdPASS )
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304 /* Enable receive and transmit. */
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305 EtherC.ECMR.BIT.RE = 1;
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306 EtherC.ECMR.BIT.TE = 1;
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308 /* Enable EDMAC receive */
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309 EDMAC.EDRRR.LONG = 0x1;
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314 /*-----------------------------------------------------------*/
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316 static void prvInitialiseDescriptors( void )
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318 ethfifo *pxDescriptor;
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321 for( x = 0; x < emacNUM_BUFFERS; x++ )
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323 /* Ensure none of the buffers are shown as in use at the start. */
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324 ucBufferInUse[ x ] = pdFALSE;
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327 /* Initialise the Rx descriptors. */
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328 for( x = 0; x < emacNUM_RX_DESCRIPTORS; x++ )
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330 pxDescriptor = &( xRxDescriptors[ x ] );
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331 pxDescriptor->buf_p = &( xEthernetBuffers[ x ][ 0 ] );
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333 pxDescriptor->bufsize = UIP_BUFSIZE;
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334 pxDescriptor->size = 0;
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335 pxDescriptor->status = ACT;
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336 pxDescriptor->next = &xRxDescriptors[ x + 1 ];
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338 /* Mark this buffer as in use. */
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339 ucBufferInUse[ x ] = pdTRUE;
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342 /* The last descriptor points back to the start. */
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343 pxDescriptor->status |= DL;
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344 pxDescriptor->next = &xRxDescriptors[ 0 ];
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346 /* Initialise the Tx descriptors. */
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347 for( x = 0; x < emacNUM_TX_BUFFERS; x++ )
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349 pxDescriptor = &( xTxDescriptors[ x ] );
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351 /* A buffer is not allocated to the Tx descriptor until a send is
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352 actually required. */
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353 pxDescriptor->buf_p = NULL;
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355 pxDescriptor->bufsize = UIP_BUFSIZE;
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356 pxDescriptor->size = 0;
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357 pxDescriptor->status = 0;
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358 pxDescriptor->next = &xTxDescriptors[ x + 1 ];
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361 /* The last descriptor points back to the start. */
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362 pxDescriptor->status |= DL;
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363 pxDescriptor->next = &( xTxDescriptors[ 0 ] );
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365 /* Use the first Rx descriptor to start with. */
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366 xCurrentRxDesc = &( xRxDescriptors[ 0 ] );
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368 /*-----------------------------------------------------------*/
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370 static unsigned char *prvGetNextBuffer( void )
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373 unsigned char *pucReturn = NULL;
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374 unsigned long ulAttempts = 0;
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376 while( pucReturn == NULL )
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378 /* Look through the buffers to find one that is not in use by
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380 for( x = 0; x < emacNUM_BUFFERS; x++ )
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382 if( ucBufferInUse[ x ] == pdFALSE )
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384 ucBufferInUse[ x ] = pdTRUE;
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385 pucReturn = ( unsigned char * ) &( xEthernetBuffers[ x ][ 0 ] );
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390 /* Was a buffer found? */
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391 if( pucReturn == NULL )
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395 if( ulAttempts >= emacBUFFER_WAIT_ATTEMPTS )
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400 /* Wait then look again. */
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401 vTaskDelay( emacBUFFER_WAIT_DELAY_ms );
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407 /*-----------------------------------------------------------*/
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409 static void prvReturnBuffer( unsigned char *pucBuffer )
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413 /* Return a buffer to the pool of free buffers. */
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414 for( ul = 0; ul < emacNUM_BUFFERS; ul++ )
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416 if( &( xEthernetBuffers[ ul ][ 0 ] ) == ( void * ) pucBuffer )
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418 ucBufferInUse[ ul ] = pdFALSE;
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423 /*-----------------------------------------------------------*/
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425 static void prvResetEverything( void )
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427 /* Temporary code just to see if this gets called. This function has not
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428 been implemented. */
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429 portDISABLE_INTERRUPTS();
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432 /*-----------------------------------------------------------*/
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434 static unsigned long prvCheckRxFifoStatus( void )
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436 unsigned long ulReturn = 0;
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438 if( ( xCurrentRxDesc->status & ACT ) != 0 )
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440 /* Current descriptor is still active. */
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442 else if( ( xCurrentRxDesc->status & FE ) != 0 )
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444 /* Frame error. Clear the error. */
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445 xCurrentRxDesc->status &= ~( FP1 | FP0 | FE );
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446 xCurrentRxDesc->status &= ~( RMAF | RRF | RTLF | RTSF | PRE | CERF );
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447 xCurrentRxDesc->status |= ACT;
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448 xCurrentRxDesc = xCurrentRxDesc->next;
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450 if( EDMAC.EDRRR.LONG == 0x00000000UL )
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452 /* Restart Ethernet if it has stopped. */
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453 EDMAC.EDRRR.LONG = 0x00000001UL;
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458 /* The descriptor contains a frame. Because of the size of the buffers
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459 the frame should always be complete. */
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460 if( (xCurrentRxDesc->status & FP0) == FP0 )
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462 ulReturn = xCurrentRxDesc->size;
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466 /* Do not expect to get here. */
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467 prvResetEverything();
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473 /*-----------------------------------------------------------*/
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475 static void prvSetupPortPinsAndReset( void )
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477 /* Initialisation code taken from Renesas example project. */
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479 PFC.PACRL4.BIT.PA12MD = 0x7; /* Set TX_CLK input (EtherC) */
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480 PFC.PACRL3.BIT.PA11MD = 0x7; /* Set TX_EN output (EtherC) */
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481 PFC.PACRL3.BIT.PA10MD = 0x7; /* Set MII_TXD0 output (EtherC) */
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482 PFC.PACRL3.BIT.PA9MD = 0x7; /* Set MII_TXD1 output (EtherC) */
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483 PFC.PACRL3.BIT.PA8MD = 0x7; /* Set MII_TXD2 output (EtherC) */
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484 PFC.PACRL2.BIT.PA7MD = 0x7; /* Set MII_TXD3 output (EtherC) */
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485 PFC.PACRL2.BIT.PA6MD = 0x7; /* Set TX_ER output (EtherC) */
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486 PFC.PDCRH4.BIT.PD31MD = 0x7; /* Set RX_DV input (EtherC) */
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487 PFC.PDCRH4.BIT.PD30MD = 0x7; /* Set RX_ER input (EtherC) */
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488 PFC.PDCRH4.BIT.PD29MD = 0x7; /* Set MII_RXD3 input (EtherC) */
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489 PFC.PDCRH4.BIT.PD28MD = 0x7; /* Set MII_RXD2 input (EtherC) */
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490 PFC.PDCRH3.BIT.PD27MD = 0x7; /* Set MII_RXD1 input (EtherC) */
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491 PFC.PDCRH3.BIT.PD26MD = 0x7; /* Set MII_RXD0 input (EtherC) */
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492 PFC.PDCRH3.BIT.PD25MD = 0x7; /* Set RX_CLK input (EtherC) */
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493 PFC.PDCRH3.BIT.PD24MD = 0x7; /* Set CRS input (EtherC) */
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494 PFC.PDCRH2.BIT.PD23MD = 0x7; /* Set COL input (EtherC) */
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495 PFC.PDCRH2.BIT.PD22MD = 0x7; /* Set WOL output (EtherC) */
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496 PFC.PDCRH2.BIT.PD21MD = 0x7; /* Set EXOUT output (EtherC) */
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497 PFC.PDCRH2.BIT.PD20MD = 0x7; /* Set MDC output (EtherC) */
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498 PFC.PDCRH1.BIT.PD19MD = 0x7; /* Set LINKSTA input (EtherC) */
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499 PFC.PDCRH1.BIT.PD18MD = 0x7; /* Set MDIO input/output (EtherC) */
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501 STB.CR4.BIT._ETHER = 0x0;
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502 EDMAC.EDMR.BIT.SWR = 1;
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504 /* Crude wait for reset to complete. */
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505 vTaskDelay( 500 / portTICK_RATE_MS );
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507 /*-----------------------------------------------------------*/
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509 static void prvConfigureEtherCAndEDMAC( void )
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511 /* Initialisation code taken from Renesas example project. */
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513 /* TODO: Check bit 5 */
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514 EtherC.ECSR.LONG = 0x00000037; /* Clear all EtherC statuS BFR, PSRTO, LCHNG, MPD, ICD */
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516 /* TODO: Check bit 5 */
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517 EtherC.ECSIPR.LONG = 0x00000020; /* Disable EtherC status change interrupt */
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518 EtherC.RFLR.LONG = 1518; /* Ether payload is 1500+ CRC */
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519 EtherC.IPGR.LONG = 0x00000014; /* Intergap is 96-bit time */
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522 EDMAC.EESR.LONG = 0x47FF0F9F; /* Clear all EtherC and EDMAC status bits */
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523 EDMAC.RDLAR = ( void * ) xCurrentRxDesc; /* Initialaize Rx Descriptor List Address */
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524 EDMAC.TDLAR = &( xTxDescriptors[ 0 ] ); /* Initialaize Tx Descriptor List Address */
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525 EDMAC.TRSCER.LONG = 0x00000000; /* Copy-back status is RFE & TFE only */
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526 EDMAC.TFTR.LONG = 0x00000000; /* Threshold of Tx_FIFO */
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527 EDMAC.FDR.LONG = 0x00000000; /* Transmit fifo & receive fifo is 256 bytes */
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528 EDMAC.RMCR.LONG = 0x00000003; /* Receive function is normal mode(continued) */
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530 /* Set the EDMAC interrupt priority - the interrupt priority must be
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531 configKERNEL_INTERRUPT_PRIORITY no matter which peripheral is used to
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532 generate the tick interrupt. */
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533 INTC.IPR19.BIT._EDMAC = portKERNEL_INTERRUPT_PRIORITY;
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534 EDMAC.EESIPR.LONG = emacTX_END_INTERRUPT | emacRX_END_INTERRUPT; /* Enable Rx and Tx end interrupts. */
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536 /* Clear the interrupt flag. */
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537 CMT0.CMCSR.BIT.CMF = 0;
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539 /*-----------------------------------------------------------*/
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541 void vEMAC_ISR_Handler( void )
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543 unsigned long ul = EDMAC.EESR.LONG;
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544 long lHigherPriorityTaskWoken = pdFALSE;
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545 extern xSemaphoreHandle xEMACSemaphore;
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546 static long ulTxEndInts = 0;
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548 /* Has a Tx end occurred? */
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549 if( ul & emacTX_END_INTERRUPT )
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552 if( ulTxEndInts >= 2 )
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554 /* Only return the buffer to the pool once both Txes have completed. */
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555 prvReturnBuffer( ( void * ) xTxDescriptors[ 0 ].buf_p );
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558 EDMAC.EESR.LONG = emacTX_END_INTERRUPT;
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561 /* Has an Rx end occurred? */
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562 if( ul & emacRX_END_INTERRUPT )
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564 /* Make sure the Ethernet task is not blocked waiting for a packet. */
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565 xSemaphoreGiveFromISR( xEMACSemaphore, &lHigherPriorityTaskWoken );
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566 portYIELD_FROM_ISR( lHigherPriorityTaskWoken );
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567 EDMAC.EESR.LONG = emacRX_END_INTERRUPT;
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