2 FreeRTOS V8.2.3 - Copyright (C) 2015 Real Time Engineers Ltd.
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5 VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
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7 This file is part of the FreeRTOS distribution.
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9 FreeRTOS is free software; you can redistribute it and/or modify it under
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10 the terms of the GNU General Public License (version 2) as published by the
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11 Free Software Foundation >>>> AND MODIFIED BY <<<< the FreeRTOS exception.
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13 ***************************************************************************
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14 >>! NOTE: The modification to the GPL is included to allow you to !<<
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15 >>! distribute a combined work that includes FreeRTOS without being !<<
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16 >>! obliged to provide the source code for proprietary components !<<
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17 >>! outside of the FreeRTOS kernel. !<<
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18 ***************************************************************************
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20 FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
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21 WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
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22 FOR A PARTICULAR PURPOSE. Full license text is available on the following
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23 link: http://www.freertos.org/a00114.html
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25 ***************************************************************************
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27 * FreeRTOS provides completely free yet professionally developed, *
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28 * robust, strictly quality controlled, supported, and cross *
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29 * platform software that is more than just the market leader, it *
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30 * is the industry's de facto standard. *
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32 * Help yourself get started quickly while simultaneously helping *
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33 * to support the FreeRTOS project by purchasing a FreeRTOS *
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34 * tutorial book, reference manual, or both: *
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35 * http://www.FreeRTOS.org/Documentation *
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37 ***************************************************************************
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39 http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading
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40 the FAQ page "My application does not run, what could be wrong?". Have you
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41 defined configASSERT()?
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43 http://www.FreeRTOS.org/support - In return for receiving this top quality
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44 embedded software for free we request you assist our global community by
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45 participating in the support forum.
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47 http://www.FreeRTOS.org/training - Investing in training allows your team to
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48 be as productive as possible as early as possible. Now you can receive
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49 FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers
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50 Ltd, and the world's leading authority on the world's leading RTOS.
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52 http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
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53 including FreeRTOS+Trace - an indispensable productivity tool, a DOS
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54 compatible FAT file system, and our tiny thread aware UDP/IP stack.
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56 http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.
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57 Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.
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59 http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High
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60 Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS
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61 licenses offer ticketed support, indemnification and commercial middleware.
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63 http://www.SafeRTOS.com - High Integrity Systems also provide a safety
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64 engineered and independently SIL3 certified version for use in safety and
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65 mission critical applications that require provable dependability.
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70 /* Hardware specific includes. */
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71 #include "iodefine.h"
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72 #include "typedefine.h"
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73 #include "hwEthernet.h"
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74 #include "hwEthernetPhy.h"
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76 /* FreeRTOS includes. */
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77 #include "FreeRTOS.h"
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82 #include "net/uip.h"
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84 /* The time to wait between attempts to obtain a free buffer. */
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85 #define emacBUFFER_WAIT_DELAY_ms ( 3 / portTICK_PERIOD_MS )
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87 /* The number of times emacBUFFER_WAIT_DELAY_ms should be waited before giving
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88 up on attempting to obtain a free buffer all together. */
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89 #define emacBUFFER_WAIT_ATTEMPTS ( 30 )
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91 /* The number of Rx descriptors. */
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92 #define emacNUM_RX_DESCRIPTORS 3
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94 /* The number of Tx descriptors. When using uIP there is not point in having
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96 #define emacNUM_TX_BUFFERS 2
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98 /* The total number of EMAC buffers to allocate. */
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99 #define emacNUM_BUFFERS ( emacNUM_RX_DESCRIPTORS + emacNUM_TX_BUFFERS )
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101 /* The time to wait for the Tx descriptor to become free. */
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102 #define emacTX_WAIT_DELAY_ms ( 10 / portTICK_PERIOD_MS )
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104 /* The total number of times to wait emacTX_WAIT_DELAY_ms for the Tx descriptor to
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106 #define emacTX_WAIT_ATTEMPTS ( 5 )
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108 /* Only Rx end and Tx end interrupts are used by this driver. */
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109 #define emacTX_END_INTERRUPT ( 1UL << 21UL )
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110 #define emacRX_END_INTERRUPT ( 1UL << 18UL )
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112 /*-----------------------------------------------------------*/
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114 /* The buffers and descriptors themselves. */
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115 #pragma section RX_DESCR
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116 ethfifo xRxDescriptors[ emacNUM_RX_DESCRIPTORS ];
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117 #pragma section TX_DESCR
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118 ethfifo xTxDescriptors[ emacNUM_TX_BUFFERS ];
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119 #pragma section _ETHERNET_BUFFERS
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120 char xEthernetBuffers[ emacNUM_BUFFERS ][ UIP_BUFSIZE ];
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123 /* Used to indicate which buffers are free and which are in use. If an index
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124 contains 0 then the corresponding buffer in xEthernetBuffers is free, otherwise
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125 the buffer is in use or about to be used. */
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126 static unsigned char ucBufferInUse[ emacNUM_BUFFERS ];
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128 /*-----------------------------------------------------------*/
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131 * Initialise both the Rx and Tx descriptors.
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133 static void prvInitialiseDescriptors( void );
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136 * Return a pointer to a free buffer within xEthernetBuffers.
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138 static unsigned char *prvGetNextBuffer( void );
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141 * Return a buffer to the list of free buffers.
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143 static void prvReturnBuffer( unsigned char *pucBuffer );
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146 * Examine the status of the next Rx FIFO to see if it contains new data.
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148 static unsigned long prvCheckRxFifoStatus( void );
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151 * Setup the microcontroller for communication with the PHY.
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153 static void prvSetupPortPinsAndReset( void );
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156 * Configure the Ethernet interface peripherals.
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158 static void prvConfigureEtherCAndEDMAC( void );
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161 * Something has gone wrong with the descriptor usage. Reset all the buffers
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164 static void prvResetEverything( void );
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166 /*-----------------------------------------------------------*/
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168 /* Points to the Rx descriptor currently in use. */
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169 static ethfifo *xCurrentRxDesc = NULL;
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171 /* The buffer used by the uIP stack to both receive and send. This points to
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172 one of the Ethernet buffers when its actually in use. */
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173 unsigned char *uip_buf = NULL;
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175 /*-----------------------------------------------------------*/
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177 void vInitEmac( void )
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179 /* Setup the SH hardware for MII communications. */
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180 prvSetupPortPinsAndReset();
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182 /* Set the Rx and Tx descriptors into their initial state. */
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183 prvInitialiseDescriptors();
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185 /* Set the MAC address into the ETHERC */
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186 EtherC.MAHR = ( ( unsigned long ) configMAC_ADDR0 << 24UL ) |
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187 ( ( unsigned long ) configMAC_ADDR1 << 16UL ) |
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188 ( ( unsigned long ) configMAC_ADDR2 << 8UL ) |
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189 ( unsigned long ) configMAC_ADDR3;
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191 EtherC.MALR.BIT.MA = ( ( unsigned long ) configMAC_ADDR4 << 8UL ) |
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192 ( unsigned long ) configMAC_ADDR5;
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194 /* Perform rest of interface hardware configuration. */
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195 prvConfigureEtherCAndEDMAC();
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197 /* Nothing received yet, so uip_buf points nowhere. */
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200 /* Initialize the PHY */
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203 /*-----------------------------------------------------------*/
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205 void vEMACWrite( void )
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209 /* Wait until the second transmission of the last packet has completed. */
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210 for( x = 0; x < emacTX_WAIT_ATTEMPTS; x++ )
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212 if( ( xTxDescriptors[ 1 ].status & ACT ) != 0 )
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214 /* Descriptor is still active. */
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215 vTaskDelay( emacTX_WAIT_DELAY_ms );
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223 /* Is the descriptor free after waiting for it? */
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224 if( ( xTxDescriptors[ 1 ].status & ACT ) != 0 )
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226 /* Something has gone wrong. */
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227 prvResetEverything();
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230 /* Setup both descriptors to transmit the frame. */
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231 xTxDescriptors[ 0 ].buf_p = ( char * ) uip_buf;
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232 xTxDescriptors[ 0 ].bufsize = uip_len;
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233 xTxDescriptors[ 1 ].buf_p = ( char * ) uip_buf;
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234 xTxDescriptors[ 1 ].bufsize = uip_len;
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236 /* uip_buf is being sent by the Tx descriptor. Allocate a new buffer
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237 for use by the stack. */
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238 uip_buf = prvGetNextBuffer();
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240 /* Clear previous settings and go. */
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241 xTxDescriptors[0].status &= ~( FP1 | FP0 );
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242 xTxDescriptors[0].status |= ( FP1 | FP0 | ACT );
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243 xTxDescriptors[1].status &= ~( FP1 | FP0 );
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244 xTxDescriptors[1].status |= ( FP1 | FP0 | ACT );
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246 EDMAC.EDTRR.LONG = 0x00000001;
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248 /*-----------------------------------------------------------*/
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250 unsigned long ulEMACRead( void )
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252 unsigned long ulBytesReceived;
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254 ulBytesReceived = prvCheckRxFifoStatus();
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256 if( ulBytesReceived > 0 )
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258 xCurrentRxDesc->status &= ~( FP1 | FP0 );
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259 xCurrentRxDesc->status |= ACT;
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261 if( EDMAC.EDRRR.LONG == 0x00000000L )
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263 /* Restart Ethernet if it has stopped */
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264 EDMAC.EDRRR.LONG = 0x00000001L;
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267 /* Mark the pxDescriptor buffer as free as uip_buf is going to be set to
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268 the buffer that contains the received data. */
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269 prvReturnBuffer( uip_buf );
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271 uip_buf = ( void * ) xCurrentRxDesc->buf_p;
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273 /* Move onto the next buffer in the ring. */
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274 xCurrentRxDesc = xCurrentRxDesc->next;
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277 return ulBytesReceived;
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279 /*-----------------------------------------------------------*/
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281 long lEMACWaitForLink( void )
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285 /* Set the link status. */
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286 switch( phyStatus() )
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288 /* Half duplex link */
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289 case PHY_LINK_100H:
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291 EtherC.ECMR.BIT.DM = 0;
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295 /* Full duplex link */
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296 case PHY_LINK_100F:
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298 EtherC.ECMR.BIT.DM = 1;
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307 if( lReturn == pdPASS )
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309 /* Enable receive and transmit. */
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310 EtherC.ECMR.BIT.RE = 1;
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311 EtherC.ECMR.BIT.TE = 1;
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313 /* Enable EDMAC receive */
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314 EDMAC.EDRRR.LONG = 0x1;
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319 /*-----------------------------------------------------------*/
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321 static void prvInitialiseDescriptors( void )
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323 ethfifo *pxDescriptor;
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326 for( x = 0; x < emacNUM_BUFFERS; x++ )
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328 /* Ensure none of the buffers are shown as in use at the start. */
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329 ucBufferInUse[ x ] = pdFALSE;
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332 /* Initialise the Rx descriptors. */
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333 for( x = 0; x < emacNUM_RX_DESCRIPTORS; x++ )
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335 pxDescriptor = &( xRxDescriptors[ x ] );
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336 pxDescriptor->buf_p = &( xEthernetBuffers[ x ][ 0 ] );
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338 pxDescriptor->bufsize = UIP_BUFSIZE;
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339 pxDescriptor->size = 0;
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340 pxDescriptor->status = ACT;
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341 pxDescriptor->next = &xRxDescriptors[ x + 1 ];
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343 /* Mark this buffer as in use. */
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344 ucBufferInUse[ x ] = pdTRUE;
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347 /* The last descriptor points back to the start. */
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348 pxDescriptor->status |= DL;
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349 pxDescriptor->next = &xRxDescriptors[ 0 ];
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351 /* Initialise the Tx descriptors. */
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352 for( x = 0; x < emacNUM_TX_BUFFERS; x++ )
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354 pxDescriptor = &( xTxDescriptors[ x ] );
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356 /* A buffer is not allocated to the Tx descriptor until a send is
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357 actually required. */
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358 pxDescriptor->buf_p = NULL;
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360 pxDescriptor->bufsize = UIP_BUFSIZE;
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361 pxDescriptor->size = 0;
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362 pxDescriptor->status = 0;
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363 pxDescriptor->next = &xTxDescriptors[ x + 1 ];
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366 /* The last descriptor points back to the start. */
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367 pxDescriptor->status |= DL;
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368 pxDescriptor->next = &( xTxDescriptors[ 0 ] );
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370 /* Use the first Rx descriptor to start with. */
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371 xCurrentRxDesc = &( xRxDescriptors[ 0 ] );
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373 /*-----------------------------------------------------------*/
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375 static unsigned char *prvGetNextBuffer( void )
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378 unsigned char *pucReturn = NULL;
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379 unsigned long ulAttempts = 0;
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381 while( pucReturn == NULL )
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383 /* Look through the buffers to find one that is not in use by
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385 for( x = 0; x < emacNUM_BUFFERS; x++ )
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387 if( ucBufferInUse[ x ] == pdFALSE )
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389 ucBufferInUse[ x ] = pdTRUE;
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390 pucReturn = ( unsigned char * ) &( xEthernetBuffers[ x ][ 0 ] );
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395 /* Was a buffer found? */
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396 if( pucReturn == NULL )
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400 if( ulAttempts >= emacBUFFER_WAIT_ATTEMPTS )
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405 /* Wait then look again. */
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406 vTaskDelay( emacBUFFER_WAIT_DELAY_ms );
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412 /*-----------------------------------------------------------*/
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414 static void prvReturnBuffer( unsigned char *pucBuffer )
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418 /* Return a buffer to the pool of free buffers. */
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419 for( ul = 0; ul < emacNUM_BUFFERS; ul++ )
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421 if( &( xEthernetBuffers[ ul ][ 0 ] ) == ( void * ) pucBuffer )
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423 ucBufferInUse[ ul ] = pdFALSE;
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428 /*-----------------------------------------------------------*/
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430 static void prvResetEverything( void )
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432 /* Temporary code just to see if this gets called. This function has not
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433 been implemented. */
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434 portDISABLE_INTERRUPTS();
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437 /*-----------------------------------------------------------*/
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439 static unsigned long prvCheckRxFifoStatus( void )
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441 unsigned long ulReturn = 0;
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443 if( ( xCurrentRxDesc->status & ACT ) != 0 )
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445 /* Current descriptor is still active. */
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447 else if( ( xCurrentRxDesc->status & FE ) != 0 )
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449 /* Frame error. Clear the error. */
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450 xCurrentRxDesc->status &= ~( FP1 | FP0 | FE );
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451 xCurrentRxDesc->status &= ~( RMAF | RRF | RTLF | RTSF | PRE | CERF );
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452 xCurrentRxDesc->status |= ACT;
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453 xCurrentRxDesc = xCurrentRxDesc->next;
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455 if( EDMAC.EDRRR.LONG == 0x00000000UL )
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457 /* Restart Ethernet if it has stopped. */
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458 EDMAC.EDRRR.LONG = 0x00000001UL;
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463 /* The descriptor contains a frame. Because of the size of the buffers
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464 the frame should always be complete. */
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465 if( (xCurrentRxDesc->status & FP0) == FP0 )
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467 ulReturn = xCurrentRxDesc->size;
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471 /* Do not expect to get here. */
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472 prvResetEverything();
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478 /*-----------------------------------------------------------*/
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480 static void prvSetupPortPinsAndReset( void )
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482 /* Initialisation code taken from Renesas example project. */
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484 PFC.PACRL4.BIT.PA12MD = 0x7; /* Set TX_CLK input (EtherC) */
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485 PFC.PACRL3.BIT.PA11MD = 0x7; /* Set TX_EN output (EtherC) */
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486 PFC.PACRL3.BIT.PA10MD = 0x7; /* Set MII_TXD0 output (EtherC) */
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487 PFC.PACRL3.BIT.PA9MD = 0x7; /* Set MII_TXD1 output (EtherC) */
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488 PFC.PACRL3.BIT.PA8MD = 0x7; /* Set MII_TXD2 output (EtherC) */
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489 PFC.PACRL2.BIT.PA7MD = 0x7; /* Set MII_TXD3 output (EtherC) */
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490 PFC.PACRL2.BIT.PA6MD = 0x7; /* Set TX_ER output (EtherC) */
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491 PFC.PDCRH4.BIT.PD31MD = 0x7; /* Set RX_DV input (EtherC) */
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492 PFC.PDCRH4.BIT.PD30MD = 0x7; /* Set RX_ER input (EtherC) */
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493 PFC.PDCRH4.BIT.PD29MD = 0x7; /* Set MII_RXD3 input (EtherC) */
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494 PFC.PDCRH4.BIT.PD28MD = 0x7; /* Set MII_RXD2 input (EtherC) */
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495 PFC.PDCRH3.BIT.PD27MD = 0x7; /* Set MII_RXD1 input (EtherC) */
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496 PFC.PDCRH3.BIT.PD26MD = 0x7; /* Set MII_RXD0 input (EtherC) */
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497 PFC.PDCRH3.BIT.PD25MD = 0x7; /* Set RX_CLK input (EtherC) */
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498 PFC.PDCRH3.BIT.PD24MD = 0x7; /* Set CRS input (EtherC) */
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499 PFC.PDCRH2.BIT.PD23MD = 0x7; /* Set COL input (EtherC) */
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500 PFC.PDCRH2.BIT.PD22MD = 0x7; /* Set WOL output (EtherC) */
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501 PFC.PDCRH2.BIT.PD21MD = 0x7; /* Set EXOUT output (EtherC) */
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502 PFC.PDCRH2.BIT.PD20MD = 0x7; /* Set MDC output (EtherC) */
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503 PFC.PDCRH1.BIT.PD19MD = 0x7; /* Set LINKSTA input (EtherC) */
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504 PFC.PDCRH1.BIT.PD18MD = 0x7; /* Set MDIO input/output (EtherC) */
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506 STB.CR4.BIT._ETHER = 0x0;
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507 EDMAC.EDMR.BIT.SWR = 1;
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509 /* Crude wait for reset to complete. */
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510 vTaskDelay( 500 / portTICK_PERIOD_MS );
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512 /*-----------------------------------------------------------*/
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514 static void prvConfigureEtherCAndEDMAC( void )
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516 /* Initialisation code taken from Renesas example project. */
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518 /* TODO: Check bit 5 */
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519 EtherC.ECSR.LONG = 0x00000037; /* Clear all EtherC statuS BFR, PSRTO, LCHNG, MPD, ICD */
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521 /* TODO: Check bit 5 */
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522 EtherC.ECSIPR.LONG = 0x00000020; /* Disable EtherC status change interrupt */
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523 EtherC.RFLR.LONG = 1518; /* Ether payload is 1500+ CRC */
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524 EtherC.IPGR.LONG = 0x00000014; /* Intergap is 96-bit time */
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527 EDMAC.EESR.LONG = 0x47FF0F9F; /* Clear all EtherC and EDMAC status bits */
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528 EDMAC.RDLAR = ( void * ) xCurrentRxDesc; /* Initialaize Rx Descriptor List Address */
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529 EDMAC.TDLAR = &( xTxDescriptors[ 0 ] ); /* Initialaize Tx Descriptor List Address */
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530 EDMAC.TRSCER.LONG = 0x00000000; /* Copy-back status is RFE & TFE only */
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531 EDMAC.TFTR.LONG = 0x00000000; /* Threshold of Tx_FIFO */
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532 EDMAC.FDR.LONG = 0x00000000; /* Transmit fifo & receive fifo is 256 bytes */
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533 EDMAC.RMCR.LONG = 0x00000003; /* Receive function is normal mode(continued) */
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535 /* Set the EDMAC interrupt priority - the interrupt priority must be
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536 configKERNEL_INTERRUPT_PRIORITY no matter which peripheral is used to
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537 generate the tick interrupt. */
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538 INTC.IPR19.BIT._EDMAC = portKERNEL_INTERRUPT_PRIORITY;
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539 EDMAC.EESIPR.LONG = emacTX_END_INTERRUPT | emacRX_END_INTERRUPT; /* Enable Rx and Tx end interrupts. */
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541 /* Clear the interrupt flag. */
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542 CMT0.CMCSR.BIT.CMF = 0;
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544 /*-----------------------------------------------------------*/
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546 void vEMAC_ISR_Handler( void )
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548 unsigned long ul = EDMAC.EESR.LONG;
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549 long lHigherPriorityTaskWoken = pdFALSE;
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550 extern SemaphoreHandle_t xEMACSemaphore;
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551 static long ulTxEndInts = 0;
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553 /* Has a Tx end occurred? */
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554 if( ul & emacTX_END_INTERRUPT )
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557 if( ulTxEndInts >= 2 )
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559 /* Only return the buffer to the pool once both Txes have completed. */
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560 prvReturnBuffer( ( void * ) xTxDescriptors[ 0 ].buf_p );
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563 EDMAC.EESR.LONG = emacTX_END_INTERRUPT;
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566 /* Has an Rx end occurred? */
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567 if( ul & emacRX_END_INTERRUPT )
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569 /* Make sure the Ethernet task is not blocked waiting for a packet. */
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570 xSemaphoreGiveFromISR( xEMACSemaphore, &lHigherPriorityTaskWoken );
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571 portYIELD_FROM_ISR( lHigherPriorityTaskWoken );
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572 EDMAC.EESR.LONG = emacRX_END_INTERRUPT;
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