2 * Copyright (C) 2017 C-SKY Microsystems Co., Ltd. All rights reserved.
4 * Licensed under the Apache License, Version 2.0 (the "License");
5 * you may not use this file except in compliance with the License.
6 * You may obtain a copy of the License at
8 * http://www.apache.org/licenses/LICENSE-2.0
10 * Unless required by applicable law or agreed to in writing, software
11 * distributed under the License is distributed on an "AS IS" BASIS,
12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 * See the License for the specific language governing permissions and
14 * limitations under the License.
17 /******************************************************************************
19 * @brief source file for the pinmux
22 ******************************************************************************/
28 ({ unsigned int __v = (*(volatile unsigned int *) (addr)); __v; })
30 #define writel(b,addr) (void)((*(volatile unsigned int *) (addr)) = (b))
32 /*******************************************************************************
33 * function: hobbit_ioreuse_inital
36 * initial hobbit_pinmux
37 *******************************************************************************/
39 void hobbit_ioreuse_initial(void)
43 value = readl(HOBBIT1_2_GIPO0_PORTCTL_REG);
44 value &= ~(GPIO0_REUSE_DIS);
45 writel(value, HOBBIT1_2_GIPO0_PORTCTL_REG);
48 int32_t pin_mux(pin_name_t pin, uint16_t function)
51 unsigned int reg_val = 0;
56 if (pin <= PB3_SPI0MISO_PWM5_I2SSD) {
57 if (pin <= PA5_RTS0_PWM1_SPI0SSN_TRIG1) {
59 /* gpio data source select */
60 val = readl(HOBBIT1_2_GIPO0_PORTCTL_REG);
61 val &= ~(1 << offset);
62 writel(val, HOBBIT1_2_GIPO0_PORTCTL_REG);
64 } else if (pin >= PB0_SCL0_PWM2_I2SMCLK) {
66 /* gpio data source select */
67 val = readl(HOBBIT1_2_GIPO1_PORTCTL_REG);
68 val &= ~(1 << offset);
69 writel(val, HOBBIT1_2_GIPO1_PORTCTL_REG);
73 if ((pin >= PA6_SPI0MOSI_PWM6_SCL0) && (pin <= PA27_RTS2_I2SSD_ADC13)) {
75 /* gpio data source select */
76 val = readl(HOBBIT1_2_GIPO0_PORTCTL_REG);
77 val &= ~(1 << offset);
78 writel(val, HOBBIT1_2_GIPO0_PORTCTL_REG);
84 if ((pin >= PA6_SPI0MOSI_PWM6_SCL0) && (pin <= PA27_RTS2_I2SSD_ADC13)) {
87 /* gpio data source select */
88 val = readl(HOBBIT1_2_GIPO0_PORTCTL_REG);
90 writel(val, HOBBIT1_2_GIPO0_PORTCTL_REG);
92 if (pin <= PA11_ACMP0N_ADC3_RXD0) {
94 reg_val = (0x3 << (offset * 2));
95 /* reuse function select */
96 val = readl(HOBBIT1_2_IOMUX0L_REG);
98 val |= (function << (2 * offset));
99 writel(val, HOBBIT1_2_IOMUX0L_REG);
103 reg_val = (0x3 << (offset * 2));
104 /* reuse function select */
105 val = readl(HOBBIT1_2_IOMUX0H_REG);
107 val |= (function << (2 * offset));
108 writel(val, HOBBIT1_2_IOMUX0H_REG);
113 if ((pin >= PA0_TRIG0_ACMP1P_TCK) && (pin <= PB3_SPI0MISO_PWM5_I2SSD)) {
114 if (pin >= PB0_SCL0_PWM2_I2SMCLK) {
116 val = readl(HOBBIT1_2_GIPO1_PORTCTL_REG);
117 val |= (1 << offset);
118 writel(val, HOBBIT1_2_GIPO1_PORTCTL_REG);
121 reg_val = (0x3 << (offset * 2));
122 /* reuse function select */
123 val = readl(HOBBIT1_2_IOMUX0L_REG);
125 val |= (function << (2 * offset));
126 writel(val, HOBBIT1_2_IOMUX0L_REG);
130 if (pin <= PA5_RTS0_PWM1_SPI0SSN_TRIG1) {
132 /* gpio data source select */
133 val = readl(HOBBIT1_2_GIPO0_PORTCTL_REG);
134 val |= (1 << offset);
135 writel(val, HOBBIT1_2_GIPO0_PORTCTL_REG);
137 reg_val = (0x3 << (offset * 2));
138 /* reuse function select */
139 val = readl(HOBBIT1_2_IOMUX0L_REG);
141 val |= (function << (2 * offset));
142 writel(val, HOBBIT1_2_IOMUX0L_REG);
147 if (pin > PA27_RTS2_I2SSD_ADC13) {
148 offset = pin - PC0_SCL1_CTS1_PWM10_ADC14;
149 reg_val = (0x3 << (offset *2));
150 val = readl(HOBBIT1_2_IOMUX1L_REG);
152 val |= (function << (2 * offset));
153 writel(val, HOBBIT1_2_IOMUX1L_REG);