2 * Copyright (C) 2017 C-SKY Microsystems Co., Ltd. All rights reserved.
4 * Licensed under the Apache License, Version 2.0 (the "License");
5 * you may not use this file except in compliance with the License.
6 * You may obtain a copy of the License at
8 * http://www.apache.org/licenses/LICENSE-2.0
10 * Unless required by applicable law or agreed to in writing, software
11 * distributed under the License is distributed on an "AS IS" BASIS,
12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 * See the License for the specific language governing permissions and
14 * limitations under the License.
17 /******************************************************************************
19 * @brief source file for the devices
22 ******************************************************************************/
25 #include <drv_usart.h>
27 #include <drv_timer.h>
33 #include <drv_eflash.h>
40 //typedef int32_t int32_t;
43 ({ unsigned int __v = (*(volatile unsigned int *) (addr)); __v; })
45 #define writel(b,addr) (void)((*(volatile unsigned int *) (addr)) = (b))
52 const sg_usi_config[CONFIG_USI_NUM] = {
53 {CSKY_USI0_BASE, USI0_IRQn},
54 {CSKY_USI1_BASE, USI1_IRQn},
61 uint16_t cfg_idx; //idx of sg_usi_config[]
64 const static usi_pin_map_t s_usi_pin_map[] = {
66 PA10_UART0CTS_USI0SCLK_SPU4_I2C0SCL,
67 PA11_UART0RTS_USI0SD0_SPU5_I2C0SDA,
68 PA12_XX_USI0SD1_XX_UART2RX,
69 PA13_XX_USI0NSS_XX_UART2TX,
74 PA16_SPI0CS0_PWMTRIG0_XX_USI1SCLK,
75 PA17_SPI0MOSI_PWMTRIG1_XX_USI1SD0,
76 PA18_SPI0MISO_XX_SPU6_USI1SD1,
77 PA19_SPI0SCK_FAULT_SPU7_USI1NSS,
89 const static sg_usart_config[CONFIG_USART_NUM] = {
90 {CSKY_UART0_BASE, UART0_IRQn},
91 {CSKY_UART1_BASE, UART1_IRQn},
92 {CSKY_UART2_BASE, UART2_IRQn},
93 {CSKY_UART3_BASE, UART3_IRQn}
102 uint16_t cfg_idx; //idx of sg_usart_config[]
105 const static usart_pin_map_t s_usart_pin_map[] = {
107 PA8_UART0TX_XX_SPU2_SIROUT0,
108 PA9_UART0RX_XX_SPU3_SIRIN0,
113 PA21_UART1TX_PWM1_SPU9_SIROUT1,
114 PA20_UART1RX_PWM0_SPU8_SIRIN1,
119 PA0_I2C0SCL_SPI1CS1_SPU0_UART1TX,
120 PA1_I2C0SDA_SPI1CS2_SPU1_UART1RX,
125 PB0_UART2TX_XX_XX_SIROUT2,
126 PB1_UART2RX_XX_XX_SIRIN2,
131 PB13_UART3TX_SPI1MISO_SPU29_SIROUT3,
132 PB12_UART3RX_SPI1CS0_SPU28_SIRIN3,
139 \param[in] instance idx, must not exceed return value of target_get_usart_count()
140 \brief get usart instance.
141 \return pointer to usart instance
144 int32_t target_usart_init(pin_t tx, pin_t rx, uint32_t *base, uint32_t *irq)
148 for (idx = 0; idx < sizeof(s_usart_pin_map) / sizeof(usart_pin_map_t); idx++) {
149 if (s_usart_pin_map[idx].tx == tx && s_usart_pin_map[idx].rx == rx) {
150 *base = sg_usart_config[s_usart_pin_map[idx].cfg_idx].base;
151 *irq = sg_usart_config[s_usart_pin_map[idx].cfg_idx].irq;
153 pin_mux(s_usart_pin_map[idx].tx, s_usart_pin_map[idx].function);
154 pin_mux(s_usart_pin_map[idx].rx, s_usart_pin_map[idx].function);
155 return s_usart_pin_map[idx].cfg_idx;
162 \brief control usart flow.
163 \param[in] tx_flow The TX flow pin name
164 \param[in] rx_flow The RX flow pin name
165 \param[in] flag 0-disable, 1-enable.
166 \return 0 if setting ready ,negative for error code
168 int32_t target_usart_flowctrl_init(int32_t tx_flow, int32_t rx_flow, uint32_t flag)
173 for (idx = 0; idx < sizeof(s_usart_pin_map) / sizeof(usart_pin_map_t); idx++) {
174 if ((s_usart_pin_map[idx].cts == tx_flow) &&(s_usart_pin_map[idx].rts == rx_flow))
178 if (idx >= sizeof(s_usart_pin_map) / sizeof(usart_pin_map_t)) {
182 if ((s_usart_pin_map[idx].cts == tx_flow) && flag) {
183 pin_mux(s_usart_pin_map[idx].cts, s_usart_pin_map[idx].function);
184 } else if ((s_usart_pin_map[idx].cts == tx_flow) && (flag == 0)) {
185 pin_mux(s_usart_pin_map[idx].cts, 0xff);
190 if ((s_usart_pin_map[idx].rts == rx_flow) && flag) {
191 pin_mux(s_usart_pin_map[idx].rts, s_usart_pin_map[idx].function);
192 } else if ((s_usart_pin_map[idx].rts == rx_flow) && (flag == 0)) {
193 pin_mux(s_usart_pin_map[idx].rts, 0xff);
210 const sg_gpio_config[CONFIG_GPIO_NUM] = {
211 {CSKY_GPIO0_BASE, GPIOA_IRQn, 32, PORTA},
212 {CSKY_GPIO1_BASE, GPIOB_IRQn, 16, PORTB}
217 uint32_t cfg_idx; //idx of sg_gpio_config[]
219 const static gpio_pin_map_t s_gpio_pin_map[] = {
220 {PA0_I2C0SCL_SPI1CS1_SPU0_UART1TX ,0},
221 {PA1_I2C0SDA_SPI1CS2_SPU1_UART1RX,0},
222 {PA2_QSPI0CLK_XX_XX_XX,0},
223 {PA3_QSPI0MISO_XX_XX_XX,0},
224 {PA4_QSPI0MOSI_XX_XX_XX,0},
225 {PA5_QSPI0HOLD_XX_XX_XX,0},
226 {PA6_QSPI0WP_XX_XX_XX,0},
227 {PA7_QSPI0CS0_XX_XX_XX,0},
228 {PA8_UART0TX_XX_SPU2_SIROUT0,0},
229 {PA9_UART0RX_XX_SPU3_SIRIN0,0},
230 {PA10_UART0CTS_USI0SCLK_SPU4_I2C0SCL,0},
231 {PA11_UART0RTS_USI0SD0_SPU5_I2C0SDA,0},
232 {PA12_XX_USI0SD1_XX_UART2RX,0},
233 {PA13_XX_USI0NSS_XX_UART2TX,0},
234 {PA14_SPI0CS2_FAULT_I2C1SDA_XX,0},
235 {PA15_SPI0CS1_XX_I2C1SCL_XX,0},
236 {PA16_SPI0CS0_PWMTRIG0_XX_USI1SCLK,0},
237 {PA17_SPI0MOSI_PWMTRIG1_XX_USI1SD0,0},
238 {PA18_SPI0MISO_XX_SPU6_USI1SD1,0},
239 {PA19_SPI0SCK_FAULT_SPU7_USI1NSS,0},
240 {PA20_UART1RX_PWM0_SPU8_SIRIN1,0},
241 {PA21_UART1TX_PWM1_SPU9_SIROUT1,0},
242 {PA22_UART1CTS_PWM2_SPU10_XX,0},
243 {PA23_UART1RTS_PWM3_SPU11_XX,0},
244 {PA24_USI1NSS_PWM4_SPU12_XX,0},
245 {PA25_USI1SD1_PWM5_SPU13_XX,0},
246 {PA26_USI1SD0_PWM6_SPU14_XX,0},
247 {PA27_USI1SCLK_PWM7_SPU15_XX,0},
248 {PA28_I2C1SCL_PWM8_SPU16_XX,0},
249 {PA29_I2C1SDA_PWM9_SPU17_XX,0},
250 {PA30_I2C0SDA_PWM10_SPU18_XX,0},
251 {PA31_I2C0SCL_PWM11_SPU19_XX,0},
252 {PB0_UART2TX_XX_XX_SIROUT2,1},
253 {PB1_UART2RX_XX_XX_SIRIN2,1},
254 {PB2_UART2RTS_XX_XX_XX,1},
255 {PB3_UART2CTS_XX_XX_XX,1},
256 {PB4_XX_XX_SPU20_UART3TX,1},
257 {PB5_QSPI1CS1_XX_SPU21_UART3RX,1},
258 {PB6_QSPI1WP_XX_SPU22_XX,1},
259 {PB7_QSPI1HOLD_XX_SPU23_XX,1},
260 {PB8_QSPI1CS0_PWMTRIG0_SPU24_XX,1},
261 {PB9_QSPI1MOSI_PWMTRIG1_SPU25_XX,1},
262 {PB10_QSPI1MISO_XX_SPU26_I2C1SDA,1},
263 {PB11_QSPI1CLK_XX_SPU27_I2C1SCL,1},
264 {PB12_UART3RX_SPI1CS0_SPU28_SIRIN3,1},
265 {PB13_UART3TX_SPI1MISO_SPU29_SIROUT3,1},
266 {PB14_UART3RTS_SPI1MOSI_SPU30_XX,1},
267 {PB15_UART3CTS_SPI1SCK_SPU31_XX,1}
270 int32_t target_gpio_port_init(port_name_t port, uint32_t *base, uint32_t *irq, uint32_t *pin_num)
274 for (i = 0; i < CONFIG_GPIO_NUM; i++) {
275 if (sg_gpio_config[i].port == port) {
276 *base = sg_gpio_config[i].base;
277 *irq = sg_gpio_config[i].irq;
278 *pin_num = sg_gpio_config[i].pin_num;
287 \param[in] instance idx, must not exceed return value of target_get_gpio_count()
288 \brief get gpio instance.
289 \return pointer to gpio instance
291 int32_t target_gpio_pin_init(int32_t gpio_pin, uint32_t *port_idx)
295 for (idx = 0; idx < sizeof(s_gpio_pin_map) / sizeof(gpio_pin_map_t); idx++) {
296 if (s_gpio_pin_map[idx].gpio_pin == gpio_pin) {
297 *port_idx = s_gpio_pin_map[idx].cfg_idx;
299 pin_mux(s_gpio_pin_map[idx].gpio_pin, 0xff);
311 const sg_timer_config[CONFIG_TIMER_NUM] = {
312 {CSKY_TIM0_BASE, TIMA0_IRQn},
313 {CSKY_TIM0_BASE + 0x14, TIMA1_IRQn},
314 {CSKY_TIM1_BASE, TIMB0_IRQn},
315 {CSKY_TIM1_BASE + 0x14, TIMB1_IRQn},
316 {CSKY_TIM2_BASE, TIM34567_IRQn},
317 {CSKY_TIM2_BASE + 0x14, TIM34567_IRQn},
318 {CSKY_TIM3_BASE, TIM34567_IRQn},
319 {CSKY_TIM3_BASE + 0x14, TIM34567_IRQn},
320 {CSKY_TIM4_BASE, TIM34567_IRQn},
321 {CSKY_TIM4_BASE + 0x14, TIM34567_IRQn},
322 {CSKY_TIM5_BASE, TIM34567_IRQn},
323 {CSKY_TIM5_BASE + 0x14, TIM34567_IRQn},
324 {CSKY_TIM6_BASE, TIM34567_IRQn},
325 {CSKY_TIM6_BASE + 0x14, TIM34567_IRQn},
328 int32_t target_get_timer_count(void)
330 return CONFIG_TIMER_NUM;
333 int32_t target_get_timer(int32_t idx, uint32_t *base, uint32_t *irq)
335 if (idx >= target_get_timer_count()) {
339 *base = sg_timer_config[idx].base;
340 *irq = sg_timer_config[idx].irq;
348 const sg_sha_config[CONFIG_SHA_NUM] = {
349 {CSKY_SHA_BASE, SHA_IRQn}
353 \brief get sha instance count.
354 \return sha instance count
356 int32_t target_get_sha_count(void)
358 return CONFIG_SHA_NUM;
362 \param[in] instance idx, must not exceed return value of target_get_sha_count()
363 \brief get sha instance.
364 \return pointer to sha instance
366 int32_t target_get_sha(int32_t idx, uint32_t *base, uint32_t *irq)
368 if (idx >= target_get_sha_count()) {
372 *base = sg_sha_config[idx].base;
373 *irq = sg_sha_config[idx].irq;
381 const sg_rsa_config[CONFIG_RSA_NUM] = {
382 {CSKY_RSA_BASE, RSA_IRQn}
386 \brief get rsa instance count.
387 \return rsa instance count
389 int32_t target_get_rsa_count(void)
391 return CONFIG_RSA_NUM;
395 \param[in] instance idx, must not exceed return value of target_get_rsa_count()
396 \brief get rsa instance.
397 \return pointer to rsa instance
399 int32_t target_get_rsa(int32_t idx, uint32_t *base, uint32_t *irq)
401 if (idx >= target_get_rsa_count()) {
405 *base = sg_rsa_config[idx].base;
406 *irq = sg_rsa_config[idx].irq;
414 const sg_aes_config[CONFIG_AES_NUM] = {
415 {CSKY_AES_BASE, AES_IRQn}
419 \brief get aes instance count.
420 \return aes instance count
422 int32_t target_get_aes_count(void)
424 return CONFIG_AES_NUM;
428 \param[in] instance idx, must not exceed return value of target_get_aes_count()
429 \brief get aes instance.
430 \return pointer to aes instance
432 int32_t target_get_aes(int32_t idx, uint32_t *base, uint32_t *irq)
434 if (idx >= target_get_aes_count()) {
438 *base = sg_aes_config[idx].base;
439 *irq = sg_aes_config[idx].irq;
447 const sg_trng_config[CONFIG_TRNG_NUM] = {
448 {CSKY_TRNG_BASE, TRNG_IRQn}
452 \param[in] instance idx
453 \brief get trng instance.
454 \return pointer to trng instance
456 int32_t target_get_trng(int32_t idx, uint32_t *base)
458 *base = sg_trng_config[idx].base;
466 const sg_crc_config[CONFIG_CRC_NUM] = {
471 \param[in] instance idx
472 \brief get crc instance.
473 \return pointer to crc instance
475 int32_t target_get_crc(int32_t idx, uint32_t *base)
477 *base = sg_crc_config[idx].base;
486 const sg_iic_config[CONFIG_IIC_NUM] = {
487 {CSKY_I2C0_BASE, I2C0_IRQn},
488 {CSKY_I2C1_BASE, I2C1_IRQn}
494 uint16_t cfg_idx; //idx of sg_iic_config[]
497 const static iic_pin_map_t s_iic_pin_map[] = {
499 PA31_I2C0SCL_PWM11_SPU19_XX,
500 PA30_I2C0SDA_PWM10_SPU18_XX,
505 PA28_I2C1SCL_PWM8_SPU16_XX,
506 PA29_I2C1SDA_PWM9_SPU17_XX,
513 \param[in] instance idx, must not exceed return value of target_get_iic_count()
514 \brief get iic instance.
515 \return pointer to iic instance
517 int32_t target_iic_init(int32_t idx, uint32_t *base, uint32_t *irq)
519 if (idx >= sizeof(s_iic_pin_map) / sizeof(iic_pin_map_t)) {
523 *base = sg_iic_config[s_iic_pin_map[idx].cfg_idx].base;
524 *irq = sg_iic_config[s_iic_pin_map[idx].cfg_idx].irq;
526 pin_mux(s_iic_pin_map[idx].scl, s_iic_pin_map[idx].function);
527 pin_mux(s_iic_pin_map[idx].sda, s_iic_pin_map[idx].function);
528 return s_iic_pin_map[idx].cfg_idx;
536 const sg_rtc_config[CONFIG_RTC_NUM] = {
537 {CSKY_RTC0_BASE, RTC_IRQn},
541 int32_t target_get_rtc_count(void)
543 return CONFIG_RTC_NUM;
546 int32_t target_get_rtc(int32_t idx, uint32_t *base, uint32_t *irq)
550 if (idx >= target_get_rtc_count()) {
554 value = readl(CSKY_PMU_BASE);
556 writel(value, CSKY_PMU_BASE);
558 *base = sg_rtc_config[idx].base;
559 *irq = sg_rtc_config[idx].irq;
568 const sg_spi_config[CONFIG_SPI_NUM] = {
569 {CSKY_SPI0_BASE, SPI0_IRQn},
570 {CSKY_SPI1_BASE, SPI1_IRQn}
577 uint32_t cfg_idx; //idx of sg_iic_config[]
580 const static spi_pin_map_t s_spi_pin_map[] = {
582 PA18_SPI0MISO_XX_SPU6_USI1SD1,
583 PA17_SPI0MOSI_PWMTRIG1_XX_USI1SD0,
584 PA19_SPI0SCK_FAULT_SPU7_USI1NSS,
585 PA16_SPI0CS0_PWMTRIG0_XX_USI1SCLK,
590 PB13_UART3TX_SPI1MISO_SPU29_SIROUT3,
591 PB14_UART3RTS_SPI1MOSI_SPU30_XX,
592 PB15_UART3CTS_SPI1SCK_SPU31_XX,
593 PB12_UART3RX_SPI1CS0_SPU28_SIRIN3,
600 \param[in] instance idx, must not exceed return value of target_get_spi_count()
601 \brief get spi instance.
602 \return pointer to spi instance
604 int32_t target_spi_init(int32_t idx, uint32_t *base, uint32_t *irq, uint32_t *ssel)
606 if (idx >= sizeof(s_spi_pin_map) / sizeof(spi_pin_map_t)) {
610 *base = sg_spi_config[s_spi_pin_map[idx].cfg_idx].base;
611 *irq = sg_spi_config[s_spi_pin_map[idx].cfg_idx].irq;
612 *ssel = s_spi_pin_map[idx].ssel;
614 pin_mux(s_spi_pin_map[idx].mosi, s_spi_pin_map[idx].function);
615 pin_mux(s_spi_pin_map[idx].miso, s_spi_pin_map[idx].function);
616 pin_mux(s_spi_pin_map[idx].sclk, s_spi_pin_map[idx].function);
617 pin_mux(s_spi_pin_map[idx].ssel, s_spi_pin_map[idx].function);
619 return s_spi_pin_map[idx].cfg_idx;
627 const sg_dmac_config[CONFIG_DMAC_NUM] = {
628 {CSKY_DMAC0_BASE, DMAC_IRQn},
631 int32_t target_get_dmac_count(void)
633 return CONFIG_DMAC_NUM;
636 int32_t target_get_dmac(int32_t idx, uint32_t *base, uint32_t *irq)
638 if (idx >= target_get_dmac_count()) {
642 *base = sg_dmac_config[idx].base;
643 *irq = sg_dmac_config[idx].irq;
651 const sg_pwm_config[CONFIG_PWM_NUM] = {
652 {CSKY_PWM_BASE, PWM_IRQn},
657 uint32_t cfg_idx; //idx of sg_pwm_config[]
661 const static pwm_pin_map_t s_pwm_pin_map[] = {
662 {PA20_UART1RX_PWM0_SPU8_SIRIN1, 0, 0, 1},
663 {PA21_UART1TX_PWM1_SPU9_SIROUT1, 0, 1, 1},
664 {PA22_UART1CTS_PWM2_SPU10_XX, 0, 2, 1},
665 {PA23_UART1RTS_PWM3_SPU11_XX, 0, 3, 1},
666 {PA24_USI1NSS_PWM4_SPU12_XX, 0, 4, 1},
667 {PA25_USI1SD1_PWM5_SPU13_XX, 0, 5, 1},
668 {PA26_USI1SD0_PWM6_SPU14_XX, 0, 6, 1},
669 {PA27_USI1SCLK_PWM7_SPU15_XX, 0, 7, 1},
670 {PA28_I2C1SCL_PWM8_SPU16_XX, 0, 8, 1},
671 {PA29_I2C1SDA_PWM9_SPU17_XX, 0, 9, 1},
672 {PA30_I2C0SDA_PWM10_SPU18_XX, 0, 10, 1},
673 {PA31_I2C0SCL_PWM11_SPU19_XX, 0, 11, 1}
677 \param[in] instance idx, must not exceed return value of target_get_pwm_count()
678 \brief get pwm instance.
679 \return pointer to pwm instance
681 int32_t target_pwm_init(int32_t pwm_pin, uint32_t *ch_num, uint32_t *base, uint32_t *irq)
685 for (idx = 0; idx < sizeof(s_pwm_pin_map) / sizeof(pwm_pin_map_t); idx++) {
686 if (s_pwm_pin_map[idx].pwm_pin == pwm_pin) {
687 *base = sg_pwm_config[s_pwm_pin_map[idx].cfg_idx].base;
688 *irq = sg_pwm_config[s_pwm_pin_map[idx].cfg_idx].irq;
689 *ch_num = s_pwm_pin_map[idx].ch_num;
691 pin_mux(s_pwm_pin_map[idx].pwm_pin, s_pwm_pin_map[idx].function);
692 return s_pwm_pin_map[idx].cfg_idx;
703 const sg_wdt_config[CONFIG_WDT_NUM] = {
704 {CSKY_WDT_BASE, WDT_IRQn}
707 int32_t target_get_wdt_count(void)
709 return CONFIG_WDT_NUM;
712 int32_t target_get_wdt(int32_t idx, uint32_t *base, uint32_t *irq)
714 if (idx >= target_get_wdt_count()) {
718 *base = sg_wdt_config[idx].base;
719 *irq = sg_wdt_config[idx].irq;
723 int32_t target_get_etb_count(void)
725 return CONFIG_ETB_NUM;
728 int32_t target_get_etb(int32_t idx, uint32_t *base, uint32_t *irq)
730 if (idx >= target_get_etb_count()) {
734 // *base = sg_etb_config[idx].base;
735 // *irq = sg_etb_config[idx].irq;
743 const sg_qspi_config[CONFIG_QSPI_NUM] = {
744 {CSKY_QSPIC0_BASE, QSPIC1_IRQn},
745 {CSKY_QSPIC1_BASE, QSPIC1_IRQn}
757 const static qspi_pin_map_t s_qspi_pin_map[] = {
759 PA2_QSPI0CLK_XX_XX_XX,
760 PA3_QSPI0MISO_XX_XX_XX,
761 PA4_QSPI0MOSI_XX_XX_XX,
762 PA5_QSPI0HOLD_XX_XX_XX,
763 PA6_QSPI0WP_XX_XX_XX,
764 PA7_QSPI0CS0_XX_XX_XX,
769 PB11_QSPI1CLK_XX_SPU27_I2C1SCL,
770 PB10_QSPI1MISO_XX_SPU26_I2C1SDA,
771 PB9_QSPI1MOSI_PWMTRIG1_SPU25_XX,
772 PB7_QSPI1HOLD_XX_SPU23_XX,
773 PB6_QSPI1WP_XX_SPU22_XX,
774 PB8_QSPI1CS0_PWMTRIG0_SPU24_XX,
781 \param[in] instance idx, must not exceed return value of target_get_qspi_count()
782 \brief get qspi instance.
783 \return pointer to qspi instance
785 int32_t target_qspi_init(pin_name_t mosi, pin_name_t miso, pin_name_t sclk, pin_name_t ssel, pin_name_t wp, pin_name_t hold, uint32_t *base, uint32_t *irq)
789 for (idx = 0; idx < sizeof(s_qspi_pin_map) / sizeof(qspi_pin_map_t); idx++) {
790 if (s_qspi_pin_map[idx].mosi == mosi && s_qspi_pin_map[idx].miso == miso
791 && s_qspi_pin_map[idx].sclk == sclk && s_qspi_pin_map[idx].ssel == ssel
792 && s_qspi_pin_map[idx].hold == hold && s_qspi_pin_map[idx].wp == wp) {
794 pin_mux(s_qspi_pin_map[idx].mosi, s_qspi_pin_map[idx].function);
795 pin_mux(s_qspi_pin_map[idx].miso, s_qspi_pin_map[idx].function);
796 pin_mux(s_qspi_pin_map[idx].sclk, s_qspi_pin_map[idx].function);
797 pin_mux(s_qspi_pin_map[idx].hold, s_qspi_pin_map[idx].function);
798 pin_mux(s_qspi_pin_map[idx].wp, s_qspi_pin_map[idx].function);
799 pin_mux(s_qspi_pin_map[idx].ssel, s_qspi_pin_map[idx].function);
800 return s_qspi_pin_map[idx].cfg_idx;