2 * Copyright (C) 2017 C-SKY Microsystems Co., Ltd. All rights reserved.
4 * Licensed under the Apache License, Version 2.0 (the "License");
5 * you may not use this file except in compliance with the License.
6 * You may obtain a copy of the License at
8 * http://www.apache.org/licenses/LICENSE-2.0
10 * Unless required by applicable law or agreed to in writing, software
11 * distributed under the License is distributed on an "AS IS" BASIS,
12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 * See the License for the specific language governing permissions and
14 * limitations under the License.
17 /**************************************************************************//**
19 * @brief CSI Core Peripheral Access Layer Header File for
20 * CSKYSOC Device Series
23 ******************************************************************************/
34 #define SYSTEM_CLOCK (20000000)
37 #ifndef LSP_DEFAULT_FREQ
38 #define LSP_DEFAULT_FREQ (20000000)
41 /* ------------------------- Interrupt Number Definition ------------------------ */
45 /* ---------------------- CSKYCK801 Specific Interrupt Numbers --------------------- */
47 CORET_IRQn = 1, /* core Timer Interrupt */
48 TIMA0_IRQn = 2, /* timerA0 Interrupt */
49 TIMA1_IRQn = 3, /* timerA1 Interrupt */
50 TIM34567_IRQn = 4, /* timerC ~ timerH Interrupt */
51 WDT_IRQn = 5, /* wdt Interrupt */
52 UART0_IRQn = 6, /* uart0 Interrupt */
53 UART1_IRQn = 7, /* uart1 Interrupt */
54 UART2_IRQn = 8, /* uart2 Interrupt */
55 I2C0_IRQn = 9, /* i2c0 Interrupt */
56 I2C1_IRQn = 10, /* i2c1 Interrupt */
57 SPI1_IRQn = 11, /* spi1 Interrupt */
58 SPI0_IRQn = 12, /* spi0 Interrupt */
59 RTC_IRQn = 13, /* rtc Interrupt */
60 UART3_IRQn = 14, /* uart3 Interrupt */
61 ADC_IRQn = 15, /* adc Interrupt */
62 QSPIC1_IRQn = 16, /* qspic1 interrupt */
63 DMAC_IRQn = 17, /* dmac Interrupt */
64 PMU_IRQn = 18, /* pmu Interrupt */
65 PWM_IRQn = 19, /* pwm Interrupt */
66 USI0_IRQn = 20, /* usi0 Interrupt */
67 USI1_IRQn = 21, /* usi1 Interrupt */
68 SPU_IRQn = 22, /* spu Interrupt */
69 TIMB0_IRQn = 23, /* timerB0 Interrupt */
70 TIMB1_IRQn = 24, /* timerB1 Interrupt */
71 GPIOB_IRQn = 27, /* GPIOB Interrupt */
72 AES_IRQn = 26, /* aes Interrupt */
73 RSA_IRQn = 28, /* rsa Interrupt */
74 SHA_IRQn = 29, /* sha Interrupt */
75 TRNG_IRQn = 30, /* trng Interrupt */
79 /* ================================================================================ */
80 /* ================ Processor and Core Peripheral Section ================ */
81 /* ================================================================================ */
83 /* -------- Configuration of the CK801 Processor and Core Peripherals ------- */
84 #define __CK803_REV 0x0000U /* Core revision r0p0 */
85 #define __MPU_PRESENT 0 /* MGU present or not */
86 #define __VIC_PRIO_BITS 2 /* Number of Bits used for Priority Levels */
87 #define __Vendor_SysTickConfig 0 /* Set to 1 if different SysTick Config is used */
89 #include "core_ck802.h" /* Processor and core peripherals */
110 } ckenum_dma_device_e;
112 #define CONFIG_CRC_NUM 1
113 #define CONFIG_IIC_NUM 2
114 #define CONFIG_TRNG_NUM 1
115 #define CONFIG_AES_NUM 1
116 #define CONFIG_RSA_NUM 1
117 #define CONFIG_SHA_NUM 1
118 #define CONFIG_SPI_NUM 2
119 #define CONFIG_QSPI_NUM 2
120 #define CONFIG_PWM_NUM 1
121 #define CONFIG_TIMER_NUM 14
122 #define CONFIG_RTC_NUM 1
123 #define CONFIG_WDT_NUM 1
124 #define CONFIG_DMAC_NUM 1
125 #define CONFIG_GPIO_NUM 2
126 #define CONFIG_GPIO_PIN_NUM 43
127 #define CONFIG_USART_NUM 4
128 #define CONFIG_SPU_NUM 1
129 #define CONFIG_EFLASH_NUM 1
130 #define CONFIG_ETB_NUM 1
131 #define CONFIG_USI_NUM 2
133 /* ================================================================================ */
134 /* ================ Peripheral memory map ================ */
135 /* ================================================================================ */
136 /* -------------------------- CPU FPGA memory map ------------------------------- */
137 #define CSKY_EFLASH_BASE (0x10000000UL)
138 #define CSKY_QSPIMEM_BASE (0x18000000UL)
139 #define CSKY_SRAM_BASE (0x20000000UL)
140 #define CSKY_PMU_BASE (0x40000000UL)
141 #define CSKY_DMAC0_BASE (0x40001000UL)
142 #define CSKY_OTP_BASE (0x40006000UL)
143 #define CSKY_SASC_BASE (0x40009000UL)
144 #define CSKY_SPU_BASE (0x40020000UL)
145 #define CSKY_QSPIC1_BASE (0x40030000UL)
146 #define CSKY_EFLASH_CONTROL_BASE (0x40005000UL)
147 #define CSKY_SASC_BASE (0x40009000UL)
150 #define CSKY_AES_BASE (0x4000D000UL)
151 #define CSKY_SHA_BASE (0x4000E000UL)
152 #define CSKY_RSA_BASE (0x4000F000UL)
153 #define CSKY_CRC_BASE (0x40010000UL)
154 #define CSKY_TRNG_BASE (0x40011000UL)
156 #define CSKY_TIM0_BASE (0x50000000UL)
157 #define CSKY_TIM1_BASE (0x50000400UL)
158 #define CSKY_TIM2_BASE (0x50000800UL)
159 #define CSKY_TIM3_BASE (0x50000C00UL)
160 #define CSKY_RTC0_BASE (0x50004000UL)
161 #define CSKY_WDT_BASE (0x50008000UL)
162 #define CSKY_SPI0_BASE (0x5000C000UL)
163 #define CSKY_UART0_BASE (0x50010000UL)
164 #define CSKY_UART1_BASE (0x50010400UL)
165 #define CSKY_I2C0_BASE (0x50014000UL)
166 #define CSKY_GPIO0_BASE (0x50018000UL)
167 #define CSKY_PWM_BASE (0x5001C000UL)
168 #define CSKY_ADC_BASE (0x50020000UL)
169 #define CSKY_USI0_BASE (0x50028000UL)
170 #define CSKY_QSPIC0_BASE (0x5002C000UL)
172 #define CSKY_TIM4_BASE (0x60000000UL)
173 #define CSKY_TIM5_BASE (0x60000400UL)
174 #define CSKY_TIM6_BASE (0x60000800UL)
175 #define CSKY_TIM7_BASE (0x60000C00UL)
176 #define CSKY_LPWDT_BASE (0x60008000UL)
177 #define CSKY_SPI1_BASE (0x6000C000UL)
178 #define CSKY_UART2_BASE (0x60010000UL)
179 #define CSKY_UART3_BASE (0x60010400UL)
180 #define CSKY_I2C1_BASE (0x60014000UL)
181 #define CSKY_GPIO1_BASE (0x60018000UL)
182 #define CSKY_TIPC_BASE (0x6001c000UL)
183 #define CSKY_ETB_BASE (0x60024000UL)
184 #define CSKY_USI1_BASE (0x60028000UL)
185 #define CSKY_DAC_BASE (0x6002C000UL)
186 #define CSKY_IOC_BASE (0x60030000UL)
188 #define SHA_CONTEXT_SIZE 224
190 /* ================================================================================ */
191 /* ================ Peripheral declaration ================ */
192 /* ================================================================================ */
193 #define CSKY_UART1 (( CSKY_UART_TypeDef *) CSKY_UART1_BASE)
194 #define CSKY_SHA (( CSKY_SHA_TypeDef *) CSKY_SHA_BASE)
196 #ifdef CONFIG_HAVE_VIC
197 #define ATTRIBUTE_ISR __attribute__((isr))
199 #define ATTRIBUTE_ISR