2 FreeRTOS V8.2.0 - Copyright (C) 2015 Real Time Engineers Ltd.
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5 VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
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7 This file is part of the FreeRTOS distribution.
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9 FreeRTOS is free software; you can redistribute it and/or modify it under
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10 the terms of the GNU General Public License (version 2) as published by the
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11 Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.
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13 ***************************************************************************
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14 >>! NOTE: The modification to the GPL is included to allow you to !<<
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15 >>! distribute a combined work that includes FreeRTOS without being !<<
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16 >>! obliged to provide the source code for proprietary components !<<
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17 >>! outside of the FreeRTOS kernel. !<<
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18 ***************************************************************************
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20 FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
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21 WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
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22 FOR A PARTICULAR PURPOSE. Full license text is available on the following
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23 link: http://www.freertos.org/a00114.html
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25 ***************************************************************************
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27 * FreeRTOS provides completely free yet professionally developed, *
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28 * robust, strictly quality controlled, supported, and cross *
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29 * platform software that is more than just the market leader, it *
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30 * is the industry's de facto standard. *
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32 * Help yourself get started quickly while simultaneously helping *
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33 * to support the FreeRTOS project by purchasing a FreeRTOS *
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34 * tutorial book, reference manual, or both: *
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35 * http://www.FreeRTOS.org/Documentation *
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37 ***************************************************************************
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39 http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading
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40 the FAQ page "My application does not run, what could be wrong?". Have you
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41 defined configASSERT()?
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43 http://www.FreeRTOS.org/support - In return for receiving this top quality
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44 embedded software for free we request you assist our global community by
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45 participating in the support forum.
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47 http://www.FreeRTOS.org/training - Investing in training allows your team to
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48 be as productive as possible as early as possible. Now you can receive
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49 FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers
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50 Ltd, and the world's leading authority on the world's leading RTOS.
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52 http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
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53 including FreeRTOS+Trace - an indispensable productivity tool, a DOS
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54 compatible FAT file system, and our tiny thread aware UDP/IP stack.
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56 http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.
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57 Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.
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59 http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High
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60 Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS
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61 licenses offer ticketed support, indemnification and commercial middleware.
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63 http://www.SafeRTOS.com - High Integrity Systems also provide a safety
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64 engineered and independently SIL3 certified version for use in safety and
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65 mission critical applications that require provable dependability.
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73 + Modified char* types to compile without warning when using GCC V4.0.1.
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74 + Corrected the address to which the MAC address is written. Thanks to
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75 Bill Knight for this correction.
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79 + Changed the default MAC address to something more realistic.
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83 /* Standard includes. */
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87 /* Scheduler include files. */
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88 #include "FreeRTOS.h"
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94 /* Application includes. */
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96 #include "html_pages.h"
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98 /*-----------------------------------------------------------*/
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100 /* Hardwired i2c address of the WIZNet device. */
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101 #define tcpDEVICE_ADDRESS ( ( unsigned char ) 0x00 )
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103 /* Constants used to configure the Tx and Rx buffer sizes within the WIZnet
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105 #define tcp8K_RX ( ( unsigned char ) 0x03 )
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106 #define tcp8K_TX ( ( unsigned char ) 0x03 )
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108 /* Constants used to generate the WIZnet internal buffer addresses. */
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109 #define tcpSINGLE_SOCKET_ADDR_MASK ( ( unsigned long ) 0x1fff )
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110 #define tcpSINGLE_SOCKET_ADDR_OFFSET ( ( unsigned long ) 0x4000 )
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112 /* Bit definitions of the commands that can be sent to the command register. */
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113 #define tcpRESET_CMD ( ( unsigned char ) 0x80 )
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114 #define tcpSYS_INIT_CMD ( ( unsigned char ) 0x01 )
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115 #define tcpSOCK_STREAM ( ( unsigned char ) 0x01 )
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116 #define tcpSOCK_INIT ( ( unsigned char ) 0x02 )
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117 #define tcpLISTEN_CMD ( ( unsigned char ) 0x08 )
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118 #define tcpRECEIVE_CMD ( ( unsigned char ) 0x40 )
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119 #define tcpDISCONNECT_CMD ( ( unsigned char ) 0x10 )
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120 #define tcpSEND_CMD ( ( unsigned char ) 0x20 )
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122 /* Constants required to handle the interrupts. */
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123 #define tcpCLEAR_EINT0 ( 1 )
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124 #define i2cCLEAR_ALL_INTERRUPTS ( ( unsigned char ) 0xff )
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125 #define i2cCHANNEL_0_ISR_ENABLE ( ( unsigned char ) 0x01 )
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126 #define i2cCHANNEL_0_ISR_DISABLE ( ( unsigned char ) 0x00 )
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127 #define tcpWAKE_ON_EINT0 ( 1 )
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128 #define tcpENABLE_EINT0_FUNCTION ( ( unsigned long ) 0x01 )
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129 #define tcpEINT0_VIC_CHANNEL_BIT ( ( unsigned long ) 0x4000 )
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130 #define tcpEINT0_VIC_CHANNEL ( ( unsigned long ) 14 )
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131 #define tcpEINT0_VIC_ENABLE ( ( unsigned long ) 0x0020 )
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133 /* Various delays used in the driver. */
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134 #define tcpRESET_DELAY ( ( TickType_t ) 16 / portTICK_PERIOD_MS )
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135 #define tcpINIT_DELAY ( ( TickType_t ) 500 / portTICK_PERIOD_MS )
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136 #define tcpLONG_DELAY ( ( TickType_t ) 500 / portTICK_PERIOD_MS )
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137 #define tcpSHORT_DELAY ( ( TickType_t ) 5 / portTICK_PERIOD_MS )
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138 #define tcpCONNECTION_WAIT_DELAY ( ( TickType_t ) 100 / portTICK_PERIOD_MS )
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139 #define tcpNO_DELAY ( ( TickType_t ) 0 )
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141 /* Length of the data to read for various register reads. */
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142 #define tcpSTATUS_READ_LEN ( ( unsigned long ) 1 )
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143 #define tcpSHADOW_READ_LEN ( ( unsigned long ) 1 )
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145 /* Register addresses within the WIZnet device. */
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146 #define tcpCOMMAND_REG ( ( unsigned short ) 0x0000 )
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147 #define tcpGATEWAY_ADDR_REG ( ( unsigned short ) 0x0080 )
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148 #define tcpSUBNET_MASK_REG ( ( unsigned short ) 0x0084 )
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149 #define tcpSOURCE_HA_REG ( ( unsigned short ) 0x0088 )
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150 #define tpcSOURCE_IP_REG ( ( unsigned short ) 0x008E )
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151 #define tpcSOCKET_OPT_REG ( ( unsigned short ) 0x00A1 )
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152 #define tcpSOURCE_PORT_REG ( ( unsigned short ) 0x00AE )
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153 #define tcpTX_WRITE_POINTER_REG ( ( unsigned short ) 0x0040 )
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154 #define tcpTX_READ_POINTER_REG ( ( unsigned short ) 0x0044 )
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155 #define tcpTX_ACK_POINTER_REG ( ( unsigned short ) 0x0018 )
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156 #define tcpTX_MEM_SIZE_REG ( ( unsigned short ) 0x0096 )
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157 #define tcpRX_MEM_SIZE_REG ( ( unsigned short ) 0x0095 )
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158 #define tcpINTERRUPT_STATUS_REG ( ( unsigned short ) 0x0004 )
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159 #define tcpTX_WRITE_SHADOW_REG ( ( unsigned short ) 0x01F0 )
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160 #define tcpTX_ACK_SHADOW_REG ( ( unsigned short ) 0x01E2 )
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161 #define tcpISR_MASK_REG ( ( unsigned short ) 0x0009 )
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162 #define tcpINTERRUPT_REG ( ( unsigned short ) 0x0008 )
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163 #define tcpSOCKET_STATE_REG ( ( unsigned short ) 0x00a0 )
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165 /* Constants required for hardware setup. */
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166 #define tcpRESET_ACTIVE_LOW ( ( unsigned long ) 0x20 )
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167 #define tcpRESET_ACTIVE_HIGH ( ( unsigned long ) 0x10 )
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169 /* Constants defining the source of the WIZnet ISR. */
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170 #define tcpISR_SYS_INIT ( ( unsigned char ) 0x01 )
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171 #define tcpISR_SOCKET_INIT ( ( unsigned char ) 0x02 )
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172 #define tcpISR_ESTABLISHED ( ( unsigned char ) 0x04 )
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173 #define tcpISR_CLOSED ( ( unsigned char ) 0x08 )
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174 #define tcpISR_TIMEOUT ( ( unsigned char ) 0x10 )
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175 #define tcpISR_TX_COMPLETE ( ( unsigned char ) 0x20 )
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176 #define tcpISR_RX_COMPLETE ( ( unsigned char ) 0x40 )
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178 /* Constants defining the socket status bits. */
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179 #define tcpSTATUS_ESTABLISHED ( ( unsigned char ) 0x06 )
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180 #define tcpSTATUS_LISTEN ( ( unsigned char ) 0x02 )
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182 /* Misc constants. */
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183 #define tcpNO_STATUS_BITS ( ( unsigned char ) 0x00 )
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184 #define i2cNO_ADDR_REQUIRED ( ( unsigned short ) 0x0000 )
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185 #define i2cNO_DATA_REQUIRED ( 0x0000 )
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186 #define tcpISR_QUEUE_LENGTH ( ( unsigned portBASE_TYPE ) 10 )
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187 #define tcpISR_QUEUE_ITEM_SIZE ( ( unsigned portBASE_TYPE ) 0 )
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188 #define tcpBUFFER_LEN ( 4 * 1024 )
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189 #define tcpMAX_REGISTER_LEN ( 4 )
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190 #define tcpMAX_ATTEMPTS_TO_CHECK_BUFFER ( 6 )
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191 #define tcpMAX_NON_LISTEN_STAUS_READS ( 5 )
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193 /* Message definitions. The IP address, MAC address, gateway address, etc.
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195 const unsigned char const ucDataGAR[] = { 172, 25, 218, 3 }; /* Gateway address. */
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196 const unsigned char const ucDataMSR[] = { 255, 255, 255, 0 }; /* Subnet mask. */
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197 const unsigned char const ucDataSIPR[] = { 172, 25, 218, 201 };/* IP address. */
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198 const unsigned char const ucDataSHAR[] = { 00, 23, 30, 41, 15, 26 }; /* MAC address - DO NOT USE THIS ON A PUBLIC NETWORK! */
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200 /* Other fixed messages. */
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201 const unsigned char const ucDataReset[] = { tcpRESET_CMD };
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202 const unsigned char const ucDataInit[] = { tcpSYS_INIT_CMD };
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203 const unsigned char const ucDataProtocol[] = { tcpSOCK_STREAM };
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204 const unsigned char const ucDataPort[] = { 0xBA, 0xCC };
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205 const unsigned char const ucDataSockInit[] = { tcpSOCK_INIT };
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206 const unsigned char const ucDataTxWritePointer[] = { 0x11, 0x22, 0x00, 0x00 };
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207 const unsigned char const ucDataTxAckPointer[] = { 0x11, 0x22, 0x00, 0x00 };
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208 const unsigned char const ucDataTxReadPointer[] = { 0x11, 0x22, 0x00, 0x00 };
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209 const unsigned char const ucDataListen[] = { tcpLISTEN_CMD };
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210 const unsigned char const ucDataReceiveCmd[] = { tcpRECEIVE_CMD };
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211 const unsigned char const ucDataSetTxBufSize[] = { tcp8K_TX };
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212 const unsigned char const ucDataSetRxBufSize[] = { tcp8K_RX };
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213 const unsigned char const ucDataSend[] = { tcpSEND_CMD };
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214 const unsigned char const ucDataDisconnect[] = { tcpDISCONNECT_CMD };
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215 const unsigned char const ucDataEnableISR[] = { i2cCHANNEL_0_ISR_ENABLE };
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216 const unsigned char const ucDataDisableISR[] = { i2cCHANNEL_0_ISR_DISABLE };
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217 const unsigned char const ucDataClearInterrupt[] = { i2cCLEAR_ALL_INTERRUPTS };
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219 static SemaphoreHandle_t xMessageComplete = NULL;
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220 QueueHandle_t xTCPISRQueue = NULL;
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222 /* Dynamically generate and send an html page. */
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223 static void prvSendSamplePage( void );
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225 /* Read a register from the WIZnet device via the i2c interface. */
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226 static void prvReadRegister( unsigned char *pucDestination, unsigned short usAddress, unsigned long ulLength );
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228 /* Send the entire Tx buffer (the Tx buffer within the WIZnet device). */
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229 static void prvFlushBuffer( unsigned long ulTxAddress );
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231 /* Write a string to the WIZnet Tx buffer. */
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232 static void prvWriteString( const char * const pucTxBuffer, long lTxLen, unsigned long *pulTxAddress );
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234 /* Convert a number to a string. */
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235 void ultoa( unsigned long ulVal, char *pcBuffer, long lIgnore );
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237 /*-----------------------------------------------------------*/
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239 void ultoa( unsigned long ulVal, char *pcBuffer, long lIgnore )
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241 unsigned long lNibble;
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244 /* Simple routine to convert an unsigned long value into a string in hex
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247 /* For each nibble in the number we are converting. */
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248 for( lIndex = 0; lIndex < ( sizeof( ulVal ) * 2 ); lIndex++ )
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250 /* Take the top four bits of the number. */
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251 lNibble = ( ulVal >> 28 );
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253 /* We are converting it to a hex string, so is the number in the range
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257 pcBuffer[ lIndex ] = '0' + lNibble;
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262 pcBuffer[ lIndex ] = 'A' + lNibble;
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265 /* Shift off the top nibble so we use the next nibble next time around. */
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269 /* Mark the end of the string with a null terminator. */
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270 pcBuffer[ lIndex ] = 0x00;
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272 /*-----------------------------------------------------------*/
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274 static void prvReadRegister( unsigned char *pucDestination, unsigned short usAddress, unsigned long ulLength )
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276 unsigned char ucRxBuffer[ tcpMAX_REGISTER_LEN ];
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278 /* Read a register value from the WIZnet device. */
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280 /* First write out the address of the register we want to read. */
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281 i2cMessage( ucRxBuffer, i2cNO_DATA_REQUIRED, tcpDEVICE_ADDRESS, usAddress, i2cWRITE, NULL, portMAX_DELAY );
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283 /* Then read back from that address. */
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284 i2cMessage( ( unsigned char * ) pucDestination, ulLength, tcpDEVICE_ADDRESS, i2cNO_ADDR_REQUIRED, i2cREAD, xMessageComplete, portMAX_DELAY );
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286 /* I2C messages are queued so use the semaphore to wait for the read to
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287 complete - otherwise we will leave this function before the I2C
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288 transactions have completed. */
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289 xSemaphoreTake( xMessageComplete, tcpLONG_DELAY );
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291 /*-----------------------------------------------------------*/
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293 void vTCPHardReset( void )
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295 /* Physical reset of the WIZnet device by using the GPIO lines to hold the
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296 WIZnet reset lines active for a few milliseconds. */
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298 /* Make sure the interrupt from the WIZnet is disabled. */
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299 VICIntEnClear |= tcpEINT0_VIC_CHANNEL_BIT;
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301 /* If xMessageComplete is NULL then this is the first time that this
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302 function has been called and the queue and semaphore used in this file
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303 have not yet been created. */
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304 if( xMessageComplete == NULL )
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306 /* Create and obtain the semaphore used when we want to wait for an i2c
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307 message to be completed. */
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308 vSemaphoreCreateBinary( xMessageComplete );
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309 xSemaphoreTake( xMessageComplete, tcpNO_DELAY );
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311 /* Create the queue used to communicate between the WIZnet and TCP tasks. */
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312 xTCPISRQueue = xQueueCreate( tcpISR_QUEUE_LENGTH, tcpISR_QUEUE_ITEM_SIZE );
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315 /* Use the GPIO to reset the network hardware. */
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316 GPIO_IOCLR = tcpRESET_ACTIVE_LOW;
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317 GPIO_IOSET = tcpRESET_ACTIVE_HIGH;
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319 /* Delay with the network hardware in reset for a short while. */
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320 vTaskDelay( tcpRESET_DELAY );
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322 GPIO_IOCLR = tcpRESET_ACTIVE_HIGH;
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323 GPIO_IOSET = tcpRESET_ACTIVE_LOW;
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325 vTaskDelay( tcpINIT_DELAY );
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327 /* Setup the EINT0 to interrupt on required events from the WIZnet device.
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328 First enable the EINT0 function of the pin. */
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329 PCB_PINSEL1 |= tcpENABLE_EINT0_FUNCTION;
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331 /* We want the TCP comms to wake us from power save. */
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332 SCB_EXTWAKE = tcpWAKE_ON_EINT0;
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334 /* Install the ISR into the VIC - but don't enable it yet! */
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335 portENTER_CRITICAL();
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337 extern void ( vEINT0_ISR_Wrapper )( void );
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339 VICIntSelect &= ~( tcpEINT0_VIC_CHANNEL_BIT );
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340 VICVectAddr3 = ( long ) vEINT0_ISR_Wrapper;
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342 VICVectCntl3 = tcpEINT0_VIC_CHANNEL | tcpEINT0_VIC_ENABLE;
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344 portEXIT_CRITICAL();
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346 /* Enable interrupts in the WIZnet itself. */
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347 i2cMessage( ucDataEnableISR, sizeof( ucDataEnableISR ), tcpDEVICE_ADDRESS, tcpISR_MASK_REG, i2cWRITE, NULL, portMAX_DELAY );
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349 vTaskDelay( tcpLONG_DELAY );
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351 /*-----------------------------------------------------------*/
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353 long lTCPSoftReset( void )
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355 unsigned char ucStatus;
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356 extern volatile long lTransactionCompleted;
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358 /* Send a message to the WIZnet device to tell it set all it's registers
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359 back to their default states. Then setup the WIZnet device as required. */
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361 /* Reset the internal WIZnet registers. */
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362 i2cMessage( ucDataReset, sizeof( ucDataReset ), tcpDEVICE_ADDRESS, tcpCOMMAND_REG, i2cWRITE, NULL, portMAX_DELAY );
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364 /* Now we can configure the protocol. Here the MAC address, gateway
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365 address, subnet mask and IP address are configured. */
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366 i2cMessage( ucDataSHAR, sizeof( ucDataSHAR ), tcpDEVICE_ADDRESS, tcpSOURCE_HA_REG, i2cWRITE, NULL, portMAX_DELAY );
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367 i2cMessage( ucDataGAR, sizeof( ucDataGAR ), tcpDEVICE_ADDRESS, tcpGATEWAY_ADDR_REG, i2cWRITE, NULL, portMAX_DELAY );
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368 i2cMessage( ucDataMSR, sizeof( ucDataMSR ), tcpDEVICE_ADDRESS, tcpSUBNET_MASK_REG, i2cWRITE, NULL, portMAX_DELAY );
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369 i2cMessage( ucDataSIPR, sizeof( ucDataSIPR ), tcpDEVICE_ADDRESS, tpcSOURCE_IP_REG, i2cWRITE, NULL, portMAX_DELAY );
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371 /* Next the memory buffers are configured to give all the WIZnet internal
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372 memory over to a single socket. This gives the socket the maximum internal
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373 Tx and Rx buffer space. */
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374 i2cMessage( ucDataSetTxBufSize, sizeof( ucDataSetTxBufSize ), tcpDEVICE_ADDRESS, tcpTX_MEM_SIZE_REG, i2cWRITE, NULL, portMAX_DELAY );
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375 i2cMessage( ucDataSetRxBufSize, sizeof( ucDataSetRxBufSize ), tcpDEVICE_ADDRESS, tcpRX_MEM_SIZE_REG, i2cWRITE, NULL, portMAX_DELAY );
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377 /* Send the sys init command so the above parameters take effect. */
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378 i2cMessage( ucDataInit, sizeof( ucDataInit ), tcpDEVICE_ADDRESS, tcpCOMMAND_REG, i2cWRITE, NULL, portMAX_DELAY );
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380 /* Seems to like a little wait here. */
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381 vTaskDelay( tcpINIT_DELAY );
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383 /* Read back the status to ensure the system initialised ok. */
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384 prvReadRegister( &ucStatus, tcpINTERRUPT_STATUS_REG, tcpSTATUS_READ_LEN );
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386 /* We should find that the sys init was successful. */
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387 if( ucStatus != tcpISR_SYS_INIT )
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389 return ( long ) pdFAIL;
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392 /* No i2c errors yet. */
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393 portENTER_CRITICAL();
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394 lTransactionCompleted = pdTRUE;
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395 portEXIT_CRITICAL();
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397 return ( long ) pdPASS;
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399 /*-----------------------------------------------------------*/
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401 long lTCPCreateSocket( void )
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403 unsigned char ucStatus;
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405 /* Create and configure a socket. */
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407 /* Setup and init the socket. Here the port number is set and the socket
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409 i2cMessage( ucDataProtocol, sizeof( ucDataProtocol),tcpDEVICE_ADDRESS, tpcSOCKET_OPT_REG, i2cWRITE, NULL, portMAX_DELAY );
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410 i2cMessage( ucDataPort, sizeof( ucDataPort), tcpDEVICE_ADDRESS, tcpSOURCE_PORT_REG, i2cWRITE, NULL, portMAX_DELAY );
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411 i2cMessage( ucDataSockInit, sizeof( ucDataSockInit),tcpDEVICE_ADDRESS, tcpCOMMAND_REG, i2cWRITE, xMessageComplete, portMAX_DELAY );
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413 /* Wait for the Init command to be sent. */
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414 if( !xSemaphoreTake( xMessageComplete, tcpLONG_DELAY ) )
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416 /* For some reason the message was not transmitted within our block
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418 return ( long ) pdFAIL;
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421 /* Allow the socket to initialise. */
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422 vTaskDelay( tcpINIT_DELAY );
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424 /* Read back the status to ensure the socket initialised ok. */
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425 prvReadRegister( &ucStatus, tcpINTERRUPT_STATUS_REG, tcpSTATUS_READ_LEN );
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427 /* We should find that the socket init was successful. */
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428 if( ucStatus != tcpISR_SOCKET_INIT )
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430 return ( long ) pdFAIL;
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434 /* Setup the Tx pointer registers to indicate that the Tx buffer is empty. */
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435 i2cMessage( ucDataTxReadPointer, sizeof( ucDataTxReadPointer ), tcpDEVICE_ADDRESS, tcpTX_READ_POINTER_REG, i2cWRITE, NULL, portMAX_DELAY );
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436 vTaskDelay( tcpSHORT_DELAY );
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437 i2cMessage( ucDataTxWritePointer, sizeof( ucDataTxWritePointer ), tcpDEVICE_ADDRESS, tcpTX_WRITE_POINTER_REG, i2cWRITE, NULL, portMAX_DELAY );
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438 vTaskDelay( tcpSHORT_DELAY );
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439 i2cMessage( ucDataTxAckPointer, sizeof( ucDataTxAckPointer ), tcpDEVICE_ADDRESS, tcpTX_ACK_POINTER_REG, i2cWRITE, NULL, portMAX_DELAY );
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440 vTaskDelay( tcpSHORT_DELAY );
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442 return ( long ) pdPASS;
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444 /*-----------------------------------------------------------*/
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446 void vTCPListen( void )
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448 unsigned char ucISR;
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450 /* Start a passive listen on the socket. */
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452 /* Enable interrupts in the WizNet device after ensuring none are
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453 currently pending. */
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454 while( SCB_EXTINT & tcpCLEAR_EINT0 )
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456 /* The WIZnet device is still asserting and interrupt so tell it to
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458 i2cMessage( ucDataClearInterrupt, sizeof( ucDataClearInterrupt ), tcpDEVICE_ADDRESS, tcpINTERRUPT_REG, i2cWRITE, xMessageComplete, portMAX_DELAY );
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459 xSemaphoreTake( xMessageComplete, tcpLONG_DELAY );
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462 SCB_EXTINT = tcpCLEAR_EINT0;
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465 while( xQueueReceive( xTCPISRQueue, &ucISR, tcpNO_DELAY ) )
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467 /* Just clearing the queue used by the ISR routine to tell this task
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468 that the WIZnet device needs attention. */
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471 /* Now all the pending interrupts have been cleared we can enable the
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472 processor interrupts. */
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473 VICIntEnable |= tcpEINT0_VIC_CHANNEL_BIT;
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475 /* Then start listening for incoming connections. */
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476 i2cMessage( ucDataListen, sizeof( ucDataListen ), tcpDEVICE_ADDRESS, tcpCOMMAND_REG, i2cWRITE, NULL, portMAX_DELAY );
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478 /*-----------------------------------------------------------*/
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480 long lProcessConnection( void )
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482 unsigned char ucISR, ucState, ucLastState = 2, ucShadow;
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483 extern volatile long lTransactionCompleted;
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484 long lSameStateCount = 0, lDataSent = pdFALSE;
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485 unsigned long ulWritePointer, ulAckPointer;
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487 /* No I2C errors can yet have occurred. */
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488 portENTER_CRITICAL();
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489 lTransactionCompleted = pdTRUE;
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490 portEXIT_CRITICAL();
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492 /* Keep looping - processing interrupts, until we have completed a
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493 transaction. This uses the WIZnet in it's simplest form. The socket
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494 accepts a connection - we process the connection - then close the socket.
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495 We then go back to reinitialise everything and start again. */
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496 while( lTransactionCompleted == pdTRUE )
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498 /* Wait for a message on the queue from the WIZnet ISR. When the
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499 WIZnet device asserts an interrupt the ISR simply posts a message
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500 onto this queue to wake this task. */
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501 if( xQueueReceive( xTCPISRQueue, &ucISR, tcpCONNECTION_WAIT_DELAY ) )
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503 /* The ISR posted a message on this queue to tell us that the
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504 WIZnet device asserted an interrupt. The ISR cannot process
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505 an I2C message so cannot tell us what caused the interrupt so
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506 we have to query the device here. This task is the highest
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507 priority in the system so will run immediately following the ISR. */
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508 prvReadRegister( &ucISR, tcpINTERRUPT_STATUS_REG, tcpSTATUS_READ_LEN );
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510 /* Once we have read what caused the ISR we can clear the interrupt
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512 i2cMessage( ucDataClearInterrupt, sizeof( ucDataClearInterrupt ), tcpDEVICE_ADDRESS, tcpINTERRUPT_REG, i2cWRITE, NULL, portMAX_DELAY );
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514 /* Now we can clear the processor interrupt and re-enable ready for
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516 SCB_EXTINT = tcpCLEAR_EINT0;
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517 VICIntEnable |= tcpEINT0_VIC_CHANNEL_BIT;
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519 /* Process the interrupt ... */
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521 if( ucISR & tcpISR_ESTABLISHED )
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523 /* A connection has been established - respond by sending
\r
524 a receive command. */
\r
525 i2cMessage( ucDataReceiveCmd, sizeof( ucDataReceiveCmd ), tcpDEVICE_ADDRESS, tcpCOMMAND_REG, i2cWRITE, NULL, portMAX_DELAY );
\r
528 if( ucISR & tcpISR_RX_COMPLETE )
\r
530 /* We message has been received. This will be an HTTP get
\r
531 command. We only have one page to send so just send it without
\r
532 regard to what the actual requested page was. */
\r
533 prvSendSamplePage();
\r
536 if( ucISR & tcpISR_TX_COMPLETE )
\r
538 /* We have a TX complete interrupt - which oddly does not
\r
539 indicate that the message being sent is complete so we cannot
\r
540 yet close the socket. Instead we read the position of the Tx
\r
541 pointer within the WIZnet device so we know how much data it
\r
542 has to send. Later we will read the ack pointer and compare
\r
543 this to the Tx pointer to ascertain whether the transmission
\r
546 /* First read the shadow register. */
\r
547 prvReadRegister( &ucShadow, tcpTX_WRITE_SHADOW_REG, tcpSHADOW_READ_LEN );
\r
549 /* Now a short delay is required. */
\r
550 vTaskDelay( tcpSHORT_DELAY );
\r
552 /* Then we can read the real register. */
\r
553 prvReadRegister( ( unsigned char * ) &ulWritePointer, tcpTX_WRITE_POINTER_REG, sizeof( ulWritePointer ) );
\r
555 /* We cannot do anything more here but need to remember that
\r
556 this interrupt has occurred. */
\r
557 lDataSent = pdTRUE;
\r
560 if( ucISR & tcpISR_CLOSED )
\r
562 /* The socket has been closed so we can leave this function. */
\r
563 lTransactionCompleted = pdFALSE;
\r
568 /* We have not received an interrupt from the WIZnet device for a
\r
569 while. Read the socket status and check that everything is as
\r
571 prvReadRegister( &ucState, tcpSOCKET_STATE_REG, tcpSTATUS_READ_LEN );
\r
573 if( ( ucState == tcpSTATUS_ESTABLISHED ) && ( lDataSent > 0 ) )
\r
575 /* The socket is established and we have already received a Tx
\r
576 end interrupt. We must therefore be waiting for the Tx buffer
\r
577 inside the WIZnet device to be empty before we can close the
\r
580 Read the Ack pointer register to see if it has caught up with
\r
581 the Tx pointer register. First we have to read the shadow
\r
583 prvReadRegister( &ucShadow, tcpTX_ACK_SHADOW_REG, tcpSHADOW_READ_LEN );
\r
584 vTaskDelay( tcpSHORT_DELAY );
\r
585 prvReadRegister( ( unsigned char * ) &ulAckPointer, tcpTX_ACK_POINTER_REG, sizeof( ulWritePointer ) );
\r
587 if( ulAckPointer == ulWritePointer )
\r
589 /* The Ack and write pointer are now equal and we can
\r
590 safely close the socket. */
\r
591 i2cMessage( ucDataDisconnect, sizeof( ucDataDisconnect ), tcpDEVICE_ADDRESS, tcpCOMMAND_REG, i2cWRITE, NULL, portMAX_DELAY );
\r
595 /* Keep a count of how many times we encounter the Tx
\r
596 buffer still containing data. */
\r
598 if( lDataSent > tcpMAX_ATTEMPTS_TO_CHECK_BUFFER )
\r
600 /* Assume we cannot complete sending the data and
\r
601 therefore cannot safely close the socket. Start over. */
\r
603 lTransactionCompleted = pdFALSE;
\r
607 else if( ucState != tcpSTATUS_LISTEN )
\r
609 /* If we have not yet received a Tx end interrupt we would only
\r
610 ever expect to find the socket still listening for any
\r
611 sustained period. */
\r
612 if( ucState == ucLastState )
\r
615 if( lSameStateCount > tcpMAX_NON_LISTEN_STAUS_READS )
\r
617 /* We are persistently in an unexpected state. Assume
\r
618 we cannot safely close the socket and start over. */
\r
620 lTransactionCompleted = pdFALSE;
\r
626 /* We are in the listen state so are happy that everything
\r
628 lSameStateCount = 0;
\r
631 /* Remember what state we are in this time around so we can check
\r
632 for a persistence on an unexpected state. */
\r
633 ucLastState = ucState;
\r
637 /* We are going to reinitialise the WIZnet device so do not want our
\r
638 interrupts from the WIZnet to be processed. */
\r
639 VICIntEnClear |= tcpEINT0_VIC_CHANNEL_BIT;
\r
640 return lTransactionCompleted;
\r
642 /*-----------------------------------------------------------*/
\r
644 static void prvWriteString( const char * const pucTxBuffer, long lTxLen, unsigned long *pulTxAddress )
\r
646 unsigned long ulSendAddress;
\r
648 /* Send a string to the Tx buffer internal to the WIZnet device. */
\r
650 /* Calculate the address to which we are going to write in the buffer. */
\r
651 ulSendAddress = ( *pulTxAddress & tcpSINGLE_SOCKET_ADDR_MASK ) + tcpSINGLE_SOCKET_ADDR_OFFSET;
\r
653 /* Send the buffer to the calculated address. Use the semaphore so we
\r
654 can wait until the entire message has been transferred. */
\r
655 i2cMessage( ( unsigned char * ) pucTxBuffer, lTxLen, tcpDEVICE_ADDRESS, ( unsigned short ) ulSendAddress, i2cWRITE, xMessageComplete, portMAX_DELAY );
\r
657 /* Wait until the semaphore indicates that the message has been transferred. */
\r
658 if( !xSemaphoreTake( xMessageComplete, tcpLONG_DELAY ) )
\r
663 /* Return the new address of the end of the buffer (within the WIZnet
\r
665 *pulTxAddress += ( unsigned long ) lTxLen;
\r
667 /*-----------------------------------------------------------*/
\r
669 static void prvFlushBuffer( unsigned long ulTxAddress )
\r
671 unsigned char ucTxBuffer[ tcpMAX_REGISTER_LEN ];
\r
673 /* We have written some data to the Tx buffer internal to the WIZnet
\r
674 device. Now we update the Tx pointer inside the WIZnet then send a
\r
675 Send command - which causes the data up to the new Tx pointer to be
\r
678 /* Make sure endieness is correct for transmission. */
\r
679 ulTxAddress = htonl( ulTxAddress );
\r
681 /* Place the new Tx pointer in the string to be transmitted. */
\r
682 ucTxBuffer[ 0 ] = ( unsigned char ) ( ulTxAddress & 0xff );
\r
684 ucTxBuffer[ 1 ] = ( unsigned char ) ( ulTxAddress & 0xff );
\r
686 ucTxBuffer[ 2 ] = ( unsigned char ) ( ulTxAddress & 0xff );
\r
688 ucTxBuffer[ 3 ] = ( unsigned char ) ( ulTxAddress & 0xff );
\r
691 /* And send it to the WIZnet device. */
\r
692 i2cMessage( ucTxBuffer, sizeof( ulTxAddress ), tcpDEVICE_ADDRESS, tcpTX_WRITE_POINTER_REG, i2cWRITE, xMessageComplete, portMAX_DELAY );
\r
694 if( !xSemaphoreTake( xMessageComplete, tcpLONG_DELAY ) )
\r
699 vTaskDelay( tcpSHORT_DELAY );
\r
702 i2cMessage( ucDataSend, sizeof( ucDataSend ), tcpDEVICE_ADDRESS, tcpCOMMAND_REG, i2cWRITE, xMessageComplete, portMAX_DELAY );
\r
704 if( !xSemaphoreTake( xMessageComplete, tcpLONG_DELAY ) )
\r
709 /*-----------------------------------------------------------*/
\r
711 static void prvSendSamplePage( void )
\r
713 extern long lErrorInTask;
\r
714 unsigned long ulTxAddress;
\r
715 unsigned char ucShadow;
\r
717 static unsigned long ulRefreshCount = 0x00;
\r
718 static char cPageBuffer[ tcpBUFFER_LEN ];
\r
721 /* This function just generates a sample page of HTML which gets
\r
722 sent each time a client attaches to the socket. The page is created
\r
723 from two fixed strings (cSamplePageFirstPart and cSamplePageSecondPart)
\r
724 with a bit of dynamically generated data in the middle. */
\r
726 /* We need to know the address to which the html string should be sent
\r
727 in the WIZnet Tx buffer. First read the shadow register. */
\r
728 prvReadRegister( &ucShadow, tcpTX_WRITE_SHADOW_REG, tcpSHADOW_READ_LEN );
\r
730 /* Now a short delay is required. */
\r
731 vTaskDelay( tcpSHORT_DELAY );
\r
733 /* Now we can read the real pointer value. */
\r
734 prvReadRegister( ( unsigned char * ) &ulTxAddress, tcpTX_WRITE_POINTER_REG, sizeof( ulTxAddress ) );
\r
736 /* Make sure endieness is correct. */
\r
737 ulTxAddress = htonl( ulTxAddress );
\r
739 /* Send the start of the page. */
\r
740 prvWriteString( cSamplePageFirstPart, strlen( cSamplePageFirstPart ), &ulTxAddress );
\r
742 /* Generate a bit of dynamic data and place it in the buffer ready to be
\r
744 strcpy( cPageBuffer, "<BR>Number of ticks since boot = 0x" );
\r
745 lIndex = strlen( cPageBuffer );
\r
746 ultoa( xTaskGetTickCount(), &( cPageBuffer[ lIndex ] ), 0 );
\r
747 strcat( cPageBuffer, "<br>Number of tasks executing = ");
\r
748 lIndex = strlen( cPageBuffer );
\r
749 ultoa( ( unsigned long ) uxTaskGetNumberOfTasks(), &( cPageBuffer[ lIndex ] ), 0 );
\r
750 strcat( cPageBuffer, "<br>IO port 0 state (used by flash tasks) = 0x" );
\r
751 lIndex = strlen( cPageBuffer );
\r
752 ultoa( ( unsigned long ) GPIO0_IOPIN, &( cPageBuffer[ lIndex ] ), 0 );
\r
753 strcat( cPageBuffer, "<br>Refresh = 0x" );
\r
754 lIndex = strlen( cPageBuffer );
\r
755 ultoa( ( unsigned long ) ulRefreshCount, &( cPageBuffer[ lIndex ] ), 0 );
\r
759 strcat( cPageBuffer, "<p>An error has occurred in at least one task." );
\r
763 strcat( cPageBuffer, "<p>All tasks executing without error." );
\r
768 /* Send the dynamically generated string. */
\r
769 prvWriteString( cPageBuffer, strlen( cPageBuffer ), &ulTxAddress );
\r
771 /* Finish the page. */
\r
772 prvWriteString( cSamplePageSecondPart, strlen( cSamplePageSecondPart ), &ulTxAddress );
\r
774 /* Tell the WIZnet to send the data we have just written to its Tx buffer. */
\r
775 prvFlushBuffer( ulTxAddress );
\r