2 * FreeRTOS Kernel V10.1.0
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3 * Copyright (C) 2018 Amazon.com, Inc. or its affiliates. All Rights Reserved.
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5 * Permission is hereby granted, free of charge, to any person obtaining a copy of
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6 * this software and associated documentation files (the "Software"), to deal in
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7 * the Software without restriction, including without limitation the rights to
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8 * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
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9 * the Software, and to permit persons to whom the Software is furnished to do so,
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10 * subject to the following conditions:
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12 * The above copyright notice and this permission notice shall be included in all
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13 * copies or substantial portions of the Software.
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15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
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17 * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
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18 * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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19 * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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20 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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22 * http://www.FreeRTOS.org
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23 * http://aws.amazon.com/freertos
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25 * 1 tab == 4 spaces!
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31 + Modified char* types to compile without warning when using GCC V4.0.1.
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32 + Corrected the address to which the MAC address is written. Thanks to
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33 Bill Knight for this correction.
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37 + Changed the default MAC address to something more realistic.
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41 /* Standard includes. */
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45 /* Scheduler include files. */
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46 #include "FreeRTOS.h"
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52 /* Application includes. */
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54 #include "html_pages.h"
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56 /*-----------------------------------------------------------*/
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58 /* Hardwired i2c address of the WIZNet device. */
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59 #define tcpDEVICE_ADDRESS ( ( unsigned char ) 0x00 )
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61 /* Constants used to configure the Tx and Rx buffer sizes within the WIZnet
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63 #define tcp8K_RX ( ( unsigned char ) 0x03 )
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64 #define tcp8K_TX ( ( unsigned char ) 0x03 )
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66 /* Constants used to generate the WIZnet internal buffer addresses. */
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67 #define tcpSINGLE_SOCKET_ADDR_MASK ( ( unsigned long ) 0x1fff )
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68 #define tcpSINGLE_SOCKET_ADDR_OFFSET ( ( unsigned long ) 0x4000 )
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70 /* Bit definitions of the commands that can be sent to the command register. */
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71 #define tcpRESET_CMD ( ( unsigned char ) 0x80 )
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72 #define tcpSYS_INIT_CMD ( ( unsigned char ) 0x01 )
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73 #define tcpSOCK_STREAM ( ( unsigned char ) 0x01 )
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74 #define tcpSOCK_INIT ( ( unsigned char ) 0x02 )
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75 #define tcpLISTEN_CMD ( ( unsigned char ) 0x08 )
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76 #define tcpRECEIVE_CMD ( ( unsigned char ) 0x40 )
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77 #define tcpDISCONNECT_CMD ( ( unsigned char ) 0x10 )
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78 #define tcpSEND_CMD ( ( unsigned char ) 0x20 )
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80 /* Constants required to handle the interrupts. */
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81 #define tcpCLEAR_EINT0 ( 1 )
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82 #define i2cCLEAR_ALL_INTERRUPTS ( ( unsigned char ) 0xff )
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83 #define i2cCHANNEL_0_ISR_ENABLE ( ( unsigned char ) 0x01 )
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84 #define i2cCHANNEL_0_ISR_DISABLE ( ( unsigned char ) 0x00 )
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85 #define tcpWAKE_ON_EINT0 ( 1 )
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86 #define tcpENABLE_EINT0_FUNCTION ( ( unsigned long ) 0x01 )
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87 #define tcpEINT0_VIC_CHANNEL_BIT ( ( unsigned long ) 0x4000 )
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88 #define tcpEINT0_VIC_CHANNEL ( ( unsigned long ) 14 )
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89 #define tcpEINT0_VIC_ENABLE ( ( unsigned long ) 0x0020 )
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91 /* Various delays used in the driver. */
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92 #define tcpRESET_DELAY ( ( TickType_t ) 16 / portTICK_PERIOD_MS )
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93 #define tcpINIT_DELAY ( ( TickType_t ) 500 / portTICK_PERIOD_MS )
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94 #define tcpLONG_DELAY ( ( TickType_t ) 500 / portTICK_PERIOD_MS )
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95 #define tcpSHORT_DELAY ( ( TickType_t ) 5 / portTICK_PERIOD_MS )
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96 #define tcpCONNECTION_WAIT_DELAY ( ( TickType_t ) 100 / portTICK_PERIOD_MS )
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97 #define tcpNO_DELAY ( ( TickType_t ) 0 )
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99 /* Length of the data to read for various register reads. */
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100 #define tcpSTATUS_READ_LEN ( ( unsigned long ) 1 )
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101 #define tcpSHADOW_READ_LEN ( ( unsigned long ) 1 )
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103 /* Register addresses within the WIZnet device. */
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104 #define tcpCOMMAND_REG ( ( unsigned short ) 0x0000 )
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105 #define tcpGATEWAY_ADDR_REG ( ( unsigned short ) 0x0080 )
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106 #define tcpSUBNET_MASK_REG ( ( unsigned short ) 0x0084 )
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107 #define tcpSOURCE_HA_REG ( ( unsigned short ) 0x0088 )
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108 #define tpcSOURCE_IP_REG ( ( unsigned short ) 0x008E )
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109 #define tpcSOCKET_OPT_REG ( ( unsigned short ) 0x00A1 )
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110 #define tcpSOURCE_PORT_REG ( ( unsigned short ) 0x00AE )
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111 #define tcpTX_WRITE_POINTER_REG ( ( unsigned short ) 0x0040 )
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112 #define tcpTX_READ_POINTER_REG ( ( unsigned short ) 0x0044 )
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113 #define tcpTX_ACK_POINTER_REG ( ( unsigned short ) 0x0018 )
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114 #define tcpTX_MEM_SIZE_REG ( ( unsigned short ) 0x0096 )
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115 #define tcpRX_MEM_SIZE_REG ( ( unsigned short ) 0x0095 )
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116 #define tcpINTERRUPT_STATUS_REG ( ( unsigned short ) 0x0004 )
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117 #define tcpTX_WRITE_SHADOW_REG ( ( unsigned short ) 0x01F0 )
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118 #define tcpTX_ACK_SHADOW_REG ( ( unsigned short ) 0x01E2 )
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119 #define tcpISR_MASK_REG ( ( unsigned short ) 0x0009 )
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120 #define tcpINTERRUPT_REG ( ( unsigned short ) 0x0008 )
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121 #define tcpSOCKET_STATE_REG ( ( unsigned short ) 0x00a0 )
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123 /* Constants required for hardware setup. */
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124 #define tcpRESET_ACTIVE_LOW ( ( unsigned long ) 0x20 )
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125 #define tcpRESET_ACTIVE_HIGH ( ( unsigned long ) 0x10 )
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127 /* Constants defining the source of the WIZnet ISR. */
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128 #define tcpISR_SYS_INIT ( ( unsigned char ) 0x01 )
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129 #define tcpISR_SOCKET_INIT ( ( unsigned char ) 0x02 )
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130 #define tcpISR_ESTABLISHED ( ( unsigned char ) 0x04 )
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131 #define tcpISR_CLOSED ( ( unsigned char ) 0x08 )
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132 #define tcpISR_TIMEOUT ( ( unsigned char ) 0x10 )
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133 #define tcpISR_TX_COMPLETE ( ( unsigned char ) 0x20 )
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134 #define tcpISR_RX_COMPLETE ( ( unsigned char ) 0x40 )
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136 /* Constants defining the socket status bits. */
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137 #define tcpSTATUS_ESTABLISHED ( ( unsigned char ) 0x06 )
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138 #define tcpSTATUS_LISTEN ( ( unsigned char ) 0x02 )
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140 /* Misc constants. */
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141 #define tcpNO_STATUS_BITS ( ( unsigned char ) 0x00 )
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142 #define i2cNO_ADDR_REQUIRED ( ( unsigned short ) 0x0000 )
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143 #define i2cNO_DATA_REQUIRED ( 0x0000 )
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144 #define tcpISR_QUEUE_LENGTH ( ( unsigned portBASE_TYPE ) 10 )
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145 #define tcpISR_QUEUE_ITEM_SIZE ( ( unsigned portBASE_TYPE ) 0 )
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146 #define tcpBUFFER_LEN ( 4 * 1024 )
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147 #define tcpMAX_REGISTER_LEN ( 4 )
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148 #define tcpMAX_ATTEMPTS_TO_CHECK_BUFFER ( 6 )
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149 #define tcpMAX_NON_LISTEN_STAUS_READS ( 5 )
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151 /* Message definitions. The IP address, MAC address, gateway address, etc.
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153 const unsigned char const ucDataGAR[] = { 172, 25, 218, 3 }; /* Gateway address. */
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154 const unsigned char const ucDataMSR[] = { 255, 255, 255, 0 }; /* Subnet mask. */
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155 const unsigned char const ucDataSIPR[] = { 172, 25, 218, 201 };/* IP address. */
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156 const unsigned char const ucDataSHAR[] = { 00, 23, 30, 41, 15, 26 }; /* MAC address - DO NOT USE THIS ON A PUBLIC NETWORK! */
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158 /* Other fixed messages. */
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159 const unsigned char const ucDataReset[] = { tcpRESET_CMD };
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160 const unsigned char const ucDataInit[] = { tcpSYS_INIT_CMD };
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161 const unsigned char const ucDataProtocol[] = { tcpSOCK_STREAM };
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162 const unsigned char const ucDataPort[] = { 0xBA, 0xCC };
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163 const unsigned char const ucDataSockInit[] = { tcpSOCK_INIT };
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164 const unsigned char const ucDataTxWritePointer[] = { 0x11, 0x22, 0x00, 0x00 };
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165 const unsigned char const ucDataTxAckPointer[] = { 0x11, 0x22, 0x00, 0x00 };
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166 const unsigned char const ucDataTxReadPointer[] = { 0x11, 0x22, 0x00, 0x00 };
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167 const unsigned char const ucDataListen[] = { tcpLISTEN_CMD };
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168 const unsigned char const ucDataReceiveCmd[] = { tcpRECEIVE_CMD };
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169 const unsigned char const ucDataSetTxBufSize[] = { tcp8K_TX };
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170 const unsigned char const ucDataSetRxBufSize[] = { tcp8K_RX };
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171 const unsigned char const ucDataSend[] = { tcpSEND_CMD };
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172 const unsigned char const ucDataDisconnect[] = { tcpDISCONNECT_CMD };
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173 const unsigned char const ucDataEnableISR[] = { i2cCHANNEL_0_ISR_ENABLE };
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174 const unsigned char const ucDataDisableISR[] = { i2cCHANNEL_0_ISR_DISABLE };
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175 const unsigned char const ucDataClearInterrupt[] = { i2cCLEAR_ALL_INTERRUPTS };
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177 static SemaphoreHandle_t xMessageComplete = NULL;
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178 QueueHandle_t xTCPISRQueue = NULL;
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180 /* Dynamically generate and send an html page. */
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181 static void prvSendSamplePage( void );
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183 /* Read a register from the WIZnet device via the i2c interface. */
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184 static void prvReadRegister( unsigned char *pucDestination, unsigned short usAddress, unsigned long ulLength );
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186 /* Send the entire Tx buffer (the Tx buffer within the WIZnet device). */
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187 static void prvFlushBuffer( unsigned long ulTxAddress );
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189 /* Write a string to the WIZnet Tx buffer. */
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190 static void prvWriteString( const char * const pucTxBuffer, long lTxLen, unsigned long *pulTxAddress );
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192 /* Convert a number to a string. */
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193 void ultoa( unsigned long ulVal, char *pcBuffer, long lIgnore );
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195 /*-----------------------------------------------------------*/
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197 void ultoa( unsigned long ulVal, char *pcBuffer, long lIgnore )
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199 unsigned long lNibble;
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202 /* Simple routine to convert an unsigned long value into a string in hex
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205 /* For each nibble in the number we are converting. */
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206 for( lIndex = 0; lIndex < ( sizeof( ulVal ) * 2 ); lIndex++ )
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208 /* Take the top four bits of the number. */
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209 lNibble = ( ulVal >> 28 );
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211 /* We are converting it to a hex string, so is the number in the range
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215 pcBuffer[ lIndex ] = '0' + lNibble;
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220 pcBuffer[ lIndex ] = 'A' + lNibble;
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223 /* Shift off the top nibble so we use the next nibble next time around. */
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227 /* Mark the end of the string with a null terminator. */
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228 pcBuffer[ lIndex ] = 0x00;
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230 /*-----------------------------------------------------------*/
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232 static void prvReadRegister( unsigned char *pucDestination, unsigned short usAddress, unsigned long ulLength )
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234 unsigned char ucRxBuffer[ tcpMAX_REGISTER_LEN ];
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236 /* Read a register value from the WIZnet device. */
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238 /* First write out the address of the register we want to read. */
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239 i2cMessage( ucRxBuffer, i2cNO_DATA_REQUIRED, tcpDEVICE_ADDRESS, usAddress, i2cWRITE, NULL, portMAX_DELAY );
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241 /* Then read back from that address. */
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242 i2cMessage( ( unsigned char * ) pucDestination, ulLength, tcpDEVICE_ADDRESS, i2cNO_ADDR_REQUIRED, i2cREAD, xMessageComplete, portMAX_DELAY );
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244 /* I2C messages are queued so use the semaphore to wait for the read to
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245 complete - otherwise we will leave this function before the I2C
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246 transactions have completed. */
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247 xSemaphoreTake( xMessageComplete, tcpLONG_DELAY );
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249 /*-----------------------------------------------------------*/
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251 void vTCPHardReset( void )
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253 /* Physical reset of the WIZnet device by using the GPIO lines to hold the
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254 WIZnet reset lines active for a few milliseconds. */
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256 /* Make sure the interrupt from the WIZnet is disabled. */
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257 VICIntEnClear |= tcpEINT0_VIC_CHANNEL_BIT;
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259 /* If xMessageComplete is NULL then this is the first time that this
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260 function has been called and the queue and semaphore used in this file
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261 have not yet been created. */
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262 if( xMessageComplete == NULL )
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264 /* Create and obtain the semaphore used when we want to wait for an i2c
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265 message to be completed. */
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266 vSemaphoreCreateBinary( xMessageComplete );
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267 xSemaphoreTake( xMessageComplete, tcpNO_DELAY );
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269 /* Create the queue used to communicate between the WIZnet and TCP tasks. */
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270 xTCPISRQueue = xQueueCreate( tcpISR_QUEUE_LENGTH, tcpISR_QUEUE_ITEM_SIZE );
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273 /* Use the GPIO to reset the network hardware. */
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274 GPIO_IOCLR = tcpRESET_ACTIVE_LOW;
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275 GPIO_IOSET = tcpRESET_ACTIVE_HIGH;
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277 /* Delay with the network hardware in reset for a short while. */
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278 vTaskDelay( tcpRESET_DELAY );
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280 GPIO_IOCLR = tcpRESET_ACTIVE_HIGH;
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281 GPIO_IOSET = tcpRESET_ACTIVE_LOW;
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283 vTaskDelay( tcpINIT_DELAY );
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285 /* Setup the EINT0 to interrupt on required events from the WIZnet device.
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286 First enable the EINT0 function of the pin. */
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287 PCB_PINSEL1 |= tcpENABLE_EINT0_FUNCTION;
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289 /* We want the TCP comms to wake us from power save. */
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290 SCB_EXTWAKE = tcpWAKE_ON_EINT0;
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292 /* Install the ISR into the VIC - but don't enable it yet! */
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293 portENTER_CRITICAL();
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295 extern void ( vEINT0_ISR_Wrapper )( void );
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297 VICIntSelect &= ~( tcpEINT0_VIC_CHANNEL_BIT );
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298 VICVectAddr3 = ( long ) vEINT0_ISR_Wrapper;
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300 VICVectCntl3 = tcpEINT0_VIC_CHANNEL | tcpEINT0_VIC_ENABLE;
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302 portEXIT_CRITICAL();
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304 /* Enable interrupts in the WIZnet itself. */
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305 i2cMessage( ucDataEnableISR, sizeof( ucDataEnableISR ), tcpDEVICE_ADDRESS, tcpISR_MASK_REG, i2cWRITE, NULL, portMAX_DELAY );
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307 vTaskDelay( tcpLONG_DELAY );
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309 /*-----------------------------------------------------------*/
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311 long lTCPSoftReset( void )
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313 unsigned char ucStatus;
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314 extern volatile long lTransactionCompleted;
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316 /* Send a message to the WIZnet device to tell it set all it's registers
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317 back to their default states. Then setup the WIZnet device as required. */
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319 /* Reset the internal WIZnet registers. */
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320 i2cMessage( ucDataReset, sizeof( ucDataReset ), tcpDEVICE_ADDRESS, tcpCOMMAND_REG, i2cWRITE, NULL, portMAX_DELAY );
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322 /* Now we can configure the protocol. Here the MAC address, gateway
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323 address, subnet mask and IP address are configured. */
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324 i2cMessage( ucDataSHAR, sizeof( ucDataSHAR ), tcpDEVICE_ADDRESS, tcpSOURCE_HA_REG, i2cWRITE, NULL, portMAX_DELAY );
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325 i2cMessage( ucDataGAR, sizeof( ucDataGAR ), tcpDEVICE_ADDRESS, tcpGATEWAY_ADDR_REG, i2cWRITE, NULL, portMAX_DELAY );
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326 i2cMessage( ucDataMSR, sizeof( ucDataMSR ), tcpDEVICE_ADDRESS, tcpSUBNET_MASK_REG, i2cWRITE, NULL, portMAX_DELAY );
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327 i2cMessage( ucDataSIPR, sizeof( ucDataSIPR ), tcpDEVICE_ADDRESS, tpcSOURCE_IP_REG, i2cWRITE, NULL, portMAX_DELAY );
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329 /* Next the memory buffers are configured to give all the WIZnet internal
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330 memory over to a single socket. This gives the socket the maximum internal
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331 Tx and Rx buffer space. */
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332 i2cMessage( ucDataSetTxBufSize, sizeof( ucDataSetTxBufSize ), tcpDEVICE_ADDRESS, tcpTX_MEM_SIZE_REG, i2cWRITE, NULL, portMAX_DELAY );
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333 i2cMessage( ucDataSetRxBufSize, sizeof( ucDataSetRxBufSize ), tcpDEVICE_ADDRESS, tcpRX_MEM_SIZE_REG, i2cWRITE, NULL, portMAX_DELAY );
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335 /* Send the sys init command so the above parameters take effect. */
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336 i2cMessage( ucDataInit, sizeof( ucDataInit ), tcpDEVICE_ADDRESS, tcpCOMMAND_REG, i2cWRITE, NULL, portMAX_DELAY );
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338 /* Seems to like a little wait here. */
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339 vTaskDelay( tcpINIT_DELAY );
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341 /* Read back the status to ensure the system initialised ok. */
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342 prvReadRegister( &ucStatus, tcpINTERRUPT_STATUS_REG, tcpSTATUS_READ_LEN );
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344 /* We should find that the sys init was successful. */
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345 if( ucStatus != tcpISR_SYS_INIT )
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347 return ( long ) pdFAIL;
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350 /* No i2c errors yet. */
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351 portENTER_CRITICAL();
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352 lTransactionCompleted = pdTRUE;
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353 portEXIT_CRITICAL();
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355 return ( long ) pdPASS;
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357 /*-----------------------------------------------------------*/
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359 long lTCPCreateSocket( void )
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361 unsigned char ucStatus;
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363 /* Create and configure a socket. */
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365 /* Setup and init the socket. Here the port number is set and the socket
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367 i2cMessage( ucDataProtocol, sizeof( ucDataProtocol),tcpDEVICE_ADDRESS, tpcSOCKET_OPT_REG, i2cWRITE, NULL, portMAX_DELAY );
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368 i2cMessage( ucDataPort, sizeof( ucDataPort), tcpDEVICE_ADDRESS, tcpSOURCE_PORT_REG, i2cWRITE, NULL, portMAX_DELAY );
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369 i2cMessage( ucDataSockInit, sizeof( ucDataSockInit),tcpDEVICE_ADDRESS, tcpCOMMAND_REG, i2cWRITE, xMessageComplete, portMAX_DELAY );
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371 /* Wait for the Init command to be sent. */
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372 if( !xSemaphoreTake( xMessageComplete, tcpLONG_DELAY ) )
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374 /* For some reason the message was not transmitted within our block
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376 return ( long ) pdFAIL;
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379 /* Allow the socket to initialise. */
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380 vTaskDelay( tcpINIT_DELAY );
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382 /* Read back the status to ensure the socket initialised ok. */
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383 prvReadRegister( &ucStatus, tcpINTERRUPT_STATUS_REG, tcpSTATUS_READ_LEN );
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385 /* We should find that the socket init was successful. */
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386 if( ucStatus != tcpISR_SOCKET_INIT )
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388 return ( long ) pdFAIL;
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392 /* Setup the Tx pointer registers to indicate that the Tx buffer is empty. */
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393 i2cMessage( ucDataTxReadPointer, sizeof( ucDataTxReadPointer ), tcpDEVICE_ADDRESS, tcpTX_READ_POINTER_REG, i2cWRITE, NULL, portMAX_DELAY );
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394 vTaskDelay( tcpSHORT_DELAY );
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395 i2cMessage( ucDataTxWritePointer, sizeof( ucDataTxWritePointer ), tcpDEVICE_ADDRESS, tcpTX_WRITE_POINTER_REG, i2cWRITE, NULL, portMAX_DELAY );
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396 vTaskDelay( tcpSHORT_DELAY );
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397 i2cMessage( ucDataTxAckPointer, sizeof( ucDataTxAckPointer ), tcpDEVICE_ADDRESS, tcpTX_ACK_POINTER_REG, i2cWRITE, NULL, portMAX_DELAY );
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398 vTaskDelay( tcpSHORT_DELAY );
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400 return ( long ) pdPASS;
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402 /*-----------------------------------------------------------*/
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404 void vTCPListen( void )
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406 unsigned char ucISR;
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408 /* Start a passive listen on the socket. */
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410 /* Enable interrupts in the WizNet device after ensuring none are
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411 currently pending. */
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412 while( SCB_EXTINT & tcpCLEAR_EINT0 )
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414 /* The WIZnet device is still asserting and interrupt so tell it to
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416 i2cMessage( ucDataClearInterrupt, sizeof( ucDataClearInterrupt ), tcpDEVICE_ADDRESS, tcpINTERRUPT_REG, i2cWRITE, xMessageComplete, portMAX_DELAY );
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417 xSemaphoreTake( xMessageComplete, tcpLONG_DELAY );
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420 SCB_EXTINT = tcpCLEAR_EINT0;
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423 while( xQueueReceive( xTCPISRQueue, &ucISR, tcpNO_DELAY ) )
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425 /* Just clearing the queue used by the ISR routine to tell this task
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426 that the WIZnet device needs attention. */
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429 /* Now all the pending interrupts have been cleared we can enable the
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430 processor interrupts. */
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431 VICIntEnable |= tcpEINT0_VIC_CHANNEL_BIT;
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433 /* Then start listening for incoming connections. */
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434 i2cMessage( ucDataListen, sizeof( ucDataListen ), tcpDEVICE_ADDRESS, tcpCOMMAND_REG, i2cWRITE, NULL, portMAX_DELAY );
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436 /*-----------------------------------------------------------*/
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438 long lProcessConnection( void )
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440 unsigned char ucISR, ucState, ucLastState = 2, ucShadow;
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441 extern volatile long lTransactionCompleted;
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442 long lSameStateCount = 0, lDataSent = pdFALSE;
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443 unsigned long ulWritePointer, ulAckPointer;
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445 /* No I2C errors can yet have occurred. */
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446 portENTER_CRITICAL();
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447 lTransactionCompleted = pdTRUE;
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448 portEXIT_CRITICAL();
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450 /* Keep looping - processing interrupts, until we have completed a
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451 transaction. This uses the WIZnet in it's simplest form. The socket
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452 accepts a connection - we process the connection - then close the socket.
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453 We then go back to reinitialise everything and start again. */
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454 while( lTransactionCompleted == pdTRUE )
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456 /* Wait for a message on the queue from the WIZnet ISR. When the
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457 WIZnet device asserts an interrupt the ISR simply posts a message
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458 onto this queue to wake this task. */
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459 if( xQueueReceive( xTCPISRQueue, &ucISR, tcpCONNECTION_WAIT_DELAY ) )
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461 /* The ISR posted a message on this queue to tell us that the
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462 WIZnet device asserted an interrupt. The ISR cannot process
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463 an I2C message so cannot tell us what caused the interrupt so
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464 we have to query the device here. This task is the highest
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465 priority in the system so will run immediately following the ISR. */
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466 prvReadRegister( &ucISR, tcpINTERRUPT_STATUS_REG, tcpSTATUS_READ_LEN );
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468 /* Once we have read what caused the ISR we can clear the interrupt
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470 i2cMessage( ucDataClearInterrupt, sizeof( ucDataClearInterrupt ), tcpDEVICE_ADDRESS, tcpINTERRUPT_REG, i2cWRITE, NULL, portMAX_DELAY );
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472 /* Now we can clear the processor interrupt and re-enable ready for
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474 SCB_EXTINT = tcpCLEAR_EINT0;
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475 VICIntEnable |= tcpEINT0_VIC_CHANNEL_BIT;
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477 /* Process the interrupt ... */
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479 if( ucISR & tcpISR_ESTABLISHED )
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481 /* A connection has been established - respond by sending
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482 a receive command. */
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483 i2cMessage( ucDataReceiveCmd, sizeof( ucDataReceiveCmd ), tcpDEVICE_ADDRESS, tcpCOMMAND_REG, i2cWRITE, NULL, portMAX_DELAY );
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486 if( ucISR & tcpISR_RX_COMPLETE )
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488 /* We message has been received. This will be an HTTP get
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489 command. We only have one page to send so just send it without
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490 regard to what the actual requested page was. */
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491 prvSendSamplePage();
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494 if( ucISR & tcpISR_TX_COMPLETE )
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496 /* We have a TX complete interrupt - which oddly does not
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497 indicate that the message being sent is complete so we cannot
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498 yet close the socket. Instead we read the position of the Tx
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499 pointer within the WIZnet device so we know how much data it
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500 has to send. Later we will read the ack pointer and compare
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501 this to the Tx pointer to ascertain whether the transmission
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504 /* First read the shadow register. */
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505 prvReadRegister( &ucShadow, tcpTX_WRITE_SHADOW_REG, tcpSHADOW_READ_LEN );
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507 /* Now a short delay is required. */
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508 vTaskDelay( tcpSHORT_DELAY );
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510 /* Then we can read the real register. */
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511 prvReadRegister( ( unsigned char * ) &ulWritePointer, tcpTX_WRITE_POINTER_REG, sizeof( ulWritePointer ) );
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513 /* We cannot do anything more here but need to remember that
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514 this interrupt has occurred. */
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515 lDataSent = pdTRUE;
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518 if( ucISR & tcpISR_CLOSED )
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520 /* The socket has been closed so we can leave this function. */
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521 lTransactionCompleted = pdFALSE;
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526 /* We have not received an interrupt from the WIZnet device for a
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527 while. Read the socket status and check that everything is as
\r
529 prvReadRegister( &ucState, tcpSOCKET_STATE_REG, tcpSTATUS_READ_LEN );
\r
531 if( ( ucState == tcpSTATUS_ESTABLISHED ) && ( lDataSent > 0 ) )
\r
533 /* The socket is established and we have already received a Tx
\r
534 end interrupt. We must therefore be waiting for the Tx buffer
\r
535 inside the WIZnet device to be empty before we can close the
\r
538 Read the Ack pointer register to see if it has caught up with
\r
539 the Tx pointer register. First we have to read the shadow
\r
541 prvReadRegister( &ucShadow, tcpTX_ACK_SHADOW_REG, tcpSHADOW_READ_LEN );
\r
542 vTaskDelay( tcpSHORT_DELAY );
\r
543 prvReadRegister( ( unsigned char * ) &ulAckPointer, tcpTX_ACK_POINTER_REG, sizeof( ulWritePointer ) );
\r
545 if( ulAckPointer == ulWritePointer )
\r
547 /* The Ack and write pointer are now equal and we can
\r
548 safely close the socket. */
\r
549 i2cMessage( ucDataDisconnect, sizeof( ucDataDisconnect ), tcpDEVICE_ADDRESS, tcpCOMMAND_REG, i2cWRITE, NULL, portMAX_DELAY );
\r
553 /* Keep a count of how many times we encounter the Tx
\r
554 buffer still containing data. */
\r
556 if( lDataSent > tcpMAX_ATTEMPTS_TO_CHECK_BUFFER )
\r
558 /* Assume we cannot complete sending the data and
\r
559 therefore cannot safely close the socket. Start over. */
\r
561 lTransactionCompleted = pdFALSE;
\r
565 else if( ucState != tcpSTATUS_LISTEN )
\r
567 /* If we have not yet received a Tx end interrupt we would only
\r
568 ever expect to find the socket still listening for any
\r
569 sustained period. */
\r
570 if( ucState == ucLastState )
\r
573 if( lSameStateCount > tcpMAX_NON_LISTEN_STAUS_READS )
\r
575 /* We are persistently in an unexpected state. Assume
\r
576 we cannot safely close the socket and start over. */
\r
578 lTransactionCompleted = pdFALSE;
\r
584 /* We are in the listen state so are happy that everything
\r
586 lSameStateCount = 0;
\r
589 /* Remember what state we are in this time around so we can check
\r
590 for a persistence on an unexpected state. */
\r
591 ucLastState = ucState;
\r
595 /* We are going to reinitialise the WIZnet device so do not want our
\r
596 interrupts from the WIZnet to be processed. */
\r
597 VICIntEnClear |= tcpEINT0_VIC_CHANNEL_BIT;
\r
598 return lTransactionCompleted;
\r
600 /*-----------------------------------------------------------*/
\r
602 static void prvWriteString( const char * const pucTxBuffer, long lTxLen, unsigned long *pulTxAddress )
\r
604 unsigned long ulSendAddress;
\r
606 /* Send a string to the Tx buffer internal to the WIZnet device. */
\r
608 /* Calculate the address to which we are going to write in the buffer. */
\r
609 ulSendAddress = ( *pulTxAddress & tcpSINGLE_SOCKET_ADDR_MASK ) + tcpSINGLE_SOCKET_ADDR_OFFSET;
\r
611 /* Send the buffer to the calculated address. Use the semaphore so we
\r
612 can wait until the entire message has been transferred. */
\r
613 i2cMessage( ( unsigned char * ) pucTxBuffer, lTxLen, tcpDEVICE_ADDRESS, ( unsigned short ) ulSendAddress, i2cWRITE, xMessageComplete, portMAX_DELAY );
\r
615 /* Wait until the semaphore indicates that the message has been transferred. */
\r
616 if( !xSemaphoreTake( xMessageComplete, tcpLONG_DELAY ) )
\r
621 /* Return the new address of the end of the buffer (within the WIZnet
\r
623 *pulTxAddress += ( unsigned long ) lTxLen;
\r
625 /*-----------------------------------------------------------*/
\r
627 static void prvFlushBuffer( unsigned long ulTxAddress )
\r
629 unsigned char ucTxBuffer[ tcpMAX_REGISTER_LEN ];
\r
631 /* We have written some data to the Tx buffer internal to the WIZnet
\r
632 device. Now we update the Tx pointer inside the WIZnet then send a
\r
633 Send command - which causes the data up to the new Tx pointer to be
\r
636 /* Make sure endieness is correct for transmission. */
\r
637 ulTxAddress = htonl( ulTxAddress );
\r
639 /* Place the new Tx pointer in the string to be transmitted. */
\r
640 ucTxBuffer[ 0 ] = ( unsigned char ) ( ulTxAddress & 0xff );
\r
642 ucTxBuffer[ 1 ] = ( unsigned char ) ( ulTxAddress & 0xff );
\r
644 ucTxBuffer[ 2 ] = ( unsigned char ) ( ulTxAddress & 0xff );
\r
646 ucTxBuffer[ 3 ] = ( unsigned char ) ( ulTxAddress & 0xff );
\r
649 /* And send it to the WIZnet device. */
\r
650 i2cMessage( ucTxBuffer, sizeof( ulTxAddress ), tcpDEVICE_ADDRESS, tcpTX_WRITE_POINTER_REG, i2cWRITE, xMessageComplete, portMAX_DELAY );
\r
652 if( !xSemaphoreTake( xMessageComplete, tcpLONG_DELAY ) )
\r
657 vTaskDelay( tcpSHORT_DELAY );
\r
660 i2cMessage( ucDataSend, sizeof( ucDataSend ), tcpDEVICE_ADDRESS, tcpCOMMAND_REG, i2cWRITE, xMessageComplete, portMAX_DELAY );
\r
662 if( !xSemaphoreTake( xMessageComplete, tcpLONG_DELAY ) )
\r
667 /*-----------------------------------------------------------*/
\r
669 static void prvSendSamplePage( void )
\r
671 extern long lErrorInTask;
\r
672 unsigned long ulTxAddress;
\r
673 unsigned char ucShadow;
\r
675 static unsigned long ulRefreshCount = 0x00;
\r
676 static char cPageBuffer[ tcpBUFFER_LEN ];
\r
679 /* This function just generates a sample page of HTML which gets
\r
680 sent each time a client attaches to the socket. The page is created
\r
681 from two fixed strings (cSamplePageFirstPart and cSamplePageSecondPart)
\r
682 with a bit of dynamically generated data in the middle. */
\r
684 /* We need to know the address to which the html string should be sent
\r
685 in the WIZnet Tx buffer. First read the shadow register. */
\r
686 prvReadRegister( &ucShadow, tcpTX_WRITE_SHADOW_REG, tcpSHADOW_READ_LEN );
\r
688 /* Now a short delay is required. */
\r
689 vTaskDelay( tcpSHORT_DELAY );
\r
691 /* Now we can read the real pointer value. */
\r
692 prvReadRegister( ( unsigned char * ) &ulTxAddress, tcpTX_WRITE_POINTER_REG, sizeof( ulTxAddress ) );
\r
694 /* Make sure endieness is correct. */
\r
695 ulTxAddress = htonl( ulTxAddress );
\r
697 /* Send the start of the page. */
\r
698 prvWriteString( cSamplePageFirstPart, strlen( cSamplePageFirstPart ), &ulTxAddress );
\r
700 /* Generate a bit of dynamic data and place it in the buffer ready to be
\r
702 strcpy( cPageBuffer, "<BR>Number of ticks since boot = 0x" );
\r
703 lIndex = strlen( cPageBuffer );
\r
704 ultoa( xTaskGetTickCount(), &( cPageBuffer[ lIndex ] ), 0 );
\r
705 strcat( cPageBuffer, "<br>Number of tasks executing = ");
\r
706 lIndex = strlen( cPageBuffer );
\r
707 ultoa( ( unsigned long ) uxTaskGetNumberOfTasks(), &( cPageBuffer[ lIndex ] ), 0 );
\r
708 strcat( cPageBuffer, "<br>IO port 0 state (used by flash tasks) = 0x" );
\r
709 lIndex = strlen( cPageBuffer );
\r
710 ultoa( ( unsigned long ) GPIO0_IOPIN, &( cPageBuffer[ lIndex ] ), 0 );
\r
711 strcat( cPageBuffer, "<br>Refresh = 0x" );
\r
712 lIndex = strlen( cPageBuffer );
\r
713 ultoa( ( unsigned long ) ulRefreshCount, &( cPageBuffer[ lIndex ] ), 0 );
\r
717 strcat( cPageBuffer, "<p>An error has occurred in at least one task." );
\r
721 strcat( cPageBuffer, "<p>All tasks executing without error." );
\r
726 /* Send the dynamically generated string. */
\r
727 prvWriteString( cPageBuffer, strlen( cPageBuffer ), &ulTxAddress );
\r
729 /* Finish the page. */
\r
730 prvWriteString( cSamplePageSecondPart, strlen( cSamplePageSecondPart ), &ulTxAddress );
\r
732 /* Tell the WIZnet to send the data we have just written to its Tx buffer. */
\r
733 prvFlushBuffer( ulTxAddress );
\r