2 * FreeRTOS Kernel V10.0.0
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3 * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved.
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5 * Permission is hereby granted, free of charge, to any person obtaining a copy of
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6 * this software and associated documentation files (the "Software"), to deal in
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7 * the Software without restriction, including without limitation the rights to
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8 * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
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9 * the Software, and to permit persons to whom the Software is furnished to do so,
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10 * subject to the following conditions:
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12 * The above copyright notice and this permission notice shall be included in all
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13 * copies or substantial portions of the Software. If you wish to use our Amazon
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14 * FreeRTOS name, please do so in a fair use way that does not cause confusion.
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16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
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18 * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
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19 * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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20 * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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21 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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23 * http://www.FreeRTOS.org
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24 * http://aws.amazon.com/freertos
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26 * 1 tab == 4 spaces!
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30 /* Standard includes. */
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33 /* Scheduler include files. */
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34 #include "FreeRTOS.h"
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39 /* Application includes. */
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42 /*-----------------------------------------------------------*/
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44 /* Bit definitions within the I2CONCLR register. */
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45 #define i2cSTA_BIT ( ( unsigned char ) 0x20 )
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46 #define i2cSI_BIT ( ( unsigned char ) 0x08 )
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47 #define i2cSTO_BIT ( ( unsigned char ) 0x10 )
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48 #define i2cAA_BIT ( ( unsigned char ) 0x04 )
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50 /* Status codes for the I2STAT register. */
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51 #define i2cSTATUS_START_TXED ( 0x08 )
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52 #define i2cSTATUS_REP_START_TXED ( 0x10 )
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53 #define i2cSTATUS_TX_ADDR_ACKED ( 0x18 )
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54 #define i2cSTATUS_DATA_TXED ( 0x28 )
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55 #define i2cSTATUS_RX_ADDR_ACKED ( 0x40 )
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56 #define i2cSTATUS_DATA_RXED ( 0x50 )
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57 #define i2cSTATUS_LAST_BYTE_RXED ( 0x58 )
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59 /* Constants for operation of the VIC. */
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60 #define i2cCLEAR_VIC_INTERRUPT ( 0 )
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62 /* Misc constants. */
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63 #define i2cJUST_ONE_BYTE_TO_RX ( 1 )
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64 #define i2cBUFFER_ADDRESS_BYTES ( 2 )
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66 /* End the current transmission and free the bus. */
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67 #define i2cEND_TRANSMISSION( lStatus ) \
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69 I2C_I2CONCLR = i2cAA_BIT; \
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70 I2C_I2CONSET = i2cSTO_BIT; \
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71 eCurrentState = eSentStart; \
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72 lTransactionCompleted = lStatus; \
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74 /*-----------------------------------------------------------*/
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76 /* Valid i2c communication states. */
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79 eSentStart, /*<< Last action was the transmission of a start bit. */
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80 eSentAddressForWrite, /*<< Last action was the transmission of the slave address we are to write to. */
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81 eSentAddressForRead, /*<< Last action was the transmission of the slave address we are to read from. */
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82 eSentData, /*<< Last action was the transmission of a data byte. */
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83 eReceiveData /*<< We expected data to be received. */
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85 /*-----------------------------------------------------------*/
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87 /* Points to the message currently being sent. */
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88 volatile xI2CMessage *pxCurrentMessage = NULL;
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90 /* The queue of messages waiting to be transmitted. */
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91 static QueueHandle_t xMessagesForTx;
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93 /* Flag used to indicate whether or not the ISR is amid sending a message. */
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94 unsigned long ulBusFree = ( unsigned long ) pdTRUE;
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96 /* Setting this to true will cause the TCP task to think a message is
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97 complete and thus restart. It can therefore be used under error states
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98 to force a restart. */
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99 volatile long lTransactionCompleted = pdTRUE;
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101 /*-----------------------------------------------------------*/
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103 void vI2CISRCreateQueues( unsigned portBASE_TYPE uxQueueLength, QueueHandle_t *pxTxMessages, unsigned long **ppulBusFree )
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105 /* Create the queues used to hold Rx and Tx characters. */
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106 xMessagesForTx = xQueueCreate( uxQueueLength, ( unsigned portBASE_TYPE ) sizeof( xI2CMessage * ) );
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108 /* Pass back a reference to the queue and bus free flag so the I2C API file
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109 can post messages. */
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110 *pxTxMessages = xMessagesForTx;
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111 *ppulBusFree = &ulBusFree;
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113 /*-----------------------------------------------------------*/
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115 /* The ISR entry point. */
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116 void vI2C_ISR_Wrapper( void ) __attribute__ (( naked ));
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118 /* The ISR function to perform the actual work. This must be a separate
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119 function from the wrapper to ensure the correct stack frame is set up. */
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120 void vI2C_ISR_Handler( void );
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122 /*-----------------------------------------------------------*/
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124 void vI2C_ISR_Wrapper( void )
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126 /* Save the context of the interrupted task. */
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127 portSAVE_CONTEXT();
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129 /* Call the handler to perform the actual work. This must be a
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130 separate function to ensure the correct stack frame is set up. */
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131 vI2C_ISR_Handler();
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133 /* Restore the context of whichever task is going to run next. */
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134 portRESTORE_CONTEXT();
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136 /*-----------------------------------------------------------*/
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138 void vI2C_ISR_Handler( void )
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140 /* Holds the current transmission state. */
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141 static I2C_STATE eCurrentState = eSentStart;
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142 static long lMessageIndex = -i2cBUFFER_ADDRESS_BYTES; /* There are two address bytes to send prior to the data. */
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143 portBASE_TYPE xHigherPriorityTaskWoken = pdFALSE;
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146 /* The action taken for this interrupt depends on our current state. */
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147 switch( eCurrentState )
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151 /* We sent a start bit, if it was successful we can
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152 go on to send the slave address. */
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153 if( ( I2C_I2STAT == i2cSTATUS_START_TXED ) || ( I2C_I2STAT == i2cSTATUS_REP_START_TXED ) )
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155 /* Send the slave address. */
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156 I2C_I2DAT = pxCurrentMessage->ucSlaveAddress;
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158 if( pxCurrentMessage->ucSlaveAddress & i2cREAD )
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160 /* We are then going to read bytes back from the
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162 eCurrentState = eSentAddressForRead;
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164 /* Initialise the buffer index so the first byte goes
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165 into the first buffer position. */
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170 /* We are then going to write some data to the slave. */
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171 eCurrentState = eSentAddressForWrite;
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173 /* When writing bytes we first have to send the two
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174 byte buffer address so lMessageIndex is set negative,
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175 when it reaches 0 it is time to send the actual data. */
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176 lMessageIndex = -i2cBUFFER_ADDRESS_BYTES;
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181 /* Could not send the start bit so give up. */
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182 i2cEND_TRANSMISSION( pdFAIL );
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185 I2C_I2CONCLR = i2cSTA_BIT;
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189 case eSentAddressForWrite :
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191 /* We sent the address of the slave we are going to write to.
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192 If this was acknowledged we can go on to send the data. */
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193 if( I2C_I2STAT == i2cSTATUS_TX_ADDR_ACKED )
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195 /* Start the first byte transmitting which is the
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196 first byte of the buffer address to which the data will
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198 I2C_I2DAT = pxCurrentMessage->ucBufferAddressHighByte;
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199 eCurrentState = eSentData;
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203 /* Address was not acknowledged so give up. */
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204 i2cEND_TRANSMISSION( pdFAIL );
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208 case eSentAddressForRead :
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210 /* We sent the address of the slave we are going to read from.
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211 If this was acknowledged we can go on to read the data. */
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212 if( I2C_I2STAT == i2cSTATUS_RX_ADDR_ACKED )
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214 eCurrentState = eReceiveData;
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215 if( pxCurrentMessage->lMessageLength > i2cJUST_ONE_BYTE_TO_RX )
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217 /* Don't ack the last byte of the message. */
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218 I2C_I2CONSET = i2cAA_BIT;
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223 /* Something unexpected happened - give up. */
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224 i2cEND_TRANSMISSION( pdFAIL );
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228 case eReceiveData :
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230 /* We have just received a byte from the slave. */
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231 if( ( I2C_I2STAT == i2cSTATUS_DATA_RXED ) || ( I2C_I2STAT == i2cSTATUS_LAST_BYTE_RXED ) )
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233 /* Buffer the byte just received then increment the index
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234 so it points to the next free space. */
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235 pxCurrentMessage->pucBuffer[ lMessageIndex ] = I2C_I2DAT;
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238 /* How many more bytes are we expecting to receive? */
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239 lBytesLeft = pxCurrentMessage->lMessageLength - lMessageIndex;
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240 if( lBytesLeft == ( unsigned long ) 0 )
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242 /* This was the last byte in the message. */
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243 i2cEND_TRANSMISSION( pdPASS );
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245 /* If xMessageCompleteSemaphore is not null then there
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246 is a task waiting for this message to complete and we
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247 must 'give' the semaphore so the task is woken.*/
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248 if( pxCurrentMessage->xMessageCompleteSemaphore )
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250 xSemaphoreGiveFromISR( pxCurrentMessage->xMessageCompleteSemaphore, &xHigherPriorityTaskWoken );
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253 /* Are there any other messages to transact? */
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254 if( xQueueReceiveFromISR( xMessagesForTx, &pxCurrentMessage, &xHigherPriorityTaskWoken ) == pdTRUE )
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256 /* Start the next message - which was
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257 retrieved from the queue. */
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258 I2C_I2CONSET = i2cSTA_BIT;
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262 /* No more messages were found to be waiting for
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263 transaction so the bus is free. */
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264 ulBusFree = ( unsigned long ) pdTRUE;
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269 /* There are more bytes to receive but don't ack the
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271 if( lBytesLeft <= i2cJUST_ONE_BYTE_TO_RX )
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273 I2C_I2CONCLR = i2cAA_BIT;
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279 /* Something unexpected happened - give up. */
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280 i2cEND_TRANSMISSION( pdFAIL );
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287 /* We sent a data byte, if successful send the next byte in
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289 if( I2C_I2STAT == i2cSTATUS_DATA_TXED )
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291 /* Index to the next byte to send. */
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293 if( lMessageIndex < 0 )
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295 /* lMessage index is still negative so we have so far
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296 only sent the first byte of the buffer address. Send
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297 the second byte now, then initialise the buffer index
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298 to zero so the next byte sent comes from the actual
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300 I2C_I2DAT = pxCurrentMessage->ucBufferAddressLowByte;
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302 else if( lMessageIndex < pxCurrentMessage->lMessageLength )
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304 /* Simply send the next byte in the tx buffer. */
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305 I2C_I2DAT = pxCurrentMessage->pucBuffer[ lMessageIndex ];
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309 /* No more bytes in this message to be send. Finished
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310 sending message - send a stop bit. */
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311 i2cEND_TRANSMISSION( pdPASS );
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313 /* If xMessageCompleteSemaphore is not null then there
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314 is a task waiting for this message to be sent and the
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315 semaphore must be 'given' to wake the task. */
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316 if( pxCurrentMessage->xMessageCompleteSemaphore )
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318 xSemaphoreGiveFromISR( pxCurrentMessage->xMessageCompleteSemaphore, &xHigherPriorityTaskWoken );
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321 /* Are there any other messages to transact? */
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322 if( xQueueReceiveFromISR( xMessagesForTx, &pxCurrentMessage, &xHigherPriorityTaskWoken ) == pdTRUE )
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324 /* Start the next message from the Tx queue. */
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325 I2C_I2CONSET = i2cSTA_BIT;
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329 /* No more message were queues for transaction so
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330 the bus is free. */
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331 ulBusFree = ( unsigned long ) pdTRUE;
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337 /* Something unexpected happened, give up. */
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338 i2cEND_TRANSMISSION( pdFAIL );
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344 /* Should never get here. */
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345 eCurrentState = eSentStart;
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349 /* Clear the interrupt. */
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350 I2C_I2CONCLR = i2cSI_BIT;
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351 VICVectAddr = i2cCLEAR_VIC_INTERRUPT;
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353 if( xHigherPriorityTaskWoken )
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355 portYIELD_FROM_ISR();
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358 /*-----------------------------------------------------------*/
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