1 /*This file is prepared for Doxygen automatic documentation generation.*/
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2 /*! \file *********************************************************************
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4 * \brief INTC driver for AVR32 UC3.
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6 * AVR32 Interrupt Controller driver module.
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8 * - Compiler: IAR EWAVR32 and GNU GCC for AVR32
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9 * - Supported devices: All AVR32 devices with an INTC module can be used.
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12 * \author Atmel Corporation: http://www.atmel.com \n
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13 * Support and FAQ: http://support.atmel.no/
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15 ******************************************************************************/
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17 /* Copyright (c) 2007, Atmel Corporation All rights reserved.
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19 * Redistribution and use in source and binary forms, with or without
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20 * modification, are permitted provided that the following conditions are met:
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22 * 1. Redistributions of source code must retain the above copyright notice,
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23 * this list of conditions and the following disclaimer.
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25 * 2. Redistributions in binary form must reproduce the above copyright notice,
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26 * this list of conditions and the following disclaimer in the documentation
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27 * and/or other materials provided with the distribution.
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29 * 3. The name of ATMEL may not be used to endorse or promote products derived
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30 * from this software without specific prior written permission.
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32 * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED
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33 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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34 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND
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35 * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT,
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36 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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37 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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38 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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39 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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40 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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41 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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45 #include <avr32/io.h>
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46 #include "compiler.h"
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47 #include "preprocessor.h"
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51 //! Values to store in the interrupt priority registers for the various interrupt priority levels.
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52 extern const unsigned int ipr_val[AVR32_INTC_NUM_INT_LEVELS];
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54 //! Creates a table of interrupt line handlers per interrupt group in order to optimize RAM space.
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55 //! Each line handler table contains a set of pointers to interrupt handlers.
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57 #define DECL_INT_LINE_HANDLER_TABLE(GRP, unused) \
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58 static volatile __int_handler _int_line_handler_table_##GRP[Max(AVR32_INTC_NUM_IRQS_PER_GRP##GRP, 1)];
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60 #define DECL_INT_LINE_HANDLER_TABLE(GRP, unused) \
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61 static volatile __no_init __int_handler _int_line_handler_table_##GRP[Max(AVR32_INTC_NUM_IRQS_PER_GRP##GRP, 1)];
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63 MREPEAT(AVR32_INTC_NUM_INT_GRPS, DECL_INT_LINE_HANDLER_TABLE, ~);
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64 #undef DECL_INT_LINE_HANDLER_TABLE
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66 //! Table containing for each interrupt group the number of interrupt request
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67 //! lines and a pointer to the table of interrupt line handlers.
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70 unsigned int num_irqs;
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71 volatile __int_handler *_int_line_handler_table;
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72 } _int_handler_table[AVR32_INTC_NUM_INT_GRPS] =
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74 #define INSERT_INT_LINE_HANDLER_TABLE(GRP, unused) \
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75 {AVR32_INTC_NUM_IRQS_PER_GRP##GRP, _int_line_handler_table_##GRP},
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76 MREPEAT(AVR32_INTC_NUM_INT_GRPS, INSERT_INT_LINE_HANDLER_TABLE, ~)
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77 #undef INSERT_INT_LINE_HANDLER_TABLE
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81 /*! \brief Default interrupt handler.
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83 * \note Taken and adapted from Newlib.
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86 __attribute__((__interrupt__))
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90 static void _unhandled_interrupt(void)
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92 // Catch unregistered interrupts.
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97 /*! \brief Gets the interrupt handler of the current event at the \a int_lev
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98 * interrupt priority level (called from exception.S).
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100 * \param int_lev Interrupt priority level to handle.
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102 * \return Interrupt handler to execute.
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104 * \note Taken and adapted from Newlib.
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106 __int_handler _get_interrupt_handler(unsigned int int_lev)
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108 // ICR3 is mapped first, ICR0 last.
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109 // Code in exception.S puts int_lev in R12 which is used by AVR32-GCC to pass
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110 // a single argument to a function.
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111 unsigned int int_grp = (&AVR32_INTC.icr3)[INT3 - int_lev];
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112 unsigned int int_req = AVR32_INTC.irr[int_grp];
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114 // As an interrupt may disappear while it is being fetched by the CPU
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115 // (spurious interrupt caused by a delayed response from an MCU peripheral to
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116 // an interrupt flag clear or interrupt disable instruction), check if there
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117 // are remaining interrupt lines to process.
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118 // If a spurious interrupt occurs, the status register (SR) contains an
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119 // execution mode and interrupt level masks corresponding to a level 0
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120 // interrupt, whatever the interrupt priority level causing the spurious
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121 // event. This behavior has been chosen because a spurious interrupt has not
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122 // to be a priority one and because it may not cause any trouble to other
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124 // However, these spurious interrupts place the hardware in an unstable state
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125 // and could give problems in other/future versions of the CPU, so the
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126 // software has to be written so that they never occur. The only safe way of
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127 // achieving this is to always clear or disable peripheral interrupts with the
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128 // following sequence:
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129 // 1: Mask the interrupt in the CPU by setting GM (or IxM) in SR.
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130 // 2: Perform the bus access to the peripheral register that clears or
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131 // disables the interrupt.
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132 // 3: Wait until the interrupt has actually been cleared or disabled by the
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133 // peripheral. This is usually performed by reading from a register in the
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134 // same peripheral (it DOES NOT have to be the same register that was
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135 // accessed in step 2, but it MUST be in the same peripheral), what takes
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136 // bus system latencies into account, but peripheral internal latencies
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137 // (generally 0 cycle) also have to be considered.
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138 // 4: Unmask the interrupt in the CPU by clearing GM (or IxM) in SR.
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139 // Note that steps 1 and 4 are useless inside interrupt handlers as the
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140 // corresponding interrupt level is automatically masked by IxM (unless IxM is
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141 // explicitly cleared by the software).
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143 // Get the right IRQ handler.
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145 // If several interrupt lines are active in the group, the interrupt line with
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146 // the highest number is selected. This is to be coherent with the
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147 // prioritization of interrupt groups performed by the hardware interrupt
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150 // If no handler has been registered for the pending interrupt,
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151 // _unhandled_interrupt will be selected thanks to the initialization of
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152 // _int_line_handler_table_x by INTC_init_interrupts.
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154 // exception.S will provide the interrupt handler with a clean interrupt stack
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155 // frame, with nothing more pushed onto the stack. The interrupt handler must
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156 // manage the `rete' instruction, what can be done thanks to pure assembly,
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157 // inline assembly or the `__attribute__((__interrupt__))' C function
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159 return (int_req) ? _int_handler_table[int_grp]._int_line_handler_table[32 - clz(int_req) - 1] : NULL;
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163 void INTC_init_interrupts(void)
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165 unsigned int int_grp, int_req;
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167 // For all interrupt groups,
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168 for (int_grp = 0; int_grp < AVR32_INTC_NUM_INT_GRPS; int_grp++)
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170 // For all interrupt request lines of each group,
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171 for (int_req = 0; int_req < _int_handler_table[int_grp].num_irqs; int_req++)
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173 // Assign _unhandled_interrupt as default interrupt handler.
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174 _int_handler_table[int_grp]._int_line_handler_table[int_req] = &_unhandled_interrupt;
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177 // Set the interrupt group priority register to its default value.
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178 // By default, all interrupt groups are linked to the interrupt priority
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179 // level 0 and to the interrupt vector _int0.
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180 AVR32_INTC.ipr[int_grp] = ipr_val[INT0];
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185 void INTC_register_interrupt(__int_handler handler, unsigned int irq, unsigned int int_lev)
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187 // Determine the group of the IRQ.
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188 unsigned int int_grp = irq / AVR32_INTC_MAX_NUM_IRQS_PER_GRP;
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190 // Store in _int_line_handler_table_x the pointer to the interrupt handler, so
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191 // that _get_interrupt_handler can retrieve it when the interrupt is vectored.
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192 _int_handler_table[int_grp]._int_line_handler_table[irq % AVR32_INTC_MAX_NUM_IRQS_PER_GRP] = handler;
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194 // Program the corresponding IPRX register to set the interrupt priority level
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195 // and the interrupt vector offset that will be fetched by the core interrupt
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197 // NOTE: The _intx functions are intermediate assembly functions between the
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198 // core interrupt system and the user interrupt handler.
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199 AVR32_INTC.ipr[int_grp] = ipr_val[int_lev & (AVR32_INTC_IPR0_INTLEV_MASK >> AVR32_INTC_IPR0_INTLEV_OFFSET)];
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