1 /*This file has been prepared for Doxygen automatic documentation generation.*/
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2 /*! \file *********************************************************************
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4 * \brief MACB driver for EVK1100 board.
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6 * This file defines a useful set of functions for the MACB interface on
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9 * - Compiler: IAR EWAVR32 and GNU GCC for AVR32
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10 * - Supported devices: All AVR32 devices with a MACB module can be used.
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13 * \author Atmel Corporation: http://www.atmel.com \n
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14 * Support and FAQ: http://support.atmel.no/
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16 *****************************************************************************/
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18 /* Copyright (c) 2007, Atmel Corporation All rights reserved.
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20 * Redistribution and use in source and binary forms, with or without
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21 * modification, are permitted provided that the following conditions are met:
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23 * 1. Redistributions of source code must retain the above copyright notice,
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24 * this list of conditions and the following disclaimer.
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26 * 2. Redistributions in binary form must reproduce the above copyright notice,
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27 * this list of conditions and the following disclaimer in the documentation
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28 * and/or other materials provided with the distribution.
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30 * 3. The name of ATMEL may not be used to endorse or promote products derived
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31 * from this software without specific prior written permission.
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33 * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED
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34 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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35 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND
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36 * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT,
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37 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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38 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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39 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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40 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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41 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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42 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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48 #include <avr32/io.h>
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51 #ifdef FREERTOS_USED
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52 #include "FreeRTOS.h"
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58 #include "conf_eth.h"
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62 /* Size of each receive buffer - DO NOT CHANGE. */
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63 #define RX_BUFFER_SIZE 128
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66 /* The buffer addresses written into the descriptors must be aligned so the
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67 last few bits are zero. These bits have special meaning for the MACB
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68 peripheral and cannot be used as part of the address. */
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69 #define ADDRESS_MASK ( ( unsigned long ) 0xFFFFFFFC )
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71 /* Bit used within the address stored in the descriptor to mark the last
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72 descriptor in the array. */
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73 #define RX_WRAP_BIT ( ( unsigned long ) 0x02 )
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75 /* A short delay is used to wait for a buffer to become available, should
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76 one not be immediately available when trying to transmit a frame. */
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77 #define BUFFER_WAIT_DELAY ( 2 )
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79 #ifndef FREERTOS_USED
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80 #define portENTER_CRITICAL Disable_global_interrupt
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81 #define portEXIT_CRITICAL Enable_global_interrupt
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82 #define portENTER_SWITCHING_ISR()
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83 #define portEXIT_SWITCHING_ISR()
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87 /* Buffer written to by the MACB DMA. Must be aligned as described by the
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88 comment above the ADDRESS_MASK definition. */
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90 static volatile char pcRxBuffer[ ETHERNET_CONF_NB_RX_BUFFERS * RX_BUFFER_SIZE ] __attribute__ ((aligned (8)));
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92 #pragma data_alignment=8
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93 static volatile char pcRxBuffer[ ETHERNET_CONF_NB_RX_BUFFERS * RX_BUFFER_SIZE ];
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97 /* Buffer read by the MACB DMA. Must be aligned as described by the comment
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98 above the ADDRESS_MASK definition. */
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100 static volatile char pcTxBuffer[ ETHERNET_CONF_NB_TX_BUFFERS * ETHERNET_CONF_TX_BUFFER_SIZE ] __attribute__ ((aligned (8)));
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102 #pragma data_alignment=8
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103 static volatile char pcTxBuffer[ ETHERNET_CONF_NB_TX_BUFFERS * ETHERNET_CONF_TX_BUFFER_SIZE ];
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106 /* Descriptors used to communicate between the program and the MACB peripheral.
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107 These descriptors hold the locations and state of the Rx and Tx buffers. */
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108 static volatile AVR32_TxTdDescriptor xTxDescriptors[ ETHERNET_CONF_NB_TX_BUFFERS ];
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109 static volatile AVR32_RxTdDescriptor xRxDescriptors[ ETHERNET_CONF_NB_RX_BUFFERS ];
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111 /* The IP and Ethernet addresses are read from the header files. */
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112 char cMACAddress[ 6 ] = { ETHERNET_CONF_ETHADDR0,ETHERNET_CONF_ETHADDR1,ETHERNET_CONF_ETHADDR2,ETHERNET_CONF_ETHADDR3,ETHERNET_CONF_ETHADDR4,ETHERNET_CONF_ETHADDR5 };
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114 /*-----------------------------------------------------------*/
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116 /* See the header file for descriptions of public functions. */
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119 * Prototype for the MACB interrupt function - called by the asm wrapper.
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121 #ifdef FREERTOS_USED
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123 __attribute__((naked))
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125 #pragma shadow_registers = full // Naked.
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129 __attribute__((__interrupt__))
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134 void vMACB_ISR( void );
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135 static long prvMACB_ISR_NonNakedBehaviour( void );
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138 #if ETHERNET_CONF_USE_PHY_IT
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139 #ifdef FREERTOS_USED
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141 __attribute__((naked))
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143 #pragma shadow_registers = full // Naked.
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147 __attribute__((__interrupt__))
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152 void vPHY_ISR( void );
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153 static long prvPHY_ISR_NonNakedBehaviour( void );
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158 * Initialise both the Tx and Rx descriptors used by the MACB.
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160 static void prvSetupDescriptors(volatile avr32_macb_t * macb);
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163 * Write our MAC address into the MACB.
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165 static void prvSetupMACAddress( volatile avr32_macb_t * macb );
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168 * Configure the MACB for interrupts.
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170 static void prvSetupMACBInterrupt( volatile avr32_macb_t * macb );
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173 * Some initialisation functions.
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175 static Bool prvProbePHY( volatile avr32_macb_t * macb );
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176 static unsigned long ulReadMDIO(volatile avr32_macb_t * macb, unsigned short usAddress);
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177 static void vWriteMDIO(volatile avr32_macb_t * macb, unsigned short usAddress, unsigned short usValue);
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180 #ifdef FREERTOS_USED
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181 /* The semaphore used by the MACB ISR to wake the MACB task. */
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182 static SemaphoreHandle_t xSemaphore = NULL;
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184 static volatile Bool DataToRead = FALSE;
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187 /* Holds the index to the next buffer from which data will be read. */
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188 volatile unsigned long ulNextRxBuffer = 0;
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191 long lMACBSend(volatile avr32_macb_t * macb, char *pcFrom, unsigned long ulLength, long lEndOfFrame )
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193 static unsigned long uxTxBufferIndex = 0;
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195 unsigned long ulLastBuffer, ulDataBuffered = 0, ulDataRemainingToSend, ulLengthToSend;
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198 /* If the length of data to be transmitted is greater than each individual
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199 transmit buffer then the data will be split into more than one buffer.
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200 Loop until the entire length has been buffered. */
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201 while( ulDataBuffered < ulLength )
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203 // Is a buffer available ?
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204 while( !( xTxDescriptors[ uxTxBufferIndex ].U_Status.status & AVR32_TRANSMIT_OK ) )
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206 // There is no room to write the Tx data to the Tx buffer.
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207 // Wait a short while, then try again.
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208 #ifdef FREERTOS_USED
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209 vTaskDelay( BUFFER_WAIT_DELAY );
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211 __asm__ __volatile__ ("nop");
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215 portENTER_CRITICAL();
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217 // Get the address of the buffer from the descriptor,
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218 // then copy the data into the buffer.
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219 pcBuffer = ( char * ) xTxDescriptors[ uxTxBufferIndex ].addr;
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221 // How much can we write to the buffer ?
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222 ulDataRemainingToSend = ulLength - ulDataBuffered;
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223 if( ulDataRemainingToSend <= ETHERNET_CONF_TX_BUFFER_SIZE )
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225 // We can write all the remaining bytes.
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226 ulLengthToSend = ulDataRemainingToSend;
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230 // We can't write more than ETH_TX_BUFFER_SIZE in one go.
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231 ulLengthToSend = ETHERNET_CONF_TX_BUFFER_SIZE;
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233 // Copy the data into the buffer.
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234 memcpy( ( void * ) pcBuffer, ( void * ) &( pcFrom[ ulDataBuffered ] ), ulLengthToSend );
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235 ulDataBuffered += ulLengthToSend;
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236 // Is this the last data for the frame ?
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237 if( lEndOfFrame && ( ulDataBuffered >= ulLength ) )
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239 // No more data remains for this frame so we can start the transmission.
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240 ulLastBuffer = AVR32_LAST_BUFFER;
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244 // More data to come for this frame.
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247 // Fill out the necessary in the descriptor to get the data sent,
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248 // then move to the next descriptor, wrapping if necessary.
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249 if( uxTxBufferIndex >= ( ETHERNET_CONF_NB_TX_BUFFERS - 1 ) )
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251 xTxDescriptors[ uxTxBufferIndex ].U_Status.status = ( ulLengthToSend & ( unsigned long ) AVR32_LENGTH_FRAME )
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253 | AVR32_TRANSMIT_WRAP;
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254 uxTxBufferIndex = 0;
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258 xTxDescriptors[ uxTxBufferIndex ].U_Status.status = ( ulLengthToSend & ( unsigned long ) AVR32_LENGTH_FRAME )
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262 /* If this is the last buffer to be sent for this frame we can
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263 start the transmission. */
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266 macb->ncr |= AVR32_MACB_TSTART_MASK;
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269 portEXIT_CRITICAL();
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276 unsigned long ulMACBInputLength( void )
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278 register unsigned long ulIndex , ulLength = 0;
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279 unsigned int uiTemp;
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281 // Skip any fragments. We are looking for the first buffer that contains
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282 // data and has the SOF (start of frame) bit set.
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283 while( ( xRxDescriptors[ ulNextRxBuffer ].addr & AVR32_OWNERSHIP_BIT ) && !( xRxDescriptors[ ulNextRxBuffer ].U_Status.status & AVR32_SOF ) )
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285 // Ignoring this buffer. Mark it as free again.
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286 uiTemp = xRxDescriptors[ ulNextRxBuffer ].addr;
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287 xRxDescriptors[ ulNextRxBuffer ].addr = uiTemp & ~( AVR32_OWNERSHIP_BIT );
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289 if( ulNextRxBuffer >= ETHERNET_CONF_NB_RX_BUFFERS )
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291 ulNextRxBuffer = 0;
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295 // We are going to walk through the descriptors that make up this frame,
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296 // but don't want to alter ulNextRxBuffer as this would prevent vMACBRead()
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297 // from finding the data. Therefore use a copy of ulNextRxBuffer instead.
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298 ulIndex = ulNextRxBuffer;
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300 // Walk through the descriptors until we find the last buffer for this frame.
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301 // The last buffer will give us the length of the entire frame.
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302 while( ( xRxDescriptors[ ulIndex ].addr & AVR32_OWNERSHIP_BIT ) && !ulLength )
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304 ulLength = xRxDescriptors[ ulIndex ].U_Status.status & AVR32_LENGTH_FRAME;
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305 // Increment to the next buffer, wrapping if necessary.
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307 if( ulIndex >= ETHERNET_CONF_NB_RX_BUFFERS )
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314 /*-----------------------------------------------------------*/
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316 void vMACBRead( char *pcTo, unsigned long ulSectionLength, unsigned long ulTotalFrameLength )
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318 static unsigned long ulSectionBytesReadSoFar = 0, ulBufferPosition = 0, ulFameBytesReadSoFar = 0;
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319 static char *pcSource;
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320 register unsigned long ulBytesRemainingInBuffer, ulRemainingSectionBytes;
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321 unsigned int uiTemp;
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323 // Read ulSectionLength bytes from the Rx buffers.
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324 // This is not necessarily any correspondence between the length of our Rx buffers,
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325 // and the length of the data we are returning or the length of the data being requested.
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326 // Therefore, between calls we have to remember not only which buffer we are currently
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327 // processing, but our position within that buffer.
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328 // This would be greatly simplified if PBUF_POOL_BUFSIZE could be guaranteed to be greater
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329 // than the size of each Rx buffer, and that memory fragmentation did not occur.
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331 // This function should only be called after a call to ulMACBInputLength().
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332 // This will ensure ulNextRxBuffer is set to the correct buffer. */
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334 // vMACBRead is called with pcTo set to NULL to indicate that we are about
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335 // to read a new frame. Any fragments remaining in the frame we were
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336 // processing during the last call should be dropped.
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339 // How many bytes are indicated as being in this buffer?
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340 // If none then the buffer is completely full and the frame is contained within more
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341 // than one buffer.
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342 // Reset our state variables ready for the next read from this buffer.
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343 pcSource = ( char * )( xRxDescriptors[ ulNextRxBuffer ].addr & ADDRESS_MASK );
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344 ulFameBytesReadSoFar = ( unsigned long ) 0;
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345 ulBufferPosition = ( unsigned long ) 0;
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349 // Loop until we have obtained the required amount of data.
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350 ulSectionBytesReadSoFar = 0;
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351 while( ulSectionBytesReadSoFar < ulSectionLength )
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353 // We may have already read some data from this buffer.
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354 // How much data remains in the buffer?
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355 ulBytesRemainingInBuffer = ( RX_BUFFER_SIZE - ulBufferPosition );
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357 // How many more bytes do we need to read before we have the
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358 // required amount of data?
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359 ulRemainingSectionBytes = ulSectionLength - ulSectionBytesReadSoFar;
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361 // Do we want more data than remains in the buffer?
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362 if( ulRemainingSectionBytes > ulBytesRemainingInBuffer )
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364 // We want more data than remains in the buffer so we can
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365 // write the remains of the buffer to the destination, then move
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366 // onto the next buffer to get the rest.
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367 memcpy( &( pcTo[ ulSectionBytesReadSoFar ] ), &( pcSource[ ulBufferPosition ] ), ulBytesRemainingInBuffer );
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368 ulSectionBytesReadSoFar += ulBytesRemainingInBuffer;
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369 ulFameBytesReadSoFar += ulBytesRemainingInBuffer;
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371 // Mark the buffer as free again.
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372 uiTemp = xRxDescriptors[ ulNextRxBuffer ].addr;
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373 xRxDescriptors[ ulNextRxBuffer ].addr = uiTemp & ~( AVR32_OWNERSHIP_BIT );
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374 // Move onto the next buffer.
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377 if( ulNextRxBuffer >= ETHERNET_CONF_NB_RX_BUFFERS )
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379 ulNextRxBuffer = ( unsigned long ) 0;
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382 // Reset the variables for the new buffer.
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383 pcSource = ( char * )( xRxDescriptors[ ulNextRxBuffer ].addr & ADDRESS_MASK );
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384 ulBufferPosition = ( unsigned long ) 0;
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388 // We have enough data in this buffer to send back.
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389 // Read out enough data and remember how far we read up to.
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390 memcpy( &( pcTo[ ulSectionBytesReadSoFar ] ), &( pcSource[ ulBufferPosition ] ), ulRemainingSectionBytes );
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392 // There may be more data in this buffer yet.
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393 // Increment our position in this buffer past the data we have just read.
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394 ulBufferPosition += ulRemainingSectionBytes;
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395 ulSectionBytesReadSoFar += ulRemainingSectionBytes;
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396 ulFameBytesReadSoFar += ulRemainingSectionBytes;
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398 // Have we now finished with this buffer?
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399 if( ( ulBufferPosition >= RX_BUFFER_SIZE ) || ( ulFameBytesReadSoFar >= ulTotalFrameLength ) )
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401 // Mark the buffer as free again.
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402 uiTemp = xRxDescriptors[ ulNextRxBuffer ].addr;
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403 xRxDescriptors[ ulNextRxBuffer ].addr = uiTemp & ~( AVR32_OWNERSHIP_BIT );
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404 // Move onto the next buffer.
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407 if( ulNextRxBuffer >= ETHERNET_CONF_NB_RX_BUFFERS )
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409 ulNextRxBuffer = 0;
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412 pcSource = ( char * )( xRxDescriptors[ ulNextRxBuffer ].addr & ADDRESS_MASK );
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413 ulBufferPosition = 0;
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419 /*-----------------------------------------------------------*/
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420 void vMACBSetMACAddress(const char * MACAddress)
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422 memcpy(cMACAddress, MACAddress, sizeof(cMACAddress));
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425 Bool xMACBInit( volatile avr32_macb_t * macb )
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427 volatile unsigned long status;
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429 // set up registers
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434 status = macb->isr;
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437 #if ETHERNET_CONF_USE_RMII_INTERFACE
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438 // RMII used, set 0 to the USRIO Register
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439 macb->usrio &= ~AVR32_MACB_RMII_MASK;
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441 // RMII not used, set 1 to the USRIO Register
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442 macb->usrio |= AVR32_MACB_RMII_MASK;
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445 // Load our MAC address into the MACB.
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446 prvSetupMACAddress(macb);
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448 // Setup the buffers and descriptors.
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449 prvSetupDescriptors(macb);
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451 #if ETHERNET_CONF_SYSTEM_CLOCK <= 20000000
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452 macb->ncfgr |= (AVR32_MACB_NCFGR_CLK_DIV8 << AVR32_MACB_NCFGR_CLK_OFFSET);
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453 #elif ETHERNET_CONF_SYSTEM_CLOCK <= 40000000
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454 macb->ncfgr |= (AVR32_MACB_NCFGR_CLK_DIV16 << AVR32_MACB_NCFGR_CLK_OFFSET);
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455 #elif ETHERNET_CONF_SYSTEM_CLOCK <= 80000000
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456 macb->ncfgr |= AVR32_MACB_NCFGR_CLK_DIV32 << AVR32_MACB_NCFGR_CLK_OFFSET;
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457 #elif ETHERNET_CONF_SYSTEM_CLOCK <= 160000000
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458 macb->ncfgr |= AVR32_MACB_NCFGR_CLK_DIV64 << AVR32_MACB_NCFGR_CLK_OFFSET;
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460 # error System clock too fast
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463 // Are we connected?
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464 if( prvProbePHY(macb) == TRUE )
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466 // Enable the interrupt!
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467 portENTER_CRITICAL();
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469 prvSetupMACBInterrupt(macb);
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471 portEXIT_CRITICAL();
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472 // Enable Rx and Tx, plus the stats register.
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473 macb->ncr = AVR32_MACB_NCR_TE_MASK | AVR32_MACB_NCR_RE_MASK;
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479 void vDisableMACBOperations(volatile avr32_macb_t * macb)
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481 #if ETHERNET_CONF_USE_PHY_IT
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482 volatile avr32_gpio_t *gpio = &AVR32_GPIO;
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483 volatile avr32_gpio_port_t *gpio_port = &gpio->port[MACB_INTERRUPT_PIN/32];
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485 gpio_port->ierc = 1 << (MACB_INTERRUPT_PIN%32);
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488 // write the MACB control register : disable Tx & Rx
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489 macb->ncr &= ~((1 << AVR32_MACB_RE_OFFSET) | (1 << AVR32_MACB_TE_OFFSET));
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490 // We no more want to interrupt on Rx and Tx events.
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491 macb->idr = AVR32_MACB_IER_RCOMP_MASK | AVR32_MACB_IER_TCOMP_MASK;
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495 void vClearMACBTxBuffer( void )
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497 static unsigned long uxNextBufferToClear = 0;
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499 // Called on Tx interrupt events to set the AVR32_TRANSMIT_OK bit in each
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500 // Tx buffer within the frame just transmitted. This marks all the buffers
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501 // as available again.
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503 // The first buffer in the frame should have the bit set automatically. */
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504 if( xTxDescriptors[ uxNextBufferToClear ].U_Status.status & AVR32_TRANSMIT_OK )
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506 // Loop through the other buffers in the frame.
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507 while( !( xTxDescriptors[ uxNextBufferToClear ].U_Status.status & AVR32_LAST_BUFFER ) )
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509 uxNextBufferToClear++;
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511 if( uxNextBufferToClear >= ETHERNET_CONF_NB_TX_BUFFERS )
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513 uxNextBufferToClear = 0;
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516 xTxDescriptors[ uxNextBufferToClear ].U_Status.status |= AVR32_TRANSMIT_OK;
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519 // Start with the next buffer the next time a Tx interrupt is called.
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520 uxNextBufferToClear++;
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522 // Do we need to wrap back to the first buffer?
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523 if( uxNextBufferToClear >= ETHERNET_CONF_NB_TX_BUFFERS )
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525 uxNextBufferToClear = 0;
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530 static void prvSetupDescriptors(volatile avr32_macb_t * macb)
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532 unsigned long xIndex;
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533 unsigned long ulAddress;
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535 // Initialise xRxDescriptors descriptor.
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536 for( xIndex = 0; xIndex < ETHERNET_CONF_NB_RX_BUFFERS; ++xIndex )
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538 // Calculate the address of the nth buffer within the array.
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539 ulAddress = ( unsigned long )( pcRxBuffer + ( xIndex * RX_BUFFER_SIZE ) );
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541 // Write the buffer address into the descriptor.
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542 // The DMA will place the data at this address when this descriptor is being used.
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543 // Mask off the bottom bits of the address as these have special meaning.
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544 xRxDescriptors[ xIndex ].addr = ulAddress & ADDRESS_MASK;
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547 // The last buffer has the wrap bit set so the MACB knows to wrap back
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548 // to the first buffer.
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549 xRxDescriptors[ ETHERNET_CONF_NB_RX_BUFFERS - 1 ].addr |= RX_WRAP_BIT;
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551 // Initialise xTxDescriptors.
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552 for( xIndex = 0; xIndex < ETHERNET_CONF_NB_TX_BUFFERS; ++xIndex )
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554 // Calculate the address of the nth buffer within the array.
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555 ulAddress = ( unsigned long )( pcTxBuffer + ( xIndex * ETHERNET_CONF_TX_BUFFER_SIZE ) );
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557 // Write the buffer address into the descriptor.
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558 // The DMA will read data from here when the descriptor is being used.
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559 xTxDescriptors[ xIndex ].addr = ulAddress & ADDRESS_MASK;
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560 xTxDescriptors[ xIndex ].U_Status.status = AVR32_TRANSMIT_OK;
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563 // The last buffer has the wrap bit set so the MACB knows to wrap back
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564 // to the first buffer.
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565 xTxDescriptors[ ETHERNET_CONF_NB_TX_BUFFERS - 1 ].U_Status.status = AVR32_TRANSMIT_WRAP | AVR32_TRANSMIT_OK;
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567 // Tell the MACB where to find the descriptors.
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568 macb->rbqp = ( unsigned long )xRxDescriptors;
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569 macb->tbqp = ( unsigned long )xTxDescriptors;
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571 // Enable the copy of data into the buffers, ignore broadcasts,
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572 // and don't copy FCS.
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573 macb->ncfgr |= (AVR32_MACB_CAF_MASK | AVR32_MACB_NBC_MASK | AVR32_MACB_NCFGR_DRFCS_MASK);
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577 static void prvSetupMACAddress( volatile avr32_macb_t * macb )
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579 // Must be written SA1L then SA1H.
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580 macb->sa1b = ( ( unsigned long ) cMACAddress[ 3 ] << 24 ) |
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581 ( ( unsigned long ) cMACAddress[ 2 ] << 16 ) |
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582 ( ( unsigned long ) cMACAddress[ 1 ] << 8 ) |
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585 macb->sa1t = ( ( unsigned long ) cMACAddress[ 5 ] << 8 ) |
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589 static void prvSetupMACBInterrupt( volatile avr32_macb_t * macb )
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591 #ifdef FREERTOS_USED
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592 // Create the semaphore used to trigger the MACB task.
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593 if (xSemaphore == NULL)
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595 vSemaphoreCreateBinary( xSemaphore );
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598 // Create the flag used to trigger the MACB polling task.
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599 DataToRead = FALSE;
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603 #ifdef FREERTOS_USED
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604 if( xSemaphore != NULL)
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606 // We start by 'taking' the semaphore so the ISR can 'give' it when the
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607 // first interrupt occurs.
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608 xSemaphoreTake( xSemaphore, 0 );
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610 // Setup the interrupt for MACB.
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611 // Register the interrupt handler to the interrupt controller at interrupt level 2
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612 INTC_register_interrupt((__int_handler)&vMACB_ISR, AVR32_MACB_IRQ, INT2);
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614 #if ETHERNET_CONF_USE_PHY_IT
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615 /* GPIO enable interrupt upon rising edge */
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616 gpio_enable_pin_interrupt(MACB_INTERRUPT_PIN, GPIO_FALLING_EDGE);
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617 // Setup the interrupt for PHY.
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618 // Register the interrupt handler to the interrupt controller at interrupt level 2
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619 INTC_register_interrupt((__int_handler)&vPHY_ISR, (AVR32_GPIO_IRQ_0 + (MACB_INTERRUPT_PIN/8)), INT2);
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620 /* enable interrupts on INT pin */
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621 vWriteMDIO( macb, PHY_MICR , ( MICR_INTEN | MICR_INTOE ));
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622 /* enable "link change" interrupt for Phy */
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623 vWriteMDIO( macb, PHY_MISR , MISR_LINK_INT_EN );
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626 // We want to interrupt on Rx and Tx events
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627 macb->ier = AVR32_MACB_IER_RCOMP_MASK | AVR32_MACB_IER_TCOMP_MASK;
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628 #ifdef FREERTOS_USED
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633 /*! Read a register on MDIO bus (access to the PHY)
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634 * This function is looping until PHY gets ready
\r
636 * \param macb Input. instance of the MACB to use
\r
637 * \param usAddress Input. register to set.
\r
639 * \return unsigned long data that has been read
\r
641 static unsigned long ulReadMDIO(volatile avr32_macb_t * macb, unsigned short usAddress)
\r
643 unsigned long value, status;
\r
645 // initiate transaction : enable management port
\r
646 macb->ncr |= AVR32_MACB_NCR_MPE_MASK;
\r
647 // Write the PHY configuration frame to the MAN register
\r
648 macb->man = (AVR32_MACB_SOF_MASK & (0x01<<AVR32_MACB_SOF_OFFSET)) // SOF
\r
649 | (2 << AVR32_MACB_CODE_OFFSET) // Code
\r
650 | (2 << AVR32_MACB_RW_OFFSET) // Read operation
\r
651 | ((ETHERNET_CONF_PHY_ADDR & 0x1f) << AVR32_MACB_PHYA_OFFSET) // Phy Add
\r
652 | (usAddress << AVR32_MACB_REGA_OFFSET); // Reg Add
\r
653 // wait for PHY to be ready
\r
655 status = macb->nsr;
\r
656 } while (!(status & AVR32_MACB_NSR_IDLE_MASK));
\r
657 // read the register value in maintenance register
\r
658 value = macb->man & 0x0000ffff;
\r
659 // disable management port
\r
660 macb->ncr &= ~AVR32_MACB_NCR_MPE_MASK;
\r
661 // return the read value
\r
665 /*! Write a given value to a register on MDIO bus (access to the PHY)
\r
666 * This function is looping until PHY gets ready
\r
668 * \param *macb Input. instance of the MACB to use
\r
669 * \param usAddress Input. register to set.
\r
670 * \param usValue Input. value to write.
\r
673 static void vWriteMDIO(volatile avr32_macb_t * macb, unsigned short usAddress, unsigned short usValue)
\r
675 unsigned long status;
\r
677 // initiate transaction : enable management port
\r
678 macb->ncr |= AVR32_MACB_NCR_MPE_MASK;
\r
679 // Write the PHY configuration frame to the MAN register
\r
680 macb->man = (( AVR32_MACB_SOF_MASK & (0x01<<AVR32_MACB_SOF_OFFSET)) // SOF
\r
681 | (2 << AVR32_MACB_CODE_OFFSET) // Code
\r
682 | (1 << AVR32_MACB_RW_OFFSET) // Write operation
\r
683 | ((ETHERNET_CONF_PHY_ADDR & 0x1f) << AVR32_MACB_PHYA_OFFSET) // Phy Add
\r
684 | (usAddress << AVR32_MACB_REGA_OFFSET)) // Reg Add
\r
685 | (usValue & 0xffff); // Data
\r
686 // wait for PHY to be ready
\r
688 status = macb->nsr;
\r
689 } while (!(status & AVR32_MACB_NSR_IDLE_MASK));
\r
690 // disable management port
\r
691 macb->ncr &= ~AVR32_MACB_NCR_MPE_MASK;
\r
694 static Bool prvProbePHY( volatile avr32_macb_t * macb )
\r
696 volatile unsigned long mii_status, phy_ctrl;
\r
697 volatile unsigned long config;
\r
698 unsigned long upper, lower, mode, advertise, lpa;
\r
699 volatile unsigned long physID;
\r
701 // Read Phy Identifier register 1 & 2
\r
702 lower = ulReadMDIO(macb, PHY_PHYSID2);
\r
703 upper = ulReadMDIO(macb, PHY_PHYSID1);
\r
704 // get Phy ID, ignore Revision
\r
705 physID = ((upper << 16) & 0xFFFF0000) | (lower & 0xFFF0);
\r
706 // check if it match config
\r
707 if (physID == ETHERNET_CONF_PHY_ID)
\r
710 mode = ulReadMDIO(macb, PHY_RBR);
\r
711 // set RMII mode if not done
\r
712 if ((mode & RBR_RMII) != RBR_RMII)
\r
714 // force RMII flag if strap options are wrong
\r
716 vWriteMDIO(macb, PHY_RBR, mode);
\r
719 // set advertise register
\r
720 #if ETHERNET_CONF_AN_ENABLE == 1
\r
721 advertise = ADVERTISE_CSMA | ADVERTISE_ALL;
\r
723 advertise = ADVERTISE_CSMA;
\r
724 #if ETHERNET_CONF_USE_100MB
\r
725 #if ETHERNET_CONF_USE_FULL_DUPLEX
\r
726 advertise |= ADVERTISE_100FULL;
\r
728 advertise |= ADVERTISE_100HALF;
\r
731 #if ETHERNET_CONF_USE_FULL_DUPLEX
\r
732 advertise |= ADVERTISE_10FULL;
\r
734 advertise |= ADVERTISE_10HALF;
\r
738 // write advertise register
\r
739 vWriteMDIO(macb, PHY_ADVERTISE, advertise);
\r
740 // read Control register
\r
741 config = ulReadMDIO(macb, PHY_BMCR);
\r
742 // read Phy Control register
\r
743 phy_ctrl = ulReadMDIO(macb, PHY_PHYCR);
\r
744 #if ETHERNET_CONF_AN_ENABLE
\r
745 #if ETHERNET_CONF_AUTO_CROSS_ENABLE
\r
746 // enable Auto MDIX
\r
747 phy_ctrl |= PHYCR_MDIX_EN;
\r
749 // disable Auto MDIX
\r
750 phy_ctrl &= ~PHYCR_MDIX_EN;
\r
751 #if ETHERNET_CONF_CROSSED_LINK
\r
752 // force direct link = Use crossed RJ45 cable
\r
753 phy_ctrl &= ~PHYCR_MDIX_FORCE;
\r
755 // force crossed link = Use direct RJ45 cable
\r
756 phy_ctrl |= PHYCR_MDIX_FORCE;
\r
759 // reset auto-negociation capability
\r
760 config |= (BMCR_ANRESTART | BMCR_ANENABLE);
\r
762 // disable Auto MDIX
\r
763 phy_ctrl &= ~PHYCR_MDIX_EN;
\r
764 #if ETHERNET_CONF_CROSSED_LINK
\r
765 // force direct link = Use crossed RJ45 cable
\r
766 phy_ctrl &= ~PHYCR_MDIX_FORCE;
\r
768 // force crossed link = Use direct RJ45 cable
\r
769 phy_ctrl |= PHYCR_MDIX_FORCE;
\r
772 config &= ~BMCR_ANENABLE;
\r
774 #if ETHERNET_CONF_USE_100MB
\r
775 config |= BMCR_SPEED100;
\r
777 config &= ~BMCR_SPEED100;
\r
779 #if ETHERNET_CONF_USE_FULL_DUPLEX
\r
780 config |= BMCR_FULLDPLX;
\r
782 config &= ~BMCR_FULLDPLX;
\r
785 // update Phy ctrl register
\r
786 vWriteMDIO(macb, PHY_PHYCR, phy_ctrl);
\r
788 // update ctrl register
\r
789 vWriteMDIO(macb, PHY_BMCR, config);
\r
791 // loop while link status isn't OK
\r
793 mii_status = ulReadMDIO(macb, PHY_BMSR);
\r
794 } while (!(mii_status & BMSR_LSTATUS));
\r
796 // read the LPA configuration of the PHY
\r
797 lpa = ulReadMDIO(macb, PHY_LPA);
\r
799 // read the MACB config register
\r
800 config = AVR32_MACB.ncfgr;
\r
803 if ((lpa & advertise) & (LPA_100HALF | LPA_100FULL))
\r
805 config |= AVR32_MACB_SPD_MASK;
\r
809 config &= ~(AVR32_MACB_SPD_MASK);
\r
812 // if FULL DUPLEX needed
\r
813 if ((lpa & advertise) & (LPA_10FULL | LPA_100FULL))
\r
815 config |= AVR32_MACB_FD_MASK;
\r
819 config &= ~(AVR32_MACB_FD_MASK);
\r
822 // write the MACB config register
\r
823 macb->ncfgr = config;
\r
831 void vMACBWaitForInput( unsigned long ulTimeOut )
\r
833 #ifdef FREERTOS_USED
\r
834 // Just wait until we are signled from an ISR that data is available, or
\r
835 // we simply time out.
\r
836 xSemaphoreTake( xSemaphore, ulTimeOut );
\r
839 gpio_clr_gpio_pin(LED0_GPIO);
\r
840 i = ulTimeOut * 1000;
\r
841 // wait for an interrupt to occurs
\r
844 if ( DataToRead == TRUE )
\r
846 // IT occurs, reset interrupt flag
\r
847 portENTER_CRITICAL();
\r
848 DataToRead = FALSE;
\r
849 portEXIT_CRITICAL();
\r
855 gpio_set_gpio_pin(LED0_GPIO);
\r
861 * The MACB ISR. Handles both Tx and Rx complete interrupts.
\r
863 #ifdef FREERTOS_USED
\r
865 __attribute__((naked))
\r
867 #pragma shadow_registers = full // Naked.
\r
871 __attribute__((__interrupt__))
\r
876 void vMACB_ISR( void )
\r
878 // This ISR can cause a context switch, so the first statement must be a
\r
879 // call to the portENTER_SWITCHING_ISR() macro. This must be BEFORE any
\r
880 // variable declarations.
\r
881 portENTER_SWITCHING_ISR();
\r
883 // the return value is used by FreeRTOS to change the context if needed after rete instruction
\r
884 // in standalone use, this value should be ignored
\r
885 prvMACB_ISR_NonNakedBehaviour();
\r
887 // Exit the ISR. If a task was woken by either a character being received
\r
888 // or transmitted then a context switch will occur.
\r
889 portEXIT_SWITCHING_ISR();
\r
891 /*-----------------------------------------------------------*/
\r
894 __attribute__((__noinline__))
\r
896 #pragma optimize = no_inline
\r
898 static long prvMACB_ISR_NonNakedBehaviour( void )
\r
901 // Variable definitions can be made now.
\r
902 volatile unsigned long ulIntStatus, ulEventStatus;
\r
903 long xHigherPriorityTaskWoken = FALSE;
\r
905 // Find the cause of the interrupt.
\r
906 ulIntStatus = AVR32_MACB.isr;
\r
907 ulEventStatus = AVR32_MACB.rsr;
\r
909 if( ( ulIntStatus & AVR32_MACB_IDR_RCOMP_MASK ) || ( ulEventStatus & AVR32_MACB_REC_MASK ) )
\r
911 // A frame has been received, signal the IP task so it can process
\r
912 // the Rx descriptors.
\r
913 portENTER_CRITICAL();
\r
914 #ifdef FREERTOS_USED
\r
915 xSemaphoreGiveFromISR( xSemaphore, &xHigherPriorityTaskWoken );
\r
917 DataToRead = TRUE;
\r
919 portEXIT_CRITICAL();
\r
920 AVR32_MACB.rsr = AVR32_MACB_REC_MASK;
\r
924 if( ulIntStatus & AVR32_MACB_TCOMP_MASK )
\r
926 // A frame has been transmitted. Mark all the buffers used by the
\r
927 // frame just transmitted as free again.
\r
928 vClearMACBTxBuffer();
\r
929 AVR32_MACB.tsr = AVR32_MACB_TSR_COMP_MASK;
\r
933 return ( xHigherPriorityTaskWoken );
\r
938 #if ETHERNET_CONF_USE_PHY_IT
\r
940 * The PHY ISR. Handles Phy interrupts.
\r
942 #ifdef FREERTOS_USED
\r
944 __attribute__((naked))
\r
946 #pragma shadow_registers = full // Naked.
\r
950 __attribute__((__interrupt__))
\r
955 void vPHY_ISR( void )
\r
957 // This ISR can cause a context switch, so the first statement must be a
\r
958 // call to the portENTER_SWITCHING_ISR() macro. This must be BEFORE any
\r
959 // variable declarations.
\r
960 portENTER_SWITCHING_ISR();
\r
962 // the return value is used by FreeRTOS to change the context if needed after rete instruction
\r
963 // in standalone use, this value should be ignored
\r
964 prvPHY_ISR_NonNakedBehaviour();
\r
966 // Exit the ISR. If a task was woken by either a character being received
\r
967 // or transmitted then a context switch will occur.
\r
968 portEXIT_SWITCHING_ISR();
\r
970 /*-----------------------------------------------------------*/
\r
973 __attribute__((__noinline__))
\r
975 #pragma optimize = no_inline
\r
977 static long prvPHY_ISR_NonNakedBehaviour( void )
\r
980 // Variable definitions can be made now.
\r
981 volatile unsigned long ulIntStatus, ulEventStatus;
\r
982 long xSwitchRequired = FALSE;
\r
983 volatile avr32_gpio_t *gpio = &AVR32_GPIO;
\r
984 volatile avr32_gpio_port_t *gpio_port = &gpio->port[MACB_INTERRUPT_PIN/32];
\r
986 // read Phy Interrupt register Status
\r
987 ulIntStatus = ulReadMDIO(&AVR32_MACB, PHY_MISR);
\r
989 // read Phy status register
\r
990 ulEventStatus = ulReadMDIO(&AVR32_MACB, PHY_BMSR);
\r
992 ulEventStatus = ulReadMDIO(&AVR32_MACB, PHY_BMSR);
\r
994 // clear interrupt flag on GPIO
\r
995 gpio_port->ifrc = 1 << (MACB_INTERRUPT_PIN%32);
\r
997 return ( xSwitchRequired );
\r