2 FreeRTOS V7.1.1 - Copyright (C) 2012 Real Time Engineers Ltd.
\r
5 ***************************************************************************
\r
7 * FreeRTOS tutorial books are available in pdf and paperback. *
\r
8 * Complete, revised, and edited pdf reference manuals are also *
\r
11 * Purchasing FreeRTOS documentation will not only help you, by *
\r
12 * ensuring you get running as quickly as possible and with an *
\r
13 * in-depth knowledge of how to use FreeRTOS, it will also help *
\r
14 * the FreeRTOS project to continue with its mission of providing *
\r
15 * professional grade, cross platform, de facto standard solutions *
\r
16 * for microcontrollers - completely free of charge! *
\r
18 * >>> See http://www.FreeRTOS.org/Documentation for details. <<< *
\r
20 * Thank you for using FreeRTOS, and thank you for your support! *
\r
22 ***************************************************************************
\r
25 This file is part of the FreeRTOS distribution.
\r
27 FreeRTOS is free software; you can redistribute it and/or modify it under
\r
28 the terms of the GNU General Public License (version 2) as published by the
\r
29 Free Software Foundation AND MODIFIED BY the FreeRTOS exception.
\r
30 >>>NOTE<<< The modification to the GPL is included to allow you to
\r
31 distribute a combined work that includes FreeRTOS without being obliged to
\r
32 provide the source code for proprietary components outside of the FreeRTOS
\r
33 kernel. FreeRTOS is distributed in the hope that it will be useful, but
\r
34 WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
\r
35 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
\r
36 more details. You should have received a copy of the GNU General Public
\r
37 License and the FreeRTOS license exception along with FreeRTOS; if not it
\r
38 can be viewed here: http://www.freertos.org/a00114.html and also obtained
\r
39 by writing to Richard Barry, contact details for whom are available on the
\r
44 ***************************************************************************
\r
46 * Having a problem? Start by reading the FAQ "My application does *
\r
47 * not run, what could be wrong? *
\r
49 * http://www.FreeRTOS.org/FAQHelp.html *
\r
51 ***************************************************************************
\r
54 http://www.FreeRTOS.org - Documentation, training, latest information,
\r
55 license and contact details.
\r
57 http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
\r
58 including FreeRTOS+Trace - an indispensable productivity tool.
\r
60 Real Time Engineers ltd license FreeRTOS to High Integrity Systems, who sell
\r
61 the code with commercial support, indemnification, and middleware, under
\r
62 the OpenRTOS brand: http://www.OpenRTOS.com. High Integrity Systems also
\r
63 provide a safety engineered and independently SIL3 certified version under
\r
64 the SafeRTOS brand: http://www.SafeRTOS.com.
\r
68 * Interrupt driven driver for the EMAC peripheral. This driver is not
\r
69 * reentrant, re-entrancy is handled by a semaphore at the network interface
\r
77 + Corrected the byte order when writing the MAC address to the MAC.
\r
78 + Support added for MII interfaces. Previously only RMII was supported.
\r
82 + The MII interface is now the default.
\r
83 + Modified the initialisation sequence slightly to allow auto init more
\r
88 + Made the function vClearEMACTxBuffer() more robust by moving the index
\r
89 manipulation into the if() statement. This allows the tx interrupt to
\r
90 execute even when there is no data to handle.
\r
94 + Corrected the Rx frame length mask when obtaining the length from the
\r
99 /* Standard includes. */
\r
100 #include <string.h>
\r
102 /* Scheduler includes. */
\r
103 #include "FreeRTOS.h"
\r
104 #include "semphr.h"
\r
107 /* Demo app includes. */
\r
108 #include "SAM7_EMAC.h"
\r
110 /* Hardware specific includes. */
\r
113 #include "AT91SAM7X256.h"
\r
116 /* USE_RMII_INTERFACE must be defined as 1 to use an RMII interface, or 0
\r
117 to use an MII interface. */
\r
118 #define USE_RMII_INTERFACE 0
\r
121 /* The buffer addresses written into the descriptors must be aligned so the
\r
122 last few bits are zero. These bits have special meaning for the EMAC
\r
123 peripheral and cannot be used as part of the address. */
\r
124 #define emacADDRESS_MASK ( ( unsigned long ) 0xFFFFFFFC )
\r
126 /* Bit used within the address stored in the descriptor to mark the last
\r
127 descriptor in the array. */
\r
128 #define emacRX_WRAP_BIT ( ( unsigned long ) 0x02 )
\r
130 /* Bit used within the Tx descriptor status to indicate whether the
\r
131 descriptor is under the control of the EMAC or the software. */
\r
132 #define emacTX_BUF_USED ( ( unsigned long ) 0x80000000 )
\r
134 /* A short delay is used to wait for a buffer to become available, should
\r
135 one not be immediately available when trying to transmit a frame. */
\r
136 #define emacBUFFER_WAIT_DELAY ( 2 )
\r
137 #define emacMAX_WAIT_CYCLES ( ( portBASE_TYPE ) ( configTICK_RATE_HZ / 40 ) )
\r
139 /* The time to block waiting for input. */
\r
140 #define emacBLOCK_TIME_WAITING_FOR_INPUT ( ( portTickType ) 100 )
\r
142 /* Peripheral setup for the EMAC. */
\r
143 #define emacPERIPHERAL_A_SETUP ( ( unsigned long ) AT91C_PB2_ETX0 ) | \
\r
144 ( ( unsigned long ) AT91C_PB12_ETXER ) | \
\r
145 ( ( unsigned long ) AT91C_PB16_ECOL ) | \
\r
146 ( ( unsigned long ) AT91C_PB11_ETX3 ) | \
\r
147 ( ( unsigned long ) AT91C_PB6_ERX1 ) | \
\r
148 ( ( unsigned long ) AT91C_PB15_ERXDV ) | \
\r
149 ( ( unsigned long ) AT91C_PB13_ERX2 ) | \
\r
150 ( ( unsigned long ) AT91C_PB3_ETX1 ) | \
\r
151 ( ( unsigned long ) AT91C_PB8_EMDC ) | \
\r
152 ( ( unsigned long ) AT91C_PB5_ERX0 ) | \
\r
153 ( ( unsigned long ) AT91C_PB14_ERX3 ) | \
\r
154 ( ( unsigned long ) AT91C_PB4_ECRS_ECRSDV ) | \
\r
155 ( ( unsigned long ) AT91C_PB1_ETXEN ) | \
\r
156 ( ( unsigned long ) AT91C_PB10_ETX2 ) | \
\r
157 ( ( unsigned long ) AT91C_PB0_ETXCK_EREFCK ) | \
\r
158 ( ( unsigned long ) AT91C_PB9_EMDIO ) | \
\r
159 ( ( unsigned long ) AT91C_PB7_ERXER ) | \
\r
160 ( ( unsigned long ) AT91C_PB17_ERXCK );
\r
162 /* Misc defines. */
\r
163 #define emacINTERRUPT_LEVEL ( 5 )
\r
164 #define emacNO_DELAY ( 0 )
\r
165 #define emacTOTAL_FRAME_HEADER_SIZE ( 54 )
\r
166 #define emacPHY_INIT_DELAY ( 5000 / portTICK_RATE_MS )
\r
167 #define emacRESET_KEY ( ( unsigned long ) 0xA5000000 )
\r
168 #define emacRESET_LENGTH ( ( unsigned long ) ( 0x01 << 8 ) )
\r
170 /* The Atmel header file only defines the TX frame length mask. */
\r
171 #define emacRX_LENGTH_FRAME ( 0xfff )
\r
173 /*-----------------------------------------------------------*/
\r
175 /* Buffer written to by the EMAC DMA. Must be aligned as described by the
\r
176 comment above the emacADDRESS_MASK definition. */
\r
177 static volatile char pcRxBuffer[ NB_RX_BUFFERS * ETH_RX_BUFFER_SIZE ] __attribute__ ((aligned (8)));
\r
179 /* Buffer read by the EMAC DMA. Must be aligned as described by the comment
\r
180 above the emacADDRESS_MASK definition. */
\r
181 static char pcTxBuffer[ NB_TX_BUFFERS * ETH_TX_BUFFER_SIZE ] __attribute__ ((aligned (8)));
\r
183 /* Descriptors used to communicate between the program and the EMAC peripheral.
\r
184 These descriptors hold the locations and state of the Rx and Tx buffers. */
\r
185 static volatile AT91S_TxTdDescriptor xTxDescriptors[ NB_TX_BUFFERS ];
\r
186 static volatile AT91S_RxTdDescriptor xRxDescriptors[ NB_RX_BUFFERS ];
\r
188 /* The IP and Ethernet addresses are read from the header files. */
\r
189 const char cMACAddress[ 6 ] = { emacETHADDR0, emacETHADDR1, emacETHADDR2, emacETHADDR3, emacETHADDR4, emacETHADDR5 };
\r
190 const unsigned char ucIPAddress[ 4 ] = { emacIPADDR0, emacIPADDR1, emacIPADDR2, emacIPADDR3 };
\r
192 /*-----------------------------------------------------------*/
\r
194 /* See the header file for descriptions of public functions. */
\r
197 * Prototype for the EMAC interrupt function.
\r
199 void vEMACISR_Wrapper( void ) __attribute__ ((naked));
\r
202 * Initialise both the Tx and Rx descriptors used by the EMAC.
\r
204 static void prvSetupDescriptors(void);
\r
207 * Write our MAC address into the EMAC.
\r
209 static void prvSetupMACAddress( void );
\r
212 * Configure the EMAC and AIC for EMAC interrupts.
\r
214 static void prvSetupEMACInterrupt( void );
\r
217 * Some initialisation functions taken from the Atmel EMAC sample code.
\r
219 static void vReadPHY( unsigned char ucPHYAddress, unsigned char ucAddress, unsigned long *pulValue );
\r
220 static portBASE_TYPE xGetLinkSpeed( void );
\r
221 static portBASE_TYPE prvProbePHY( void );
\r
222 #if USE_RMII_INTERFACE != 1
\r
223 static void vWritePHY( unsigned char ucPHYAddress, unsigned char ucAddress, unsigned long ulValue);
\r
227 /* The semaphore used by the EMAC ISR to wake the EMAC task. */
\r
228 static xSemaphoreHandle xSemaphore = NULL;
\r
230 /* Holds the index to the next buffer from which data will be read. */
\r
231 static volatile unsigned long ulNextRxBuffer = 0;
\r
233 /*-----------------------------------------------------------*/
\r
235 /* See the header file for descriptions of public functions. */
\r
236 long lEMACSend( char *pcFrom, unsigned long ulLength, long lEndOfFrame )
\r
238 static unsigned portBASE_TYPE uxTxBufferIndex = 0;
\r
239 portBASE_TYPE xWaitCycles = 0;
\r
240 long lReturn = pdPASS;
\r
242 unsigned long ulLastBuffer, ulDataBuffered = 0, ulDataRemainingToSend, ulLengthToSend;
\r
244 /* If the length of data to be transmitted is greater than each individual
\r
245 transmit buffer then the data will be split into more than one buffer.
\r
246 Loop until the entire length has been buffered. */
\r
247 while( ulDataBuffered < ulLength )
\r
249 /* Is a buffer available? */
\r
250 while( !( xTxDescriptors[ uxTxBufferIndex ].U_Status.status & AT91C_TRANSMIT_OK ) )
\r
252 /* There is no room to write the Tx data to the Tx buffer. Wait a
\r
253 short while, then try again. */
\r
255 if( xWaitCycles > emacMAX_WAIT_CYCLES )
\r
263 vTaskDelay( emacBUFFER_WAIT_DELAY );
\r
267 /* lReturn will only be pdPASS if a buffer is available. */
\r
268 if( lReturn == pdPASS )
\r
270 portENTER_CRITICAL();
\r
272 /* Get the address of the buffer from the descriptor, then copy
\r
273 the data into the buffer. */
\r
274 pcBuffer = ( char * ) xTxDescriptors[ uxTxBufferIndex ].addr;
\r
276 /* How much can we write to the buffer? */
\r
277 ulDataRemainingToSend = ulLength - ulDataBuffered;
\r
278 if( ulDataRemainingToSend <= ETH_TX_BUFFER_SIZE )
\r
280 /* We can write all the remaining bytes. */
\r
281 ulLengthToSend = ulDataRemainingToSend;
\r
285 /* We can not write more than ETH_TX_BUFFER_SIZE in one go. */
\r
286 ulLengthToSend = ETH_TX_BUFFER_SIZE;
\r
289 /* Copy the data into the buffer. */
\r
290 memcpy( ( void * ) pcBuffer, ( void * ) &( pcFrom[ ulDataBuffered ] ), ulLengthToSend );
\r
291 ulDataBuffered += ulLengthToSend;
\r
293 /* Is this the last data for the frame? */
\r
294 if( lEndOfFrame && ( ulDataBuffered >= ulLength ) )
\r
296 /* No more data remains for this frame so we can start the
\r
298 ulLastBuffer = AT91C_LAST_BUFFER;
\r
302 /* More data to come for this frame. */
\r
306 /* Fill out the necessary in the descriptor to get the data sent,
\r
307 then move to the next descriptor, wrapping if necessary. */
\r
308 if( uxTxBufferIndex >= ( NB_TX_BUFFERS - 1 ) )
\r
310 xTxDescriptors[ uxTxBufferIndex ].U_Status.status = ( ulLengthToSend & ( unsigned long ) AT91C_LENGTH_FRAME )
\r
312 | AT91C_TRANSMIT_WRAP;
\r
313 uxTxBufferIndex = 0;
\r
317 xTxDescriptors[ uxTxBufferIndex ].U_Status.status = ( ulLengthToSend & ( unsigned long ) AT91C_LENGTH_FRAME )
\r
322 /* If this is the last buffer to be sent for this frame we can
\r
323 start the transmission. */
\r
326 AT91C_BASE_EMAC->EMAC_NCR |= AT91C_EMAC_TSTART;
\r
329 portEXIT_CRITICAL();
\r
339 /*-----------------------------------------------------------*/
\r
341 /* See the header file for descriptions of public functions. */
\r
342 unsigned long ulEMACInputLength( void )
\r
344 register unsigned long ulIndex, ulLength = 0;
\r
346 /* Skip any fragments. We are looking for the first buffer that contains
\r
347 data and has the SOF (start of frame) bit set. */
\r
348 while( ( xRxDescriptors[ ulNextRxBuffer ].addr & AT91C_OWNERSHIP_BIT ) && !( xRxDescriptors[ ulNextRxBuffer ].U_Status.status & AT91C_SOF ) )
\r
350 /* Ignoring this buffer. Mark it as free again. */
\r
351 xRxDescriptors[ ulNextRxBuffer ].addr &= ~( AT91C_OWNERSHIP_BIT );
\r
353 if( ulNextRxBuffer >= NB_RX_BUFFERS )
\r
355 ulNextRxBuffer = 0;
\r
359 /* We are going to walk through the descriptors that make up this frame,
\r
360 but don't want to alter ulNextRxBuffer as this would prevent vEMACRead()
\r
361 from finding the data. Therefore use a copy of ulNextRxBuffer instead. */
\r
362 ulIndex = ulNextRxBuffer;
\r
364 /* Walk through the descriptors until we find the last buffer for this
\r
365 frame. The last buffer will give us the length of the entire frame. */
\r
366 while( ( xRxDescriptors[ ulIndex ].addr & AT91C_OWNERSHIP_BIT ) && !ulLength )
\r
368 ulLength = xRxDescriptors[ ulIndex ].U_Status.status & emacRX_LENGTH_FRAME;
\r
370 /* Increment to the next buffer, wrapping if necessary. */
\r
372 if( ulIndex >= NB_RX_BUFFERS )
\r
380 /*-----------------------------------------------------------*/
\r
382 /* See the header file for descriptions of public functions. */
\r
383 void vEMACRead( char *pcTo, unsigned long ulSectionLength, unsigned long ulTotalFrameLength )
\r
385 static unsigned long ulSectionBytesReadSoFar = 0, ulBufferPosition = 0, ulFameBytesReadSoFar = 0;
\r
386 static char *pcSource;
\r
387 register unsigned long ulBytesRemainingInBuffer, ulRemainingSectionBytes;
\r
389 /* Read ulSectionLength bytes from the Rx buffers. This is not necessarily any
\r
390 correspondence between the length of our Rx buffers, and the length of the
\r
391 data we are returning or the length of the data being requested. Therefore,
\r
392 between calls we have to remember not only which buffer we are currently
\r
393 processing, but our position within that buffer. This would be greatly
\r
394 simplified if PBUF_POOL_BUFSIZE could be guaranteed to be greater than
\r
395 the size of each Rx buffer, and that memory fragmentation did not occur.
\r
397 This function should only be called after a call to ulEMACInputLength().
\r
398 This will ensure ulNextRxBuffer is set to the correct buffer. */
\r
402 /* vEMACRead is called with pcTo set to NULL to indicate that we are about
\r
403 to read a new frame. Any fragments remaining in the frame we were
\r
404 processing during the last call should be dropped. */
\r
407 /* How many bytes are indicated as being in this buffer? If none then
\r
408 the buffer is completely full and the frame is contained within more
\r
409 than one buffer. */
\r
411 /* Reset our state variables ready for the next read from this buffer. */
\r
412 pcSource = ( char * )( xRxDescriptors[ ulNextRxBuffer ].addr & emacADDRESS_MASK );
\r
413 ulFameBytesReadSoFar = ( unsigned long ) 0;
\r
414 ulBufferPosition = ( unsigned long ) 0;
\r
418 /* Loop until we have obtained the required amount of data. */
\r
419 ulSectionBytesReadSoFar = 0;
\r
420 while( ulSectionBytesReadSoFar < ulSectionLength )
\r
422 /* We may have already read some data from this buffer. How much
\r
423 data remains in the buffer? */
\r
424 ulBytesRemainingInBuffer = ( ETH_RX_BUFFER_SIZE - ulBufferPosition );
\r
426 /* How many more bytes do we need to read before we have the
\r
427 required amount of data? */
\r
428 ulRemainingSectionBytes = ulSectionLength - ulSectionBytesReadSoFar;
\r
430 /* Do we want more data than remains in the buffer? */
\r
431 if( ulRemainingSectionBytes > ulBytesRemainingInBuffer )
\r
433 /* We want more data than remains in the buffer so we can
\r
434 write the remains of the buffer to the destination, then move
\r
435 onto the next buffer to get the rest. */
\r
436 memcpy( &( pcTo[ ulSectionBytesReadSoFar ] ), &( pcSource[ ulBufferPosition ] ), ulBytesRemainingInBuffer );
\r
437 ulSectionBytesReadSoFar += ulBytesRemainingInBuffer;
\r
438 ulFameBytesReadSoFar += ulBytesRemainingInBuffer;
\r
440 /* Mark the buffer as free again. */
\r
441 xRxDescriptors[ ulNextRxBuffer ].addr &= ~( AT91C_OWNERSHIP_BIT );
\r
443 /* Move onto the next buffer. */
\r
445 if( ulNextRxBuffer >= NB_RX_BUFFERS )
\r
447 ulNextRxBuffer = ( unsigned long ) 0;
\r
450 /* Reset the variables for the new buffer. */
\r
451 pcSource = ( char * )( xRxDescriptors[ ulNextRxBuffer ].addr & emacADDRESS_MASK );
\r
452 ulBufferPosition = ( unsigned long ) 0;
\r
456 /* We have enough data in this buffer to send back. Read out
\r
457 enough data and remember how far we read up to. */
\r
458 memcpy( &( pcTo[ ulSectionBytesReadSoFar ] ), &( pcSource[ ulBufferPosition ] ), ulRemainingSectionBytes );
\r
460 /* There may be more data in this buffer yet. Increment our
\r
461 position in this buffer past the data we have just read. */
\r
462 ulBufferPosition += ulRemainingSectionBytes;
\r
463 ulSectionBytesReadSoFar += ulRemainingSectionBytes;
\r
464 ulFameBytesReadSoFar += ulRemainingSectionBytes;
\r
466 /* Have we now finished with this buffer? */
\r
467 if( ( ulBufferPosition >= ETH_RX_BUFFER_SIZE ) || ( ulFameBytesReadSoFar >= ulTotalFrameLength ) )
\r
469 /* Mark the buffer as free again. */
\r
470 xRxDescriptors[ ulNextRxBuffer ].addr &= ~( AT91C_OWNERSHIP_BIT );
\r
472 /* Move onto the next buffer. */
\r
474 if( ulNextRxBuffer >= NB_RX_BUFFERS )
\r
476 ulNextRxBuffer = 0;
\r
479 pcSource = ( char * )( xRxDescriptors[ ulNextRxBuffer ].addr & emacADDRESS_MASK );
\r
480 ulBufferPosition = 0;
\r
486 /*-----------------------------------------------------------*/
\r
488 /* See the header file for descriptions of public functions. */
\r
489 xSemaphoreHandle xEMACInit( void )
\r
491 /* Code supplied by Atmel -------------------------------*/
\r
493 /* Disable pull up on RXDV => PHY normal mode (not in test mode),
\r
494 PHY has internal pull down. */
\r
495 AT91C_BASE_PIOB->PIO_PPUDR = 1 << 15;
\r
497 #if USE_RMII_INTERFACE != 1
\r
498 /* PHY has internal pull down : set MII mode. */
\r
499 AT91C_BASE_PIOB->PIO_PPUDR = 1 << 16;
\r
502 /* Clear PB18 <=> PHY powerdown. */
\r
503 AT91C_BASE_PIOB->PIO_PER = 1 << 18;
\r
504 AT91C_BASE_PIOB->PIO_OER = 1 << 18;
\r
505 AT91C_BASE_PIOB->PIO_CODR = 1 << 18;
\r
507 /* After PHY power up, hardware reset. */
\r
508 AT91C_BASE_RSTC->RSTC_RMR = emacRESET_KEY | emacRESET_LENGTH;
\r
509 AT91C_BASE_RSTC->RSTC_RCR = emacRESET_KEY | AT91C_RSTC_EXTRST;
\r
511 /* Wait for hardware reset end. */
\r
512 while( !( AT91C_BASE_RSTC->RSTC_RSR & AT91C_RSTC_NRSTL ) )
\r
514 __asm volatile ( "NOP" );
\r
516 __asm volatile ( "NOP" );
\r
518 /* Setup the pins. */
\r
519 AT91C_BASE_PIOB->PIO_ASR = emacPERIPHERAL_A_SETUP;
\r
520 AT91C_BASE_PIOB->PIO_PDR = emacPERIPHERAL_A_SETUP;
\r
522 /* Enable com between EMAC PHY.
\r
524 Enable management port. */
\r
525 AT91C_BASE_EMAC->EMAC_NCR |= AT91C_EMAC_MPE;
\r
527 /* MDC = MCK/32. */
\r
528 AT91C_BASE_EMAC->EMAC_NCFGR |= ( 2 ) << 10;
\r
530 /* Wait for PHY auto init end (rather crude delay!). */
\r
531 vTaskDelay( emacPHY_INIT_DELAY );
\r
533 /* PHY configuration. */
\r
534 #if USE_RMII_INTERFACE != 1
\r
536 unsigned long ulControl;
\r
538 /* PHY has internal pull down : disable MII isolate. */
\r
539 vReadPHY( AT91C_PHY_ADDR, MII_BMCR, &ulControl );
\r
540 vReadPHY( AT91C_PHY_ADDR, MII_BMCR, &ulControl );
\r
541 ulControl &= ~BMCR_ISOLATE;
\r
542 vWritePHY( AT91C_PHY_ADDR, MII_BMCR, ulControl );
\r
546 /* Disable management port again. */
\r
547 AT91C_BASE_EMAC->EMAC_NCR &= ~AT91C_EMAC_MPE;
\r
549 #if USE_RMII_INTERFACE != 1
\r
550 /* Enable EMAC in MII mode, enable clock ERXCK and ETXCK. */
\r
551 AT91C_BASE_EMAC->EMAC_USRIO = AT91C_EMAC_CLKEN ;
\r
553 /* Enable EMAC in RMII mode, enable RMII clock (50MHz from oscillator
\r
555 AT91C_BASE_EMAC->EMAC_USRIO = AT91C_EMAC_RMII | AT91C_EMAC_CLKEN ;
\r
558 /* End of code supplied by Atmel ------------------------*/
\r
560 /* Setup the buffers and descriptors. */
\r
561 prvSetupDescriptors();
\r
563 /* Load our MAC address into the EMAC. */
\r
564 prvSetupMACAddress();
\r
566 /* Are we connected? */
\r
567 if( prvProbePHY() )
\r
569 /* Enable the interrupt! */
\r
570 portENTER_CRITICAL();
\r
572 prvSetupEMACInterrupt();
\r
573 vPassEMACSemaphore( xSemaphore );
\r
575 portEXIT_CRITICAL();
\r
580 /*-----------------------------------------------------------*/
\r
582 /* See the header file for descriptions of public functions. */
\r
583 void vClearEMACTxBuffer( void )
\r
585 static unsigned portBASE_TYPE uxNextBufferToClear = 0;
\r
587 /* Called on Tx interrupt events to reset the AT91C_TRANSMIT_OK bit in each
\r
588 Tx buffer within the frame just transmitted. This marks all the buffers
\r
589 as available again.
\r
591 The first buffer in the frame should have the bit set automatically. */
\r
592 if( xTxDescriptors[ uxNextBufferToClear ].U_Status.status & AT91C_TRANSMIT_OK )
\r
594 /* Loop through the other buffers in the frame. */
\r
595 while( !( xTxDescriptors[ uxNextBufferToClear ].U_Status.status & AT91C_LAST_BUFFER ) )
\r
597 uxNextBufferToClear++;
\r
599 if( uxNextBufferToClear >= NB_TX_BUFFERS )
\r
601 uxNextBufferToClear = 0;
\r
604 xTxDescriptors[ uxNextBufferToClear ].U_Status.status |= AT91C_TRANSMIT_OK;
\r
607 /* Start with the next buffer the next time a Tx interrupt is called. */
\r
608 uxNextBufferToClear++;
\r
610 /* Do we need to wrap back to the first buffer? */
\r
611 if( uxNextBufferToClear >= NB_TX_BUFFERS )
\r
613 uxNextBufferToClear = 0;
\r
617 /*-----------------------------------------------------------*/
\r
619 static void prvSetupDescriptors(void)
\r
621 unsigned portBASE_TYPE xIndex;
\r
622 unsigned long ulAddress;
\r
624 /* Initialise xRxDescriptors descriptor. */
\r
625 for( xIndex = 0; xIndex < NB_RX_BUFFERS; ++xIndex )
\r
627 /* Calculate the address of the nth buffer within the array. */
\r
628 ulAddress = ( unsigned long )( pcRxBuffer + ( xIndex * ETH_RX_BUFFER_SIZE ) );
\r
630 /* Write the buffer address into the descriptor. The DMA will place
\r
631 the data at this address when this descriptor is being used. Mask off
\r
632 the bottom bits of the address as these have special meaning. */
\r
633 xRxDescriptors[ xIndex ].addr = ulAddress & emacADDRESS_MASK;
\r
636 /* The last buffer has the wrap bit set so the EMAC knows to wrap back
\r
637 to the first buffer. */
\r
638 xRxDescriptors[ NB_RX_BUFFERS - 1 ].addr |= emacRX_WRAP_BIT;
\r
640 /* Initialise xTxDescriptors. */
\r
641 for( xIndex = 0; xIndex < NB_TX_BUFFERS; ++xIndex )
\r
643 /* Calculate the address of the nth buffer within the array. */
\r
644 ulAddress = ( unsigned long )( pcTxBuffer + ( xIndex * ETH_TX_BUFFER_SIZE ) );
\r
646 /* Write the buffer address into the descriptor. The DMA will read
\r
647 data from here when the descriptor is being used. */
\r
648 xTxDescriptors[ xIndex ].addr = ulAddress & emacADDRESS_MASK;
\r
649 xTxDescriptors[ xIndex ].U_Status.status = AT91C_TRANSMIT_OK;
\r
652 /* The last buffer has the wrap bit set so the EMAC knows to wrap back
\r
653 to the first buffer. */
\r
654 xTxDescriptors[ NB_TX_BUFFERS - 1 ].U_Status.status = AT91C_TRANSMIT_WRAP | AT91C_TRANSMIT_OK;
\r
656 /* Tell the EMAC where to find the descriptors. */
\r
657 AT91C_BASE_EMAC->EMAC_RBQP = ( unsigned long ) xRxDescriptors;
\r
658 AT91C_BASE_EMAC->EMAC_TBQP = ( unsigned long ) xTxDescriptors;
\r
660 /* Clear all the bits in the receive status register. */
\r
661 AT91C_BASE_EMAC->EMAC_RSR = ( AT91C_EMAC_OVR | AT91C_EMAC_REC | AT91C_EMAC_BNA );
\r
663 /* Enable the copy of data into the buffers, ignore broadcasts,
\r
664 and don't copy FCS. */
\r
665 AT91C_BASE_EMAC->EMAC_NCFGR |= ( AT91C_EMAC_CAF | AT91C_EMAC_NBC | AT91C_EMAC_DRFCS);
\r
667 /* Enable Rx and Tx, plus the stats register. */
\r
668 AT91C_BASE_EMAC->EMAC_NCR |= ( AT91C_EMAC_TE | AT91C_EMAC_RE | AT91C_EMAC_WESTAT );
\r
670 /*-----------------------------------------------------------*/
\r
672 static void prvSetupMACAddress( void )
\r
674 /* Must be written SA1L then SA1H. */
\r
675 AT91C_BASE_EMAC->EMAC_SA1L = ( ( unsigned long ) cMACAddress[ 3 ] << 24 ) |
\r
676 ( ( unsigned long ) cMACAddress[ 2 ] << 16 ) |
\r
677 ( ( unsigned long ) cMACAddress[ 1 ] << 8 ) |
\r
680 AT91C_BASE_EMAC->EMAC_SA1H = ( ( unsigned long ) cMACAddress[ 5 ] << 8 ) |
\r
683 /*-----------------------------------------------------------*/
\r
685 static void prvSetupEMACInterrupt( void )
\r
687 /* Create the semaphore used to trigger the EMAC task. */
\r
688 vSemaphoreCreateBinary( xSemaphore );
\r
691 /* We start by 'taking' the semaphore so the ISR can 'give' it when the
\r
692 first interrupt occurs. */
\r
693 xSemaphoreTake( xSemaphore, emacNO_DELAY );
\r
694 portENTER_CRITICAL();
\r
696 /* We want to interrupt on Rx and Tx events. */
\r
697 AT91C_BASE_EMAC->EMAC_IER = AT91C_EMAC_RCOMP | AT91C_EMAC_TCOMP;
\r
699 /* Enable the interrupts in the AIC. */
\r
700 AT91F_AIC_ConfigureIt( AT91C_ID_EMAC, emacINTERRUPT_LEVEL, AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL, ( void (*)( void ) ) vEMACISR_Wrapper );
\r
701 AT91C_BASE_AIC->AIC_IECR = 0x1 << AT91C_ID_EMAC;
\r
703 portEXIT_CRITICAL();
\r
712 * The following functions are initialisation functions taken from the Atmel
\r
713 * EMAC sample code.
\r
717 static portBASE_TYPE prvProbePHY( void )
\r
719 unsigned long ulPHYId1, ulPHYId2, ulStatus;
\r
720 portBASE_TYPE xReturn = pdPASS;
\r
722 /* Code supplied by Atmel (reformatted) -----------------*/
\r
724 /* Enable management port */
\r
725 AT91C_BASE_EMAC->EMAC_NCR |= AT91C_EMAC_MPE;
\r
726 AT91C_BASE_EMAC->EMAC_NCFGR |= ( 2 ) << 10;
\r
728 /* Read the PHY ID. */
\r
729 vReadPHY( AT91C_PHY_ADDR, MII_PHYSID1, &ulPHYId1 );
\r
730 vReadPHY(AT91C_PHY_ADDR, MII_PHYSID2, &ulPHYId2 );
\r
735 Bits 3:0 Revision Number Four bit manufacturer?s revision number.
\r
736 0001 stands for Rev. A, etc.
\r
738 if( ( ( ulPHYId1 << 16 ) | ( ulPHYId2 & 0xfff0 ) ) != MII_DM9161_ID )
\r
740 /* Did not expect this ID. */
\r
745 ulStatus = xGetLinkSpeed();
\r
747 if( ulStatus != pdPASS )
\r
753 /* Disable management port */
\r
754 AT91C_BASE_EMAC->EMAC_NCR &= ~AT91C_EMAC_MPE;
\r
756 /* End of code supplied by Atmel ------------------------*/
\r
760 /*-----------------------------------------------------------*/
\r
762 static void vReadPHY( unsigned char ucPHYAddress, unsigned char ucAddress, unsigned long *pulValue )
\r
764 /* Code supplied by Atmel (reformatted) ----------------------*/
\r
766 AT91C_BASE_EMAC->EMAC_MAN = (AT91C_EMAC_SOF & (0x01<<30))
\r
767 | (2 << 16) | (2 << 28)
\r
768 | ((ucPHYAddress & 0x1f) << 23)
\r
769 | (ucAddress << 18);
\r
771 /* Wait until IDLE bit in Network Status register is cleared. */
\r
772 while( !( AT91C_BASE_EMAC->EMAC_NSR & AT91C_EMAC_IDLE ) )
\r
777 *pulValue = ( AT91C_BASE_EMAC->EMAC_MAN & 0x0000ffff );
\r
779 /* End of code supplied by Atmel ------------------------*/
\r
781 /*-----------------------------------------------------------*/
\r
783 #if USE_RMII_INTERFACE != 1
\r
784 static void vWritePHY( unsigned char ucPHYAddress, unsigned char ucAddress, unsigned long ulValue )
\r
786 /* Code supplied by Atmel (reformatted) ----------------------*/
\r
788 AT91C_BASE_EMAC->EMAC_MAN = (( AT91C_EMAC_SOF & (0x01<<30))
\r
789 | (2 << 16) | (1 << 28)
\r
790 | ((ucPHYAddress & 0x1f) << 23)
\r
791 | (ucAddress << 18))
\r
792 | (ulValue & 0xffff);
\r
794 /* Wait until IDLE bit in Network Status register is cleared */
\r
795 while( !( AT91C_BASE_EMAC->EMAC_NSR & AT91C_EMAC_IDLE ) )
\r
800 /* End of code supplied by Atmel ------------------------*/
\r
803 /*-----------------------------------------------------------*/
\r
805 static portBASE_TYPE xGetLinkSpeed( void )
\r
807 unsigned long ulBMSR, ulBMCR, ulLPA, ulMACCfg, ulSpeed, ulDuplex;
\r
809 /* Code supplied by Atmel (reformatted) -----------------*/
\r
811 /* Link status is latched, so read twice to get current value */
\r
812 vReadPHY(AT91C_PHY_ADDR, MII_BMSR, &ulBMSR);
\r
813 vReadPHY(AT91C_PHY_ADDR, MII_BMSR, &ulBMSR);
\r
815 if( !( ulBMSR & BMSR_LSTATUS ) )
\r
821 vReadPHY(AT91C_PHY_ADDR, MII_BMCR, &ulBMCR);
\r
822 if (ulBMCR & BMCR_ANENABLE)
\r
824 /* AutoNegotiation is enabled. */
\r
825 if (!(ulBMSR & BMSR_ANEGCOMPLETE))
\r
827 /* Auto-negotitation in progress. */
\r
831 vReadPHY(AT91C_PHY_ADDR, MII_LPA, &ulLPA);
\r
832 if( ( ulLPA & LPA_100FULL ) || ( ulLPA & LPA_100HALF ) )
\r
834 ulSpeed = SPEED_100;
\r
838 ulSpeed = SPEED_10;
\r
841 if( ( ulLPA & LPA_100FULL ) || ( ulLPA & LPA_10FULL ) )
\r
843 ulDuplex = DUPLEX_FULL;
\r
847 ulDuplex = DUPLEX_HALF;
\r
852 ulSpeed = ( ulBMCR & BMCR_SPEED100 ) ? SPEED_100 : SPEED_10;
\r
853 ulDuplex = ( ulBMCR & BMCR_FULLDPLX ) ? DUPLEX_FULL : DUPLEX_HALF;
\r
856 /* Update the MAC */
\r
857 ulMACCfg = AT91C_BASE_EMAC->EMAC_NCFGR & ~( AT91C_EMAC_SPD | AT91C_EMAC_FD );
\r
858 if( ulSpeed == SPEED_100 )
\r
860 if( ulDuplex == DUPLEX_FULL )
\r
862 /* 100 Full Duplex */
\r
863 AT91C_BASE_EMAC->EMAC_NCFGR = ulMACCfg | AT91C_EMAC_SPD | AT91C_EMAC_FD;
\r
867 /* 100 Half Duplex */
\r
868 AT91C_BASE_EMAC->EMAC_NCFGR = ulMACCfg | AT91C_EMAC_SPD;
\r
873 if (ulDuplex == DUPLEX_FULL)
\r
875 /* 10 Full Duplex */
\r
876 AT91C_BASE_EMAC->EMAC_NCFGR = ulMACCfg | AT91C_EMAC_FD;
\r
879 { /* 10 Half Duplex */
\r
880 AT91C_BASE_EMAC->EMAC_NCFGR = ulMACCfg;
\r
884 /* End of code supplied by Atmel ------------------------*/
\r
888 /*-----------------------------------------------------------*/
\r
890 void vEMACWaitForInput( void )
\r
892 /* Just wait until we are signled from an ISR that data is available, or
\r
893 we simply time out. */
\r
894 xSemaphoreTake( xSemaphore, emacBLOCK_TIME_WAITING_FOR_INPUT );
\r