2 FreeRTOS V7.4.2 - Copyright (C) 2013 Real Time Engineers Ltd.
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4 FEATURES AND PORTS ARE ADDED TO FREERTOS ALL THE TIME. PLEASE VISIT
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5 http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
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7 ***************************************************************************
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9 * FreeRTOS tutorial books are available in pdf and paperback. *
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10 * Complete, revised, and edited pdf reference manuals are also *
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13 * Purchasing FreeRTOS documentation will not only help you, by *
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14 * ensuring you get running as quickly as possible and with an *
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15 * in-depth knowledge of how to use FreeRTOS, it will also help *
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16 * the FreeRTOS project to continue with its mission of providing *
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17 * professional grade, cross platform, de facto standard solutions *
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18 * for microcontrollers - completely free of charge! *
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20 * >>> See http://www.FreeRTOS.org/Documentation for details. <<< *
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22 * Thank you for using FreeRTOS, and thank you for your support! *
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24 ***************************************************************************
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27 This file is part of the FreeRTOS distribution.
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29 FreeRTOS is free software; you can redistribute it and/or modify it under
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30 the terms of the GNU General Public License (version 2) as published by the
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31 Free Software Foundation AND MODIFIED BY the FreeRTOS exception.
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33 >>>>>>NOTE<<<<<< The modification to the GPL is included to allow you to
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34 distribute a combined work that includes FreeRTOS without being obliged to
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35 provide the source code for proprietary components outside of the FreeRTOS
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38 FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
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39 WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
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40 FOR A PARTICULAR PURPOSE. See the GNU General Public License for more
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41 details. You should have received a copy of the GNU General Public License
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42 and the FreeRTOS license exception along with FreeRTOS; if not it can be
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43 viewed here: http://www.freertos.org/a00114.html and also obtained by
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44 writing to Real Time Engineers Ltd., contact details for whom are available
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45 on the FreeRTOS WEB site.
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49 ***************************************************************************
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51 * Having a problem? Start by reading the FAQ "My application does *
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52 * not run, what could be wrong?" *
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54 * http://www.FreeRTOS.org/FAQHelp.html *
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56 ***************************************************************************
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59 http://www.FreeRTOS.org - Documentation, books, training, latest versions,
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60 license and Real Time Engineers Ltd. contact details.
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62 http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
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63 including FreeRTOS+Trace - an indispensable productivity tool, and our new
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64 fully thread aware and reentrant UDP/IP stack.
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66 http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High
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67 Integrity Systems, who sell the code with commercial support,
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68 indemnification and middleware, under the OpenRTOS brand.
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70 http://www.SafeRTOS.com - High Integrity Systems also provide a safety
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71 engineered and independently SIL3 certified version for use in safety and
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72 mission critical applications that require provable dependability.
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76 * Interrupt driven driver for the EMAC peripheral. This driver is not
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77 * reentrant, re-entrancy is handled by a semaphore at the network interface
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85 + Corrected the byte order when writing the MAC address to the MAC.
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86 + Support added for MII interfaces. Previously only RMII was supported.
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90 + The MII interface is now the default.
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91 + Modified the initialisation sequence slightly to allow auto init more
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96 + Made the function vClearEMACTxBuffer() more robust by moving the index
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97 manipulation into the if() statement. This allows the tx interrupt to
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98 execute even when there is no data to handle.
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100 Changes from V4.0.4
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102 + Corrected the Rx frame length mask when obtaining the length from the
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107 /* Standard includes. */
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108 #include <string.h>
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110 /* Scheduler includes. */
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111 #include "FreeRTOS.h"
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112 #include "semphr.h"
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115 /* Demo app includes. */
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116 #include "SAM7_EMAC.h"
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118 /* Hardware specific includes. */
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121 #include "AT91SAM7X256.h"
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124 /* USE_RMII_INTERFACE must be defined as 1 to use an RMII interface, or 0
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125 to use an MII interface. */
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126 #define USE_RMII_INTERFACE 0
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129 /* The buffer addresses written into the descriptors must be aligned so the
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130 last few bits are zero. These bits have special meaning for the EMAC
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131 peripheral and cannot be used as part of the address. */
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132 #define emacADDRESS_MASK ( ( unsigned long ) 0xFFFFFFFC )
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134 /* Bit used within the address stored in the descriptor to mark the last
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135 descriptor in the array. */
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136 #define emacRX_WRAP_BIT ( ( unsigned long ) 0x02 )
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138 /* Bit used within the Tx descriptor status to indicate whether the
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139 descriptor is under the control of the EMAC or the software. */
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140 #define emacTX_BUF_USED ( ( unsigned long ) 0x80000000 )
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142 /* A short delay is used to wait for a buffer to become available, should
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143 one not be immediately available when trying to transmit a frame. */
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144 #define emacBUFFER_WAIT_DELAY ( 2 )
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145 #define emacMAX_WAIT_CYCLES ( ( portBASE_TYPE ) ( configTICK_RATE_HZ / 40 ) )
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147 /* The time to block waiting for input. */
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148 #define emacBLOCK_TIME_WAITING_FOR_INPUT ( ( portTickType ) 100 )
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150 /* Peripheral setup for the EMAC. */
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151 #define emacPERIPHERAL_A_SETUP ( ( unsigned long ) AT91C_PB2_ETX0 ) | \
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152 ( ( unsigned long ) AT91C_PB12_ETXER ) | \
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153 ( ( unsigned long ) AT91C_PB16_ECOL ) | \
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154 ( ( unsigned long ) AT91C_PB11_ETX3 ) | \
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155 ( ( unsigned long ) AT91C_PB6_ERX1 ) | \
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156 ( ( unsigned long ) AT91C_PB15_ERXDV ) | \
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157 ( ( unsigned long ) AT91C_PB13_ERX2 ) | \
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158 ( ( unsigned long ) AT91C_PB3_ETX1 ) | \
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159 ( ( unsigned long ) AT91C_PB8_EMDC ) | \
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160 ( ( unsigned long ) AT91C_PB5_ERX0 ) | \
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161 ( ( unsigned long ) AT91C_PB14_ERX3 ) | \
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162 ( ( unsigned long ) AT91C_PB4_ECRS_ECRSDV ) | \
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163 ( ( unsigned long ) AT91C_PB1_ETXEN ) | \
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164 ( ( unsigned long ) AT91C_PB10_ETX2 ) | \
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165 ( ( unsigned long ) AT91C_PB0_ETXCK_EREFCK ) | \
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166 ( ( unsigned long ) AT91C_PB9_EMDIO ) | \
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167 ( ( unsigned long ) AT91C_PB7_ERXER ) | \
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168 ( ( unsigned long ) AT91C_PB17_ERXCK );
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170 /* Misc defines. */
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171 #define emacINTERRUPT_LEVEL ( 5 )
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172 #define emacNO_DELAY ( 0 )
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173 #define emacTOTAL_FRAME_HEADER_SIZE ( 54 )
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174 #define emacPHY_INIT_DELAY ( 5000 / portTICK_RATE_MS )
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175 #define emacRESET_KEY ( ( unsigned long ) 0xA5000000 )
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176 #define emacRESET_LENGTH ( ( unsigned long ) ( 0x01 << 8 ) )
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178 /* The Atmel header file only defines the TX frame length mask. */
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179 #define emacRX_LENGTH_FRAME ( 0xfff )
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181 /*-----------------------------------------------------------*/
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183 /* Buffer written to by the EMAC DMA. Must be aligned as described by the
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184 comment above the emacADDRESS_MASK definition. */
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185 static volatile char pcRxBuffer[ NB_RX_BUFFERS * ETH_RX_BUFFER_SIZE ] __attribute__ ((aligned (8)));
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187 /* Buffer read by the EMAC DMA. Must be aligned as described by the comment
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188 above the emacADDRESS_MASK definition. */
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189 static char pcTxBuffer[ NB_TX_BUFFERS * ETH_TX_BUFFER_SIZE ] __attribute__ ((aligned (8)));
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191 /* Descriptors used to communicate between the program and the EMAC peripheral.
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192 These descriptors hold the locations and state of the Rx and Tx buffers. */
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193 static volatile AT91S_TxTdDescriptor xTxDescriptors[ NB_TX_BUFFERS ];
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194 static volatile AT91S_RxTdDescriptor xRxDescriptors[ NB_RX_BUFFERS ];
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196 /* The IP and Ethernet addresses are read from the header files. */
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197 const char cMACAddress[ 6 ] = { emacETHADDR0, emacETHADDR1, emacETHADDR2, emacETHADDR3, emacETHADDR4, emacETHADDR5 };
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198 const unsigned char ucIPAddress[ 4 ] = { emacIPADDR0, emacIPADDR1, emacIPADDR2, emacIPADDR3 };
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200 /*-----------------------------------------------------------*/
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202 /* See the header file for descriptions of public functions. */
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205 * Prototype for the EMAC interrupt function.
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207 void vEMACISR_Wrapper( void ) __attribute__ ((naked));
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210 * Initialise both the Tx and Rx descriptors used by the EMAC.
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212 static void prvSetupDescriptors(void);
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215 * Write our MAC address into the EMAC.
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217 static void prvSetupMACAddress( void );
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220 * Configure the EMAC and AIC for EMAC interrupts.
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222 static void prvSetupEMACInterrupt( void );
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225 * Some initialisation functions taken from the Atmel EMAC sample code.
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227 static void vReadPHY( unsigned char ucPHYAddress, unsigned char ucAddress, unsigned long *pulValue );
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228 static portBASE_TYPE xGetLinkSpeed( void );
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229 static portBASE_TYPE prvProbePHY( void );
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230 #if USE_RMII_INTERFACE != 1
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231 static void vWritePHY( unsigned char ucPHYAddress, unsigned char ucAddress, unsigned long ulValue);
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235 /* The semaphore used by the EMAC ISR to wake the EMAC task. */
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236 static xSemaphoreHandle xSemaphore = NULL;
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238 /* Holds the index to the next buffer from which data will be read. */
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239 static volatile unsigned long ulNextRxBuffer = 0;
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241 /*-----------------------------------------------------------*/
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243 /* See the header file for descriptions of public functions. */
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244 long lEMACSend( char *pcFrom, unsigned long ulLength, long lEndOfFrame )
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246 static unsigned portBASE_TYPE uxTxBufferIndex = 0;
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247 portBASE_TYPE xWaitCycles = 0;
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248 long lReturn = pdPASS;
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250 unsigned long ulLastBuffer, ulDataBuffered = 0, ulDataRemainingToSend, ulLengthToSend;
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252 /* If the length of data to be transmitted is greater than each individual
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253 transmit buffer then the data will be split into more than one buffer.
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254 Loop until the entire length has been buffered. */
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255 while( ulDataBuffered < ulLength )
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257 /* Is a buffer available? */
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258 while( !( xTxDescriptors[ uxTxBufferIndex ].U_Status.status & AT91C_TRANSMIT_OK ) )
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260 /* There is no room to write the Tx data to the Tx buffer. Wait a
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261 short while, then try again. */
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263 if( xWaitCycles > emacMAX_WAIT_CYCLES )
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271 vTaskDelay( emacBUFFER_WAIT_DELAY );
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275 /* lReturn will only be pdPASS if a buffer is available. */
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276 if( lReturn == pdPASS )
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278 portENTER_CRITICAL();
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280 /* Get the address of the buffer from the descriptor, then copy
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281 the data into the buffer. */
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282 pcBuffer = ( char * ) xTxDescriptors[ uxTxBufferIndex ].addr;
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284 /* How much can we write to the buffer? */
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285 ulDataRemainingToSend = ulLength - ulDataBuffered;
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286 if( ulDataRemainingToSend <= ETH_TX_BUFFER_SIZE )
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288 /* We can write all the remaining bytes. */
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289 ulLengthToSend = ulDataRemainingToSend;
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293 /* We can not write more than ETH_TX_BUFFER_SIZE in one go. */
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294 ulLengthToSend = ETH_TX_BUFFER_SIZE;
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297 /* Copy the data into the buffer. */
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298 memcpy( ( void * ) pcBuffer, ( void * ) &( pcFrom[ ulDataBuffered ] ), ulLengthToSend );
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299 ulDataBuffered += ulLengthToSend;
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301 /* Is this the last data for the frame? */
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302 if( lEndOfFrame && ( ulDataBuffered >= ulLength ) )
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304 /* No more data remains for this frame so we can start the
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306 ulLastBuffer = AT91C_LAST_BUFFER;
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310 /* More data to come for this frame. */
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314 /* Fill out the necessary in the descriptor to get the data sent,
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315 then move to the next descriptor, wrapping if necessary. */
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316 if( uxTxBufferIndex >= ( NB_TX_BUFFERS - 1 ) )
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318 xTxDescriptors[ uxTxBufferIndex ].U_Status.status = ( ulLengthToSend & ( unsigned long ) AT91C_LENGTH_FRAME )
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320 | AT91C_TRANSMIT_WRAP;
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321 uxTxBufferIndex = 0;
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325 xTxDescriptors[ uxTxBufferIndex ].U_Status.status = ( ulLengthToSend & ( unsigned long ) AT91C_LENGTH_FRAME )
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330 /* If this is the last buffer to be sent for this frame we can
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331 start the transmission. */
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334 AT91C_BASE_EMAC->EMAC_NCR |= AT91C_EMAC_TSTART;
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337 portEXIT_CRITICAL();
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347 /*-----------------------------------------------------------*/
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349 /* See the header file for descriptions of public functions. */
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350 unsigned long ulEMACInputLength( void )
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352 register unsigned long ulIndex, ulLength = 0;
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354 /* Skip any fragments. We are looking for the first buffer that contains
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355 data and has the SOF (start of frame) bit set. */
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356 while( ( xRxDescriptors[ ulNextRxBuffer ].addr & AT91C_OWNERSHIP_BIT ) && !( xRxDescriptors[ ulNextRxBuffer ].U_Status.status & AT91C_SOF ) )
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358 /* Ignoring this buffer. Mark it as free again. */
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359 xRxDescriptors[ ulNextRxBuffer ].addr &= ~( AT91C_OWNERSHIP_BIT );
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361 if( ulNextRxBuffer >= NB_RX_BUFFERS )
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363 ulNextRxBuffer = 0;
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367 /* We are going to walk through the descriptors that make up this frame,
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368 but don't want to alter ulNextRxBuffer as this would prevent vEMACRead()
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369 from finding the data. Therefore use a copy of ulNextRxBuffer instead. */
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370 ulIndex = ulNextRxBuffer;
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372 /* Walk through the descriptors until we find the last buffer for this
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373 frame. The last buffer will give us the length of the entire frame. */
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374 while( ( xRxDescriptors[ ulIndex ].addr & AT91C_OWNERSHIP_BIT ) && !ulLength )
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376 ulLength = xRxDescriptors[ ulIndex ].U_Status.status & emacRX_LENGTH_FRAME;
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378 /* Increment to the next buffer, wrapping if necessary. */
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380 if( ulIndex >= NB_RX_BUFFERS )
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388 /*-----------------------------------------------------------*/
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390 /* See the header file for descriptions of public functions. */
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391 void vEMACRead( char *pcTo, unsigned long ulSectionLength, unsigned long ulTotalFrameLength )
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393 static unsigned long ulSectionBytesReadSoFar = 0, ulBufferPosition = 0, ulFameBytesReadSoFar = 0;
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394 static char *pcSource;
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395 register unsigned long ulBytesRemainingInBuffer, ulRemainingSectionBytes;
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397 /* Read ulSectionLength bytes from the Rx buffers. This is not necessarily any
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398 correspondence between the length of our Rx buffers, and the length of the
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399 data we are returning or the length of the data being requested. Therefore,
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400 between calls we have to remember not only which buffer we are currently
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401 processing, but our position within that buffer. This would be greatly
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402 simplified if PBUF_POOL_BUFSIZE could be guaranteed to be greater than
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403 the size of each Rx buffer, and that memory fragmentation did not occur.
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405 This function should only be called after a call to ulEMACInputLength().
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406 This will ensure ulNextRxBuffer is set to the correct buffer. */
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410 /* vEMACRead is called with pcTo set to NULL to indicate that we are about
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411 to read a new frame. Any fragments remaining in the frame we were
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412 processing during the last call should be dropped. */
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415 /* How many bytes are indicated as being in this buffer? If none then
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416 the buffer is completely full and the frame is contained within more
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417 than one buffer. */
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419 /* Reset our state variables ready for the next read from this buffer. */
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420 pcSource = ( char * )( xRxDescriptors[ ulNextRxBuffer ].addr & emacADDRESS_MASK );
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421 ulFameBytesReadSoFar = ( unsigned long ) 0;
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422 ulBufferPosition = ( unsigned long ) 0;
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426 /* Loop until we have obtained the required amount of data. */
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427 ulSectionBytesReadSoFar = 0;
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428 while( ulSectionBytesReadSoFar < ulSectionLength )
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430 /* We may have already read some data from this buffer. How much
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431 data remains in the buffer? */
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432 ulBytesRemainingInBuffer = ( ETH_RX_BUFFER_SIZE - ulBufferPosition );
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434 /* How many more bytes do we need to read before we have the
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435 required amount of data? */
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436 ulRemainingSectionBytes = ulSectionLength - ulSectionBytesReadSoFar;
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438 /* Do we want more data than remains in the buffer? */
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439 if( ulRemainingSectionBytes > ulBytesRemainingInBuffer )
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441 /* We want more data than remains in the buffer so we can
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442 write the remains of the buffer to the destination, then move
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443 onto the next buffer to get the rest. */
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444 memcpy( &( pcTo[ ulSectionBytesReadSoFar ] ), &( pcSource[ ulBufferPosition ] ), ulBytesRemainingInBuffer );
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445 ulSectionBytesReadSoFar += ulBytesRemainingInBuffer;
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446 ulFameBytesReadSoFar += ulBytesRemainingInBuffer;
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448 /* Mark the buffer as free again. */
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449 xRxDescriptors[ ulNextRxBuffer ].addr &= ~( AT91C_OWNERSHIP_BIT );
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451 /* Move onto the next buffer. */
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453 if( ulNextRxBuffer >= NB_RX_BUFFERS )
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455 ulNextRxBuffer = ( unsigned long ) 0;
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458 /* Reset the variables for the new buffer. */
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459 pcSource = ( char * )( xRxDescriptors[ ulNextRxBuffer ].addr & emacADDRESS_MASK );
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460 ulBufferPosition = ( unsigned long ) 0;
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464 /* We have enough data in this buffer to send back. Read out
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465 enough data and remember how far we read up to. */
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466 memcpy( &( pcTo[ ulSectionBytesReadSoFar ] ), &( pcSource[ ulBufferPosition ] ), ulRemainingSectionBytes );
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468 /* There may be more data in this buffer yet. Increment our
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469 position in this buffer past the data we have just read. */
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470 ulBufferPosition += ulRemainingSectionBytes;
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471 ulSectionBytesReadSoFar += ulRemainingSectionBytes;
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472 ulFameBytesReadSoFar += ulRemainingSectionBytes;
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474 /* Have we now finished with this buffer? */
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475 if( ( ulBufferPosition >= ETH_RX_BUFFER_SIZE ) || ( ulFameBytesReadSoFar >= ulTotalFrameLength ) )
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477 /* Mark the buffer as free again. */
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478 xRxDescriptors[ ulNextRxBuffer ].addr &= ~( AT91C_OWNERSHIP_BIT );
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480 /* Move onto the next buffer. */
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482 if( ulNextRxBuffer >= NB_RX_BUFFERS )
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484 ulNextRxBuffer = 0;
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487 pcSource = ( char * )( xRxDescriptors[ ulNextRxBuffer ].addr & emacADDRESS_MASK );
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488 ulBufferPosition = 0;
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494 /*-----------------------------------------------------------*/
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496 /* See the header file for descriptions of public functions. */
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497 xSemaphoreHandle xEMACInit( void )
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499 /* Code supplied by Atmel -------------------------------*/
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501 /* Disable pull up on RXDV => PHY normal mode (not in test mode),
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502 PHY has internal pull down. */
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503 AT91C_BASE_PIOB->PIO_PPUDR = 1 << 15;
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505 #if USE_RMII_INTERFACE != 1
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506 /* PHY has internal pull down : set MII mode. */
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507 AT91C_BASE_PIOB->PIO_PPUDR = 1 << 16;
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510 /* Clear PB18 <=> PHY powerdown. */
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511 AT91C_BASE_PIOB->PIO_PER = 1 << 18;
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512 AT91C_BASE_PIOB->PIO_OER = 1 << 18;
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513 AT91C_BASE_PIOB->PIO_CODR = 1 << 18;
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515 /* After PHY power up, hardware reset. */
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516 AT91C_BASE_RSTC->RSTC_RMR = emacRESET_KEY | emacRESET_LENGTH;
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517 AT91C_BASE_RSTC->RSTC_RCR = emacRESET_KEY | AT91C_RSTC_EXTRST;
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519 /* Wait for hardware reset end. */
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520 while( !( AT91C_BASE_RSTC->RSTC_RSR & AT91C_RSTC_NRSTL ) )
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522 __asm volatile ( "NOP" );
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524 __asm volatile ( "NOP" );
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526 /* Setup the pins. */
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527 AT91C_BASE_PIOB->PIO_ASR = emacPERIPHERAL_A_SETUP;
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528 AT91C_BASE_PIOB->PIO_PDR = emacPERIPHERAL_A_SETUP;
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530 /* Enable com between EMAC PHY.
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532 Enable management port. */
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533 AT91C_BASE_EMAC->EMAC_NCR |= AT91C_EMAC_MPE;
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535 /* MDC = MCK/32. */
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536 AT91C_BASE_EMAC->EMAC_NCFGR |= ( 2 ) << 10;
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538 /* Wait for PHY auto init end (rather crude delay!). */
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539 vTaskDelay( emacPHY_INIT_DELAY );
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541 /* PHY configuration. */
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542 #if USE_RMII_INTERFACE != 1
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544 unsigned long ulControl;
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546 /* PHY has internal pull down : disable MII isolate. */
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547 vReadPHY( AT91C_PHY_ADDR, MII_BMCR, &ulControl );
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548 vReadPHY( AT91C_PHY_ADDR, MII_BMCR, &ulControl );
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549 ulControl &= ~BMCR_ISOLATE;
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550 vWritePHY( AT91C_PHY_ADDR, MII_BMCR, ulControl );
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554 /* Disable management port again. */
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555 AT91C_BASE_EMAC->EMAC_NCR &= ~AT91C_EMAC_MPE;
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557 #if USE_RMII_INTERFACE != 1
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558 /* Enable EMAC in MII mode, enable clock ERXCK and ETXCK. */
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559 AT91C_BASE_EMAC->EMAC_USRIO = AT91C_EMAC_CLKEN ;
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561 /* Enable EMAC in RMII mode, enable RMII clock (50MHz from oscillator
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563 AT91C_BASE_EMAC->EMAC_USRIO = AT91C_EMAC_RMII | AT91C_EMAC_CLKEN ;
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566 /* End of code supplied by Atmel ------------------------*/
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568 /* Setup the buffers and descriptors. */
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569 prvSetupDescriptors();
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571 /* Load our MAC address into the EMAC. */
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572 prvSetupMACAddress();
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574 /* Are we connected? */
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575 if( prvProbePHY() )
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577 /* Enable the interrupt! */
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578 portENTER_CRITICAL();
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580 prvSetupEMACInterrupt();
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581 vPassEMACSemaphore( xSemaphore );
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583 portEXIT_CRITICAL();
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588 /*-----------------------------------------------------------*/
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590 /* See the header file for descriptions of public functions. */
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591 void vClearEMACTxBuffer( void )
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593 static unsigned portBASE_TYPE uxNextBufferToClear = 0;
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595 /* Called on Tx interrupt events to reset the AT91C_TRANSMIT_OK bit in each
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596 Tx buffer within the frame just transmitted. This marks all the buffers
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597 as available again.
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599 The first buffer in the frame should have the bit set automatically. */
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600 if( xTxDescriptors[ uxNextBufferToClear ].U_Status.status & AT91C_TRANSMIT_OK )
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602 /* Loop through the other buffers in the frame. */
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603 while( !( xTxDescriptors[ uxNextBufferToClear ].U_Status.status & AT91C_LAST_BUFFER ) )
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605 uxNextBufferToClear++;
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607 if( uxNextBufferToClear >= NB_TX_BUFFERS )
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609 uxNextBufferToClear = 0;
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612 xTxDescriptors[ uxNextBufferToClear ].U_Status.status |= AT91C_TRANSMIT_OK;
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615 /* Start with the next buffer the next time a Tx interrupt is called. */
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616 uxNextBufferToClear++;
\r
618 /* Do we need to wrap back to the first buffer? */
\r
619 if( uxNextBufferToClear >= NB_TX_BUFFERS )
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621 uxNextBufferToClear = 0;
\r
625 /*-----------------------------------------------------------*/
\r
627 static void prvSetupDescriptors(void)
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629 unsigned portBASE_TYPE xIndex;
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630 unsigned long ulAddress;
\r
632 /* Initialise xRxDescriptors descriptor. */
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633 for( xIndex = 0; xIndex < NB_RX_BUFFERS; ++xIndex )
\r
635 /* Calculate the address of the nth buffer within the array. */
\r
636 ulAddress = ( unsigned long )( pcRxBuffer + ( xIndex * ETH_RX_BUFFER_SIZE ) );
\r
638 /* Write the buffer address into the descriptor. The DMA will place
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639 the data at this address when this descriptor is being used. Mask off
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640 the bottom bits of the address as these have special meaning. */
\r
641 xRxDescriptors[ xIndex ].addr = ulAddress & emacADDRESS_MASK;
\r
644 /* The last buffer has the wrap bit set so the EMAC knows to wrap back
\r
645 to the first buffer. */
\r
646 xRxDescriptors[ NB_RX_BUFFERS - 1 ].addr |= emacRX_WRAP_BIT;
\r
648 /* Initialise xTxDescriptors. */
\r
649 for( xIndex = 0; xIndex < NB_TX_BUFFERS; ++xIndex )
\r
651 /* Calculate the address of the nth buffer within the array. */
\r
652 ulAddress = ( unsigned long )( pcTxBuffer + ( xIndex * ETH_TX_BUFFER_SIZE ) );
\r
654 /* Write the buffer address into the descriptor. The DMA will read
\r
655 data from here when the descriptor is being used. */
\r
656 xTxDescriptors[ xIndex ].addr = ulAddress & emacADDRESS_MASK;
\r
657 xTxDescriptors[ xIndex ].U_Status.status = AT91C_TRANSMIT_OK;
\r
660 /* The last buffer has the wrap bit set so the EMAC knows to wrap back
\r
661 to the first buffer. */
\r
662 xTxDescriptors[ NB_TX_BUFFERS - 1 ].U_Status.status = AT91C_TRANSMIT_WRAP | AT91C_TRANSMIT_OK;
\r
664 /* Tell the EMAC where to find the descriptors. */
\r
665 AT91C_BASE_EMAC->EMAC_RBQP = ( unsigned long ) xRxDescriptors;
\r
666 AT91C_BASE_EMAC->EMAC_TBQP = ( unsigned long ) xTxDescriptors;
\r
668 /* Clear all the bits in the receive status register. */
\r
669 AT91C_BASE_EMAC->EMAC_RSR = ( AT91C_EMAC_OVR | AT91C_EMAC_REC | AT91C_EMAC_BNA );
\r
671 /* Enable the copy of data into the buffers, ignore broadcasts,
\r
672 and don't copy FCS. */
\r
673 AT91C_BASE_EMAC->EMAC_NCFGR |= ( AT91C_EMAC_CAF | AT91C_EMAC_NBC | AT91C_EMAC_DRFCS);
\r
675 /* Enable Rx and Tx, plus the stats register. */
\r
676 AT91C_BASE_EMAC->EMAC_NCR |= ( AT91C_EMAC_TE | AT91C_EMAC_RE | AT91C_EMAC_WESTAT );
\r
678 /*-----------------------------------------------------------*/
\r
680 static void prvSetupMACAddress( void )
\r
682 /* Must be written SA1L then SA1H. */
\r
683 AT91C_BASE_EMAC->EMAC_SA1L = ( ( unsigned long ) cMACAddress[ 3 ] << 24 ) |
\r
684 ( ( unsigned long ) cMACAddress[ 2 ] << 16 ) |
\r
685 ( ( unsigned long ) cMACAddress[ 1 ] << 8 ) |
\r
688 AT91C_BASE_EMAC->EMAC_SA1H = ( ( unsigned long ) cMACAddress[ 5 ] << 8 ) |
\r
691 /*-----------------------------------------------------------*/
\r
693 static void prvSetupEMACInterrupt( void )
\r
695 /* Create the semaphore used to trigger the EMAC task. */
\r
696 vSemaphoreCreateBinary( xSemaphore );
\r
699 /* We start by 'taking' the semaphore so the ISR can 'give' it when the
\r
700 first interrupt occurs. */
\r
701 xSemaphoreTake( xSemaphore, emacNO_DELAY );
\r
702 portENTER_CRITICAL();
\r
704 /* We want to interrupt on Rx and Tx events. */
\r
705 AT91C_BASE_EMAC->EMAC_IER = AT91C_EMAC_RCOMP | AT91C_EMAC_TCOMP;
\r
707 /* Enable the interrupts in the AIC. */
\r
708 AT91F_AIC_ConfigureIt( AT91C_ID_EMAC, emacINTERRUPT_LEVEL, AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL, ( void (*)( void ) ) vEMACISR_Wrapper );
\r
709 AT91C_BASE_AIC->AIC_IECR = 0x1 << AT91C_ID_EMAC;
\r
711 portEXIT_CRITICAL();
\r
720 * The following functions are initialisation functions taken from the Atmel
\r
721 * EMAC sample code.
\r
725 static portBASE_TYPE prvProbePHY( void )
\r
727 unsigned long ulPHYId1, ulPHYId2, ulStatus;
\r
728 portBASE_TYPE xReturn = pdPASS;
\r
730 /* Code supplied by Atmel (reformatted) -----------------*/
\r
732 /* Enable management port */
\r
733 AT91C_BASE_EMAC->EMAC_NCR |= AT91C_EMAC_MPE;
\r
734 AT91C_BASE_EMAC->EMAC_NCFGR |= ( 2 ) << 10;
\r
736 /* Read the PHY ID. */
\r
737 vReadPHY( AT91C_PHY_ADDR, MII_PHYSID1, &ulPHYId1 );
\r
738 vReadPHY(AT91C_PHY_ADDR, MII_PHYSID2, &ulPHYId2 );
\r
743 Bits 3:0 Revision Number Four bit manufacturer?s revision number.
\r
744 0001 stands for Rev. A, etc.
\r
746 if( ( ( ulPHYId1 << 16 ) | ( ulPHYId2 & 0xfff0 ) ) != MII_DM9161_ID )
\r
748 /* Did not expect this ID. */
\r
753 ulStatus = xGetLinkSpeed();
\r
755 if( ulStatus != pdPASS )
\r
761 /* Disable management port */
\r
762 AT91C_BASE_EMAC->EMAC_NCR &= ~AT91C_EMAC_MPE;
\r
764 /* End of code supplied by Atmel ------------------------*/
\r
768 /*-----------------------------------------------------------*/
\r
770 static void vReadPHY( unsigned char ucPHYAddress, unsigned char ucAddress, unsigned long *pulValue )
\r
772 /* Code supplied by Atmel (reformatted) ----------------------*/
\r
774 AT91C_BASE_EMAC->EMAC_MAN = (AT91C_EMAC_SOF & (0x01<<30))
\r
775 | (2 << 16) | (2 << 28)
\r
776 | ((ucPHYAddress & 0x1f) << 23)
\r
777 | (ucAddress << 18);
\r
779 /* Wait until IDLE bit in Network Status register is cleared. */
\r
780 while( !( AT91C_BASE_EMAC->EMAC_NSR & AT91C_EMAC_IDLE ) )
\r
785 *pulValue = ( AT91C_BASE_EMAC->EMAC_MAN & 0x0000ffff );
\r
787 /* End of code supplied by Atmel ------------------------*/
\r
789 /*-----------------------------------------------------------*/
\r
791 #if USE_RMII_INTERFACE != 1
\r
792 static void vWritePHY( unsigned char ucPHYAddress, unsigned char ucAddress, unsigned long ulValue )
\r
794 /* Code supplied by Atmel (reformatted) ----------------------*/
\r
796 AT91C_BASE_EMAC->EMAC_MAN = (( AT91C_EMAC_SOF & (0x01<<30))
\r
797 | (2 << 16) | (1 << 28)
\r
798 | ((ucPHYAddress & 0x1f) << 23)
\r
799 | (ucAddress << 18))
\r
800 | (ulValue & 0xffff);
\r
802 /* Wait until IDLE bit in Network Status register is cleared */
\r
803 while( !( AT91C_BASE_EMAC->EMAC_NSR & AT91C_EMAC_IDLE ) )
\r
808 /* End of code supplied by Atmel ------------------------*/
\r
811 /*-----------------------------------------------------------*/
\r
813 static portBASE_TYPE xGetLinkSpeed( void )
\r
815 unsigned long ulBMSR, ulBMCR, ulLPA, ulMACCfg, ulSpeed, ulDuplex;
\r
817 /* Code supplied by Atmel (reformatted) -----------------*/
\r
819 /* Link status is latched, so read twice to get current value */
\r
820 vReadPHY(AT91C_PHY_ADDR, MII_BMSR, &ulBMSR);
\r
821 vReadPHY(AT91C_PHY_ADDR, MII_BMSR, &ulBMSR);
\r
823 if( !( ulBMSR & BMSR_LSTATUS ) )
\r
829 vReadPHY(AT91C_PHY_ADDR, MII_BMCR, &ulBMCR);
\r
830 if (ulBMCR & BMCR_ANENABLE)
\r
832 /* AutoNegotiation is enabled. */
\r
833 if (!(ulBMSR & BMSR_ANEGCOMPLETE))
\r
835 /* Auto-negotitation in progress. */
\r
839 vReadPHY(AT91C_PHY_ADDR, MII_LPA, &ulLPA);
\r
840 if( ( ulLPA & LPA_100FULL ) || ( ulLPA & LPA_100HALF ) )
\r
842 ulSpeed = SPEED_100;
\r
846 ulSpeed = SPEED_10;
\r
849 if( ( ulLPA & LPA_100FULL ) || ( ulLPA & LPA_10FULL ) )
\r
851 ulDuplex = DUPLEX_FULL;
\r
855 ulDuplex = DUPLEX_HALF;
\r
860 ulSpeed = ( ulBMCR & BMCR_SPEED100 ) ? SPEED_100 : SPEED_10;
\r
861 ulDuplex = ( ulBMCR & BMCR_FULLDPLX ) ? DUPLEX_FULL : DUPLEX_HALF;
\r
864 /* Update the MAC */
\r
865 ulMACCfg = AT91C_BASE_EMAC->EMAC_NCFGR & ~( AT91C_EMAC_SPD | AT91C_EMAC_FD );
\r
866 if( ulSpeed == SPEED_100 )
\r
868 if( ulDuplex == DUPLEX_FULL )
\r
870 /* 100 Full Duplex */
\r
871 AT91C_BASE_EMAC->EMAC_NCFGR = ulMACCfg | AT91C_EMAC_SPD | AT91C_EMAC_FD;
\r
875 /* 100 Half Duplex */
\r
876 AT91C_BASE_EMAC->EMAC_NCFGR = ulMACCfg | AT91C_EMAC_SPD;
\r
881 if (ulDuplex == DUPLEX_FULL)
\r
883 /* 10 Full Duplex */
\r
884 AT91C_BASE_EMAC->EMAC_NCFGR = ulMACCfg | AT91C_EMAC_FD;
\r
887 { /* 10 Half Duplex */
\r
888 AT91C_BASE_EMAC->EMAC_NCFGR = ulMACCfg;
\r
892 /* End of code supplied by Atmel ------------------------*/
\r
896 /*-----------------------------------------------------------*/
\r
898 void vEMACWaitForInput( void )
\r
900 /* Just wait until we are signled from an ISR that data is available, or
\r
901 we simply time out. */
\r
902 xSemaphoreTake( xSemaphore, emacBLOCK_TIME_WAITING_FOR_INPUT );
\r