2 * These files are taken from the MCF523X source code example package
\r
3 * which is available on the Freescale website. Freescale explicitly
\r
4 * grants the redistribution and modification of these source files.
\r
5 * The complete licensing information is available in the file
\r
6 * LICENSE_FREESCALE.TXT.
\r
8 * File: mcf523x_wtm.h
\r
9 * Purpose: Register and bit definitions for the MCF523X
\r
15 #ifndef __MCF523X_WTM_H__
\r
16 #define __MCF523X_WTM_H__
\r
18 /*********************************************************************
\r
20 * Watchdog Timer Modules (WTM)
\r
22 *********************************************************************/
\r
24 /* Register read/write macros */
\r
25 #define MCF_WTM_WCR (*(vuint16*)(void*)(&__IPSBAR[0x140000]))
\r
26 #define MCF_WTM_WMR (*(vuint16*)(void*)(&__IPSBAR[0x140002]))
\r
27 #define MCF_WTM_WCNTR (*(vuint16*)(void*)(&__IPSBAR[0x140004]))
\r
28 #define MCF_WTM_WSR (*(vuint16*)(void*)(&__IPSBAR[0x140006]))
\r
30 /* Bit definitions and macros for MCF_WTM_WCR */
\r
31 #define MCF_WTM_WCR_EN (0x0001)
\r
32 #define MCF_WTM_WCR_HALTED (0x0002)
\r
33 #define MCF_WTM_WCR_DOZE (0x0004)
\r
34 #define MCF_WTM_WCR_WAIT (0x0008)
\r
36 /* Bit definitions and macros for MCF_WTM_WMR */
\r
37 #define MCF_WTM_WMR_WM0 (0x0001)
\r
38 #define MCF_WTM_WMR_WM1 (0x0002)
\r
39 #define MCF_WTM_WMR_WM2 (0x0004)
\r
40 #define MCF_WTM_WMR_WM3 (0x0008)
\r
41 #define MCF_WTM_WMR_WM4 (0x0010)
\r
42 #define MCF_WTM_WMR_WM5 (0x0020)
\r
43 #define MCF_WTM_WMR_WM6 (0x0040)
\r
44 #define MCF_WTM_WMR_WM7 (0x0080)
\r
45 #define MCF_WTM_WMR_WM8 (0x0100)
\r
46 #define MCF_WTM_WMR_WM9 (0x0200)
\r
47 #define MCF_WTM_WMR_WM10 (0x0400)
\r
48 #define MCF_WTM_WMR_WM11 (0x0800)
\r
49 #define MCF_WTM_WMR_WM12 (0x1000)
\r
50 #define MCF_WTM_WMR_WM13 (0x2000)
\r
51 #define MCF_WTM_WMR_WM14 (0x4000)
\r
52 #define MCF_WTM_WMR_WM15 (0x8000)
\r
54 /* Bit definitions and macros for MCF_WTM_WCNTR */
\r
55 #define MCF_WTM_WCNTR_WC0 (0x0001)
\r
56 #define MCF_WTM_WCNTR_WC1 (0x0002)
\r
57 #define MCF_WTM_WCNTR_WC2 (0x0004)
\r
58 #define MCF_WTM_WCNTR_WC3 (0x0008)
\r
59 #define MCF_WTM_WCNTR_WC4 (0x0010)
\r
60 #define MCF_WTM_WCNTR_WC5 (0x0020)
\r
61 #define MCF_WTM_WCNTR_WC6 (0x0040)
\r
62 #define MCF_WTM_WCNTR_WC7 (0x0080)
\r
63 #define MCF_WTM_WCNTR_WC8 (0x0100)
\r
64 #define MCF_WTM_WCNTR_WC9 (0x0200)
\r
65 #define MCF_WTM_WCNTR_WC10 (0x0400)
\r
66 #define MCF_WTM_WCNTR_WC11 (0x0800)
\r
67 #define MCF_WTM_WCNTR_WC12 (0x1000)
\r
68 #define MCF_WTM_WCNTR_WC13 (0x2000)
\r
69 #define MCF_WTM_WCNTR_WC14 (0x4000)
\r
70 #define MCF_WTM_WCNTR_WC15 (0x8000)
\r
72 /* Bit definitions and macros for MCF_WTM_WSR */
\r
73 #define MCF_WTM_WSR_WS0 (0x0001)
\r
74 #define MCF_WTM_WSR_WS1 (0x0002)
\r
75 #define MCF_WTM_WSR_WS2 (0x0004)
\r
76 #define MCF_WTM_WSR_WS3 (0x0008)
\r
77 #define MCF_WTM_WSR_WS4 (0x0010)
\r
78 #define MCF_WTM_WSR_WS5 (0x0020)
\r
79 #define MCF_WTM_WSR_WS6 (0x0040)
\r
80 #define MCF_WTM_WSR_WS7 (0x0080)
\r
81 #define MCF_WTM_WSR_WS8 (0x0100)
\r
82 #define MCF_WTM_WSR_WS9 (0x0200)
\r
83 #define MCF_WTM_WSR_WS10 (0x0400)
\r
84 #define MCF_WTM_WSR_WS11 (0x0800)
\r
85 #define MCF_WTM_WSR_WS12 (0x1000)
\r
86 #define MCF_WTM_WSR_WS13 (0x2000)
\r
87 #define MCF_WTM_WSR_WS14 (0x4000)
\r
88 #define MCF_WTM_WSR_WS15 (0x8000)
\r
90 /********************************************************************/
\r
92 #endif /* __MCF523X_WTM_H__ */
\r