1 // cs8900a.c: device driver for the CS8900a chip in 8-bit mode.
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9 #define IOR (1<<12) // CS8900's ISA-bus interface pins
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12 // definitions for Crystal CS8900 ethernet-controller
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13 // based on linux-header by Russel Nelson
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15 #define PP_ChipID 0x0000 // offset 0h -> Corp-ID
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17 // offset 2h -> Model/Product Number
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18 #define LED_RED (1<<8)
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19 #define LED_GREEN (1<<10)
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20 #define LED_YELLOW (1<<11)
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22 #define PP_ISAIOB 0x0020 // IO base address
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23 #define PP_CS8900_ISAINT 0x0022 // ISA interrupt select
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24 #define PP_CS8900_ISADMA 0x0024 // ISA Rec DMA channel
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25 #define PP_ISASOF 0x0026 // ISA DMA offset
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26 #define PP_DmaFrameCnt 0x0028 // ISA DMA Frame count
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27 #define PP_DmaByteCnt 0x002A // ISA DMA Byte count
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28 #define PP_CS8900_ISAMemB 0x002C // Memory base
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29 #define PP_ISABootBase 0x0030 // Boot Prom base
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30 #define PP_ISABootMask 0x0034 // Boot Prom Mask
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32 // EEPROM data and command registers
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33 #define PP_EECMD 0x0040 // NVR Interface Command register
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34 #define PP_EEData 0x0042 // NVR Interface Data Register
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36 // Configuration and control registers
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37 #define PP_RxCFG 0x0102 // Rx Bus config
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38 #define PP_RxCTL 0x0104 // Receive Control Register
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39 #define PP_TxCFG 0x0106 // Transmit Config Register
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40 #define PP_TxCMD 0x0108 // Transmit Command Register
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41 #define PP_BufCFG 0x010A // Bus configuration Register
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42 #define PP_LineCTL 0x0112 // Line Config Register
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43 #define PP_SelfCTL 0x0114 // Self Command Register
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44 #define PP_BusCTL 0x0116 // ISA bus control Register
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45 #define PP_TestCTL 0x0118 // Test Register
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47 // Status and Event Registers
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48 #define PP_ISQ 0x0120 // Interrupt Status
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49 #define PP_RxEvent 0x0124 // Rx Event Register
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50 #define PP_TxEvent 0x0128 // Tx Event Register
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51 #define PP_BufEvent 0x012C // Bus Event Register
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52 #define PP_RxMiss 0x0130 // Receive Miss Count
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53 #define PP_TxCol 0x0132 // Transmit Collision Count
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54 #define PP_LineST 0x0134 // Line State Register
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55 #define PP_SelfST 0x0136 // Self State register
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56 #define PP_BusST 0x0138 // Bus Status
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57 #define PP_TDR 0x013C // Time Domain Reflectometry
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59 // Initiate Transmit Registers
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60 #define PP_TxCommand 0x0144 // Tx Command
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61 #define PP_TxLength 0x0146 // Tx Length
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63 // Adress Filter Registers
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64 #define PP_LAF 0x0150 // Hash Table
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65 #define PP_IA 0x0158 // Physical Address Register
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68 #define PP_RxStatus 0x0400 // Receive start of frame
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69 #define PP_RxLength 0x0402 // Receive Length of frame
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70 #define PP_RxFrame 0x0404 // Receive frame pointer
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71 #define PP_TxFrame 0x0A00 // Transmit frame pointer
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73 // Primary I/O Base Address. If no I/O base is supplied by the user, then this
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74 // can be used as the default I/O base to access the PacketPage Area.
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75 #define DEFAULTIOBASE 0x0300
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77 // PP_RxCFG - Receive Configuration and Interrupt Mask bit definition - Read/write
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78 #define SKIP_1 0x0040
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79 #define RX_STREAM_ENBL 0x0080
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80 #define RX_OK_ENBL 0x0100
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81 #define RX_DMA_ONLY 0x0200
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82 #define AUTO_RX_DMA 0x0400
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83 #define BUFFER_CRC 0x0800
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84 #define RX_CRC_ERROR_ENBL 0x1000
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85 #define RX_RUNT_ENBL 0x2000
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86 #define RX_EXTRA_DATA_ENBL 0x4000
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88 // PP_RxCTL - Receive Control bit definition - Read/write
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89 #define RX_IA_HASH_ACCEPT 0x0040
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90 #define RX_PROM_ACCEPT 0x0080
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91 #define RX_OK_ACCEPT 0x0100
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92 #define RX_MULTCAST_ACCEPT 0x0200
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93 #define RX_IA_ACCEPT 0x0400
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94 #define RX_BROADCAST_ACCEPT 0x0800
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95 #define RX_BAD_CRC_ACCEPT 0x1000
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96 #define RX_RUNT_ACCEPT 0x2000
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97 #define RX_EXTRA_DATA_ACCEPT 0x4000
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99 // PP_TxCFG - Transmit Configuration Interrupt Mask bit definition - Read/write
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100 #define TX_LOST_CRS_ENBL 0x0040
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101 #define TX_SQE_ERROR_ENBL 0x0080
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102 #define TX_OK_ENBL 0x0100
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103 #define TX_LATE_COL_ENBL 0x0200
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104 #define TX_JBR_ENBL 0x0400
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105 #define TX_ANY_COL_ENBL 0x0800
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106 #define TX_16_COL_ENBL 0x8000
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108 // PP_TxCMD - Transmit Command bit definition - Read-only and
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109 // PP_TxCommand - Write-only
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110 #define TX_START_5_BYTES 0x0000
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111 #define TX_START_381_BYTES 0x0040
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112 #define TX_START_1021_BYTES 0x0080
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113 #define TX_START_ALL_BYTES 0x00C0
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114 #define TX_FORCE 0x0100
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115 #define TX_ONE_COL 0x0200
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116 #define TX_NO_CRC 0x1000
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117 #define TX_RUNT 0x2000
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119 // PP_BufCFG - Buffer Configuration Interrupt Mask bit definition - Read/write
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120 #define GENERATE_SW_INTERRUPT 0x0040
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121 #define RX_DMA_ENBL 0x0080
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122 #define READY_FOR_TX_ENBL 0x0100
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123 #define TX_UNDERRUN_ENBL 0x0200
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124 #define RX_MISS_ENBL 0x0400
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125 #define RX_128_BYTE_ENBL 0x0800
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126 #define TX_COL_COUNT_OVRFLOW_ENBL 0x1000
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127 #define RX_MISS_COUNT_OVRFLOW_ENBL 0x2000
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128 #define RX_DEST_MATCH_ENBL 0x8000
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130 // PP_LineCTL - Line Control bit definition - Read/write
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131 #define SERIAL_RX_ON 0x0040
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132 #define SERIAL_TX_ON 0x0080
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133 #define AUI_ONLY 0x0100
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134 #define AUTO_AUI_10BASET 0x0200
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135 #define MODIFIED_BACKOFF 0x0800
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136 #define NO_AUTO_POLARITY 0x1000
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137 #define TWO_PART_DEFDIS 0x2000
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138 #define LOW_RX_SQUELCH 0x4000
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140 // PP_SelfCTL - Software Self Control bit definition - Read/write
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141 #define POWER_ON_RESET 0x0040
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142 #define SW_STOP 0x0100
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143 #define SLEEP_ON 0x0200
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144 #define AUTO_WAKEUP 0x0400
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145 #define HCB0_ENBL 0x1000
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146 #define HCB1_ENBL 0x2000
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147 #define HCB0 0x4000
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148 #define HCB1 0x8000
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150 // PP_BusCTL - ISA Bus Control bit definition - Read/write
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151 #define RESET_RX_DMA 0x0040
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152 #define MEMORY_ON 0x0400
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153 #define DMA_BURST_MODE 0x0800
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154 #define IO_CHANNEL_READY_ON 0x1000
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155 #define RX_DMA_SIZE_64K 0x2000
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156 #define ENABLE_IRQ 0x8000
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158 // PP_TestCTL - Test Control bit definition - Read/write
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159 #define LINK_OFF 0x0080
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160 #define ENDEC_LOOPBACK 0x0200
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161 #define AUI_LOOPBACK 0x0400
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162 #define BACKOFF_OFF 0x0800
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163 #define FDX_8900 0x4000
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165 // PP_RxEvent - Receive Event Bit definition - Read-only
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166 #define RX_IA_HASHED 0x0040
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167 #define RX_DRIBBLE 0x0080
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168 #define RX_OK 0x0100
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169 #define RX_HASHED 0x0200
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170 #define RX_IA 0x0400
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171 #define RX_BROADCAST 0x0800
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172 #define RX_CRC_ERROR 0x1000
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173 #define RX_RUNT 0x2000
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174 #define RX_EXTRA_DATA 0x4000
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175 #define HASH_INDEX_MASK 0xFC00 // Hash-Table Index Mask (6 Bit)
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177 // PP_TxEvent - Transmit Event Bit definition - Read-only
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178 #define TX_LOST_CRS 0x0040
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179 #define TX_SQE_ERROR 0x0080
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180 #define TX_OK 0x0100
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181 #define TX_LATE_COL 0x0200
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182 #define TX_JBR 0x0400
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183 #define TX_16_COL 0x8000
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184 #define TX_COL_COUNT_MASK 0x7800
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186 // PP_BufEvent - Buffer Event Bit definition - Read-only
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187 #define SW_INTERRUPT 0x0040
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188 #define RX_DMA 0x0080
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189 #define READY_FOR_TX 0x0100
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190 #define TX_UNDERRUN 0x0200
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191 #define RX_MISS 0x0400
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192 #define RX_128_BYTE 0x0800
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193 #define TX_COL_OVRFLW 0x1000
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194 #define RX_MISS_OVRFLW 0x2000
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195 #define RX_DEST_MATCH 0x8000
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197 // PP_LineST - Ethernet Line Status bit definition - Read-only
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198 #define LINK_OK 0x0080
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199 #define AUI_ON 0x0100
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200 #define TENBASET_ON 0x0200
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201 #define POLARITY_OK 0x1000
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202 #define CRS_OK 0x4000
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204 // PP_SelfST - Chip Software Status bit definition
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205 #define ACTIVE_33V 0x0040
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206 #define INIT_DONE 0x0080
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207 #define SI_BUSY 0x0100
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208 #define EEPROM_PRESENT 0x0200
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209 #define EEPROM_OK 0x0400
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210 #define EL_PRESENT 0x0800
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211 #define EE_SIZE_64 0x1000
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213 // PP_BusST - ISA Bus Status bit definition
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214 #define TX_BID_ERROR 0x0080
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215 #define READY_FOR_TX_NOW 0x0100
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217 // The following block defines the ISQ event types
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218 #define ISQ_RX_EVENT 0x0004
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219 #define ISQ_TX_EVENT 0x0008
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220 #define ISQ_BUFFER_EVENT 0x000C
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221 #define ISQ_RX_MISS_EVENT 0x0010
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222 #define ISQ_TX_COL_EVENT 0x0012
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224 #define ISQ_EVENT_MASK 0x003F // ISQ mask to find out type of event
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226 // Ports for I/O-Mode
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227 #define RX_FRAME_PORT 0x0000
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228 #define TX_FRAME_PORT 0x0000
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229 #define TX_CMD_PORT 0x0004
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230 #define TX_LEN_PORT 0x0006
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231 #define ISQ_PORT 0x0008
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232 #define ADD_PORT 0x000A
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233 #define DATA_PORT 0x000C
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235 #define AUTOINCREMENT 0x8000 // Bit mask to set Bit-15 for autoincrement
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238 #define EEPROM_WRITE_EN 0x00F0
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239 #define EEPROM_WRITE_DIS 0x0000
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240 #define EEPROM_WRITE_CMD 0x0100
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241 #define EEPROM_READ_CMD 0x0200
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243 // Receive Header of each packet in receive area of memory for DMA-Mode
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244 #define RBUF_EVENT_LOW 0x0000 // Low byte of RxEvent
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245 #define RBUF_EVENT_HIGH 0x0001 // High byte of RxEvent
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246 #define RBUF_LEN_LOW 0x0002 // Length of received data - low byte
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247 #define RBUF_LEN_HI 0x0003 // Length of received data - high byte
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248 #define RBUF_HEAD_LEN 0x0004 // Length of this header
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251 typedef struct { // struct to store CS8900's
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252 unsigned int Addr; // init-sequence
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256 unsigned short ticks;
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258 static void skip_frame(void);
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260 const TInitSeq InitSeq[] =
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262 PP_IA, UIP_ETHADDR0 + (UIP_ETHADDR1 << 8), // set our MAC as Individual Address
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263 PP_IA + 2, UIP_ETHADDR2 + (UIP_ETHADDR3 << 8),
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264 PP_IA + 4, UIP_ETHADDR4 + (UIP_ETHADDR5 << 8),
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265 PP_LineCTL, SERIAL_RX_ON | SERIAL_TX_ON, // configure the Physical Interface
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266 PP_RxCTL, RX_OK_ACCEPT | RX_IA_ACCEPT | RX_BROADCAST_ACCEPT
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269 // Writes a word in little-endian byte order to a specified port-address
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271 cs8900a_write(unsigned addr, unsigned int data)
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273 GPIO_IODIR |= 0xff << 16; // Data port to output
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275 GPIO_IOCLR = 0xf << 4; // Put address on bus
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276 GPIO_IOSET = addr << 4;
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278 GPIO_IOCLR = 0xff << 16; // Write low order byte to data bus
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279 GPIO_IOSET = data << 16;
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281 asm volatile ( "NOP" );
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282 GPIO_IOCLR = IOW; // Toggle IOW-signal
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283 asm volatile ( "NOP" );
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285 asm volatile ( "NOP" );
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287 GPIO_IOCLR = 0xf << 4;
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288 GPIO_IOSET = ((addr | 1) << 4); // And put next address on bus
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290 GPIO_IOCLR = 0xff << 16; // Write high order byte to data bus
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291 GPIO_IOSET = data >> 8 << 16;
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293 asm volatile ( "NOP" );
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294 GPIO_IOCLR = IOW; // Toggle IOW-signal
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295 asm volatile ( "NOP" );
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297 asm volatile ( "NOP" );
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300 // Reads a word in little-endian byte order from a specified port-address
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302 cs8900a_read(unsigned addr)
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304 unsigned int value;
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306 GPIO_IODIR &= ~(0xff << 16); // Data port to input
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308 GPIO_IOCLR = 0xf << 4; // Put address on bus
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309 GPIO_IOSET = addr << 4;
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311 asm volatile ( "NOP" );
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312 GPIO_IOCLR = IOR; // IOR-signal low
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313 asm volatile ( "NOP" );
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314 value = (GPIO_IOPIN >> 16) & 0xff; // get low order byte from data bus
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317 GPIO_IOSET = 1 << 4; // IOR high and put next address on bus
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319 asm volatile ( "NOP" );
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320 GPIO_IOCLR = IOR; // IOR-signal low
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321 asm volatile ( "NOP" );
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322 value |= ((GPIO_IOPIN >> 8) & 0xff00); // get high order byte from data bus
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323 GPIO_IOSET = IOR; // IOR-signal low
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328 // Reads a word in little-endian byte order from a specified port-address
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330 cs8900a_read_addr_high_first(unsigned addr)
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332 unsigned int value;
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334 GPIO_IODIR &= ~(0xff << 16); // Data port to input
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336 GPIO_IOCLR = 0xf << 4; // Put address on bus
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337 GPIO_IOSET = (addr+1) << 4;
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339 asm volatile ( "NOP" );
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340 GPIO_IOCLR = IOR; // IOR-signal low
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341 asm volatile ( "NOP" );
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342 value = ((GPIO_IOPIN >> 8) & 0xff00); // get high order byte from data bus
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343 GPIO_IOSET = IOR; // IOR-signal high
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345 GPIO_IOCLR = 1 << 4; // Put low address on bus
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347 asm volatile ( "NOP" );
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348 GPIO_IOCLR = IOR; // IOR-signal low
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349 asm volatile ( "NOP" );
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350 value |= (GPIO_IOPIN >> 16) & 0xff; // get low order byte from data bus
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361 // Reset outputs, control lines high
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362 GPIO_IOSET = IOR | IOW;
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365 GPIO_IOSET = LED_RED | LED_YELLOW | LED_GREEN;
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367 // Port 3 as output (all pins but RS232)
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368 GPIO_IODIR = ~0U; // everything to output.
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371 GPIO_IOCLR = 0xff << 16; // clear data outputs
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373 // Reset the CS8900A
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374 cs8900a_write(ADD_PORT, PP_SelfCTL);
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375 cs8900a_write(DATA_PORT, POWER_ON_RESET);
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377 // Wait until chip-reset is done
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378 cs8900a_write(ADD_PORT, PP_SelfST);
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379 while ((cs8900a_read(DATA_PORT) & INIT_DONE) == 0)
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382 // Configure the CS8900A
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383 for (i = 0; i < sizeof InitSeq / sizeof (TInitSeq); ++i)
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385 cs8900a_write(ADD_PORT, InitSeq[i].Addr);
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386 cs8900a_write(DATA_PORT, InitSeq[i].Data);
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395 GPIO_IOCLR = LED_RED; // Light RED LED when frame starting
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397 // Transmit command
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398 cs8900a_write(TX_CMD_PORT, TX_START_ALL_BYTES);
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399 cs8900a_write(TX_LEN_PORT, uip_len);
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401 // Maximum number of retries
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405 // Check for avaliable buffer space
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406 cs8900a_write(ADD_PORT, PP_BusST);
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407 if (cs8900a_read(DATA_PORT) & READY_FOR_TX_NOW)
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411 GPIO_IOSET = LED_RED; // Extinguish RED LED on end of frame
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415 // No space avaliable, skip a received frame and try again
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419 GPIO_IODIR |= 0xff << 16; // Data port to output
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421 // Send 40+14=54 bytes of header
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422 for (u = 0; u < 54; u += 2)
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424 GPIO_IOCLR = 0xf << 4; // Put address on bus
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425 GPIO_IOSET = TX_FRAME_PORT << 4;
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427 GPIO_IOCLR = 0xff << 16; // Write low order byte to data bus
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428 GPIO_IOSET = uip_buf[u] << 16; // write low order byte to data bus
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430 asm volatile ( "NOP" );
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431 GPIO_IOCLR = IOW; // Toggle IOW-signal
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432 asm volatile ( "NOP" );
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435 GPIO_IOCLR = 0xf << 4; // Put address on bus
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436 GPIO_IOSET = (TX_FRAME_PORT | 1) << 4; // and put next address on bus
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438 GPIO_IOCLR = 0xff << 16; // Write low order byte to data bus
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439 GPIO_IOSET = uip_buf[u+1] << 16; // write low order byte to data bus
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441 asm volatile ( "NOP" );
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442 GPIO_IOCLR = IOW; // Toggle IOW-signal
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443 asm volatile ( "NOP" );
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449 GPIO_IOSET = LED_RED; // Extinguish RED LED on end of frame
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453 // Send remainder of packet, the application data
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455 for (u = 0; u < uip_len; u += 2)
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458 GPIO_IOCLR = 0xf << 4; // Put address on bus
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459 GPIO_IOSET = TX_FRAME_PORT << 4;
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461 GPIO_IOCLR = 0xff << 16; // Write low order byte to data bus
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462 GPIO_IOSET = uip_appdata[u] << 16; // write low order byte to data bus
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464 asm volatile ( "NOP" );
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465 GPIO_IOCLR = IOW; // Toggle IOW-signal
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466 asm volatile ( "NOP" );
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469 GPIO_IOCLR = 0xf << 4; // Put address on bus
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470 GPIO_IOSET = (TX_FRAME_PORT | 1) << 4; // and put next address on bus
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472 GPIO_IOCLR = 0xff << 16; // Write low order byte to data bus
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473 GPIO_IOSET = uip_appdata[u+1] << 16; // write low order byte to data bus
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475 asm volatile ( "NOP" );
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476 GPIO_IOCLR = IOW; // Toggle IOW-signal
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477 asm volatile ( "NOP" );
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481 GPIO_IOSET = LED_RED; // Extinguish RED LED on end of frame
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487 // No space avaliable, skip a received frame and try again
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488 cs8900a_write(ADD_PORT, PP_RxCFG);
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489 cs8900a_write(DATA_PORT, cs8900a_read(DATA_PORT) | SKIP_1);
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497 // Check receiver event register to see if there are any valid frames avaliable
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498 cs8900a_write(ADD_PORT, PP_RxEvent);
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499 if ((cs8900a_read(DATA_PORT) & 0xd00) == 0)
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502 GPIO_IOCLR = LED_GREEN; // Light GREED LED when frame coming in.
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504 // Read receiver status and discard it.
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505 cs8900a_read_addr_high_first(RX_FRAME_PORT);
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507 // Read frame length
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508 len = cs8900a_read_addr_high_first(RX_FRAME_PORT);
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510 // If the frame is too big to handle, throw it away
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511 if (len > UIP_BUFSIZE)
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517 // Data port to input
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518 GPIO_IODIR &= ~(0xff << 16);
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520 GPIO_IOCLR = 0xf << 4; // put address on bus
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521 GPIO_IOSET = RX_FRAME_PORT << 4;
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523 // Read bytes into uip_buf
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527 GPIO_IOCLR = 1 << 4; // put address on bus
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529 GPIO_IOCLR = IOR; // IOR-signal low
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530 uip_buf[u] = GPIO_IOPIN >> 16; // get high order byte from data bus
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531 asm volatile ( "NOP" );
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532 GPIO_IOSET = IOR; // IOR-signal high
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534 GPIO_IOSET = 1 << 4; // put address on bus
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536 GPIO_IOCLR = IOR; // IOR-signal low
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537 asm volatile ( "NOP" );
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538 uip_buf[u+1] = GPIO_IOPIN >> 16; // get high order byte from data bus
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539 GPIO_IOSET = IOR; // IOR-signal high
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543 GPIO_IOSET = LED_GREEN; // Extinguish GREED LED when frame finished.
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