2 * FreeRTOS Kernel V10.2.0
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3 * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.
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5 * Permission is hereby granted, free of charge, to any person obtaining a copy of
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6 * this software and associated documentation files (the "Software"), to deal in
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7 * the Software without restriction, including without limitation the rights to
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8 * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
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9 * the Software, and to permit persons to whom the Software is furnished to do so,
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10 * subject to the following conditions:
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12 * The above copyright notice and this permission notice shall be included in all
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13 * copies or substantial portions of the Software.
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15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
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17 * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
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18 * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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19 * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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20 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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22 * http://www.FreeRTOS.org
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23 * http://aws.amazon.com/freertos
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25 * 1 tab == 4 spaces!
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28 /* Standard includes. */
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31 /* Portasm includes. */
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32 #include "portasm.h"
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34 void vRestoreContextOfFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
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38 " .syntax unified \n"
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40 " ldr r2, pxCurrentTCBConst2 \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
\r
41 " ldr r3, [r2] \n" /* Read pxCurrentTCB. */
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42 " ldr r0, [r3] \n" /* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */
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44 #if( configENABLE_MPU == 1 )
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45 " adds r3, #4 \n" /* r3 = r3 + 4. r3 now points to MAIR0 in TCB. */
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46 " ldr r4, [r3] \n" /* r4 = *r3 i.e. r4 = MAIR0. */
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47 " ldr r2, xMAIR0Const2 \n" /* r2 = 0xe000edc0 [Location of MAIR0]. */
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48 " str r4, [r2] \n" /* Program MAIR0. */
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49 " ldr r2, xRNRConst2 \n" /* r2 = 0xe000ed98 [Location of RNR]. */
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50 " movs r4, #4 \n" /* r4 = 4. */
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51 " str r4, [r2] \n" /* Program RNR = 4. */
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52 " adds r3, #4 \n" /* r3 = r3 + 4. r3 now points to first RBAR in TCB. */
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53 " ldr r2, xRBARConst2 \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
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54 " ldmia r3!, {r4-r11} \n" /* Read 4 set of RBAR/RLAR registers from TCB. */
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55 " stmia r2!, {r4-r11} \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
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56 #endif /* configENABLE_MPU */
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58 #if( configENABLE_MPU == 1 )
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59 " ldm r0!, {r1-r4} \n" /* Read from stack - r1 = xSecureContext, r2 = PSPLIM, r3 = CONTROL and r4 = EXC_RETURN. */
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60 " ldr r5, xSecureContextConst2 \n"
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61 " str r1, [r5] \n" /* Set xSecureContext to this task's value for the same. */
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62 " msr psplim, r2 \n" /* Set this task's PSPLIM value. */
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63 " msr control, r3 \n" /* Set this task's CONTROL value. */
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64 " adds r0, #32 \n" /* Discard everything up to r0. */
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65 " msr psp, r0 \n" /* This is now the new top of stack to use in the task. */
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67 " bx r4 \n" /* Finally, branch to EXC_RETURN. */
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68 #else /* configENABLE_MPU */
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69 " ldm r0!, {r1-r3} \n" /* Read from stack - r1 = xSecureContext, r2 = PSPLIM and r3 = EXC_RETURN. */
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70 " ldr r4, xSecureContextConst2 \n"
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71 " str r1, [r4] \n" /* Set xSecureContext to this task's value for the same. */
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72 " msr psplim, r2 \n" /* Set this task's PSPLIM value. */
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73 " movs r1, #2 \n" /* r1 = 2. */
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74 " msr CONTROL, r1 \n" /* Switch to use PSP in the thread mode. */
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75 " adds r0, #32 \n" /* Discard everything up to r0. */
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76 " msr psp, r0 \n" /* This is now the new top of stack to use in the task. */
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78 " bx r3 \n" /* Finally, branch to EXC_RETURN. */
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79 #endif /* configENABLE_MPU */
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82 "pxCurrentTCBConst2: .word pxCurrentTCB \n"
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83 "xSecureContextConst2: .word xSecureContext \n"
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84 #if( configENABLE_MPU == 1 )
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85 "xMAIR0Const2: .word 0xe000edc0 \n"
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86 "xRNRConst2: .word 0xe000ed98 \n"
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87 "xRBARConst2: .word 0xe000ed9c \n"
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88 #endif /* configENABLE_MPU */
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91 /*-----------------------------------------------------------*/
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93 BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */
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97 " mrs r0, control \n" /* r0 = CONTROL. */
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98 " tst r0, #1 \n" /* Perform r0 & 1 (bitwise AND) and update the conditions flag. */
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100 " movne r0, #0 \n" /* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */
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101 " moveq r0, #1 \n" /* CONTROL[0]==0. Return true to indicate that the processor is privileged. */
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102 " bx lr \n" /* Return. */
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108 /*-----------------------------------------------------------*/
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110 void vRaisePrivilege( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
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114 " mrs r0, control \n" /* Read the CONTROL register. */
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115 " bic r0, #1 \n" /* Clear the bit 0. */
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116 " msr control, r0 \n" /* Write back the new CONTROL value. */
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117 " bx lr \n" /* Return to the caller. */
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121 /*-----------------------------------------------------------*/
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123 void vResetPrivilege( void ) /* __attribute__ (( naked )) */
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127 " mrs r0, control \n" /* r0 = CONTROL. */
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128 " orr r0, #1 \n" /* r0 = r0 | 1. */
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129 " msr control, r0 \n" /* CONTROL = r0. */
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130 " bx lr \n" /* Return to the caller. */
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134 /*-----------------------------------------------------------*/
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136 void vStartFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
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140 " ldr r0, xVTORConst \n" /* Use the NVIC offset register to locate the stack. */
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141 " ldr r0, [r0] \n" /* Read the VTOR register which gives the address of vector table. */
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142 " ldr r0, [r0] \n" /* The first entry in vector table is stack pointer. */
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143 " msr msp, r0 \n" /* Set the MSP back to the start of the stack. */
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144 " cpsie i \n" /* Globally enable interrupts. */
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148 " svc %0 \n" /* System call to start the first task. */
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152 "xVTORConst: .word 0xe000ed08 \n"
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153 :: "i" ( portSVC_START_SCHEDULER ) : "memory"
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156 /*-----------------------------------------------------------*/
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158 uint32_t ulSetInterruptMaskFromISR( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */
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162 " mrs r0, PRIMASK \n"
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168 #if !defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
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169 /* To avoid compiler warnings. The return statement will never be reached,
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170 * but some compilers warn if it is not included, while others won't compile
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175 /*-----------------------------------------------------------*/
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177 void vClearInterruptMaskFromISR( __attribute__( ( unused ) ) uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */
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181 " msr PRIMASK, r0 \n"
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186 #if !defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
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187 /* Just to avoid compiler warning. ulMask is used from the asm code but
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188 * the compiler can't see that. Some compilers generate warnings without
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189 * the following line, while others generate warnings if the line is
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194 /*-----------------------------------------------------------*/
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196 void PendSV_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
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200 " .syntax unified \n"
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201 " .extern SecureContext_SaveContext \n"
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202 " .extern SecureContext_LoadContext \n"
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204 " mrs r1, psp \n" /* Read PSP in r1. */
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205 " ldr r2, xSecureContextConst \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */
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206 " ldr r0, [r2] \n" /* Read xSecureContext - Value of xSecureContext must be in r0 as it is used as a parameter later. */
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208 " cbz r0, save_ns_context \n" /* No secure context to save. */
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209 " push {r0-r2, r14} \n"
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210 " bl SecureContext_SaveContext \n"
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211 " pop {r0-r3} \n" /* LR is now in r3. */
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212 " mov lr, r3 \n" /* LR = r3. */
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213 " lsls r2, r3, #25 \n" /* r2 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
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214 " bpl save_ns_context \n" /* bpl - branch if positive or zero. If r2 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
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215 " ldr r3, pxCurrentTCBConst \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
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216 " ldr r2, [r3] \n" /* Read pxCurrentTCB. */
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217 #if( configENABLE_MPU == 1 )
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218 " subs r1, r1, #16 \n" /* Make space for xSecureContext, PSPLIM, CONTROL and LR on the stack. */
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219 " str r1, [r2] \n" /* Save the new top of stack in TCB. */
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220 " mrs r2, psplim \n" /* r2 = PSPLIM. */
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221 " mrs r3, control \n" /* r3 = CONTROL. */
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222 " mov r4, lr \n" /* r4 = LR/EXC_RETURN. */
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223 " stmia r1!, {r0, r2-r4} \n" /* Store xSecureContext, PSPLIM, CONTROL and LR on the stack. */
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224 #else /* configENABLE_MPU */
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225 " subs r1, r1, #12 \n" /* Make space for xSecureContext, PSPLIM and LR on the stack. */
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226 " str r1, [r2] \n" /* Save the new top of stack in TCB. */
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227 " mrs r2, psplim \n" /* r2 = PSPLIM. */
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228 " mov r3, lr \n" /* r3 = LR/EXC_RETURN. */
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229 " stmia r1!, {r0, r2-r3} \n" /* Store xSecureContext, PSPLIM and LR on the stack. */
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230 #endif /* configENABLE_MPU */
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231 " b select_next_task \n"
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233 " save_ns_context: \n"
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234 " ldr r3, pxCurrentTCBConst \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
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235 " ldr r2, [r3] \n" /* Read pxCurrentTCB. */
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236 #if( configENABLE_FPU == 1 )
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237 " tst lr, #0x10 \n" /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the FPU is in use. */
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239 " vstmdbeq r1!, {s16-s31} \n" /* Store the FPU registers which are not saved automatically. */
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240 #endif /* configENABLE_FPU */
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241 #if( configENABLE_MPU == 1 )
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242 " subs r1, r1, #48 \n" /* Make space for xSecureContext, PSPLIM, CONTROL, LR and the remaining registers on the stack. */
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243 " str r1, [r2] \n" /* Save the new top of stack in TCB. */
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244 " adds r1, r1, #16 \n" /* r1 = r1 + 16. */
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245 " stm r1, {r4-r11} \n" /* Store the registers that are not saved automatically. */
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246 " mrs r2, psplim \n" /* r2 = PSPLIM. */
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247 " mrs r3, control \n" /* r3 = CONTROL. */
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248 " mov r4, lr \n" /* r4 = LR/EXC_RETURN. */
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249 " subs r1, r1, #16 \n" /* r1 = r1 - 16. */
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250 " stm r1, {r0, r2-r4} \n" /* Store xSecureContext, PSPLIM, CONTROL and LR on the stack. */
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251 #else /* configENABLE_MPU */
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252 " subs r1, r1, #44 \n" /* Make space for xSecureContext, PSPLIM, LR and the remaining registers on the stack. */
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253 " str r1, [r2] \n" /* Save the new top of stack in TCB. */
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254 " adds r1, r1, #12 \n" /* r1 = r1 + 12. */
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255 " stm r1, {r4-r11} \n" /* Store the registers that are not saved automatically. */
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256 " mrs r2, psplim \n" /* r2 = PSPLIM. */
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257 " mov r3, lr \n" /* r3 = LR/EXC_RETURN. */
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258 " subs r1, r1, #12 \n" /* r1 = r1 - 12. */
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259 " stmia r1!, {r0, r2-r3} \n" /* Store xSecureContext, PSPLIM and LR on the stack. */
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260 #endif /* configENABLE_MPU */
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262 " select_next_task: \n"
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264 " bl vTaskSwitchContext \n"
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267 " ldr r2, pxCurrentTCBConst \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
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268 " ldr r3, [r2] \n" /* Read pxCurrentTCB. */
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269 " ldr r1, [r3] \n" /* The first item in pxCurrentTCB is the task top of stack. r1 now points to the top of stack. */
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271 #if( configENABLE_MPU == 1 )
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272 " adds r3, #4 \n" /* r3 = r3 + 4. r3 now points to MAIR0 in TCB. */
\r
273 " ldr r4, [r3] \n" /* r4 = *r3 i.e. r4 = MAIR0. */
\r
274 " ldr r2, xMAIR0Const \n" /* r2 = 0xe000edc0 [Location of MAIR0]. */
\r
275 " str r4, [r2] \n" /* Program MAIR0. */
\r
276 " ldr r2, xRNRConst \n" /* r2 = 0xe000ed98 [Location of RNR]. */
\r
277 " movs r4, #4 \n" /* r4 = 4. */
\r
278 " str r4, [r2] \n" /* Program RNR = 4. */
\r
279 " adds r3, #4 \n" /* r3 = r3 + 4. r3 now points to first RBAR in TCB. */
\r
280 " ldr r2, xRBARConst \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
\r
281 " ldmia r3!, {r4-r11} \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */
\r
282 " stmia r2!, {r4-r11} \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
\r
283 #endif /* configENABLE_MPU */
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285 #if( configENABLE_MPU == 1 )
\r
286 " ldmia r1!, {r0, r2-r4} \n" /* Read from stack - r0 = xSecureContext, r2 = PSPLIM, r3 = CONTROL and r4 = LR. */
\r
287 " msr psplim, r2 \n" /* Restore the PSPLIM register value for the task. */
\r
288 " msr control, r3 \n" /* Restore the CONTROL register value for the task. */
\r
289 " mov lr, r4 \n" /* LR = r4. */
\r
290 " ldr r2, xSecureContextConst \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */
\r
291 " str r0, [r2] \n" /* Restore the task's xSecureContext. */
\r
292 " cbz r0, restore_ns_context \n" /* If there is no secure context for the task, restore the non-secure context. */
\r
294 " bl SecureContext_LoadContext \n" /* Restore the secure context. */
\r
296 " mov lr, r4 \n" /* LR = r4. */
\r
297 " lsls r2, r4, #25 \n" /* r2 = r4 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
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298 " bpl restore_ns_context \n" /* bpl - branch if positive or zero. If r2 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
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299 " msr psp, r1 \n" /* Remember the new top of stack for the task. */
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301 #else /* configENABLE_MPU */
\r
302 " ldmia r1!, {r0, r2-r3} \n" /* Read from stack - r0 = xSecureContext, r2 = PSPLIM and r3 = LR. */
\r
303 " msr psplim, r2 \n" /* Restore the PSPLIM register value for the task. */
\r
304 " mov lr, r3 \n" /* LR = r3. */
\r
305 " ldr r2, xSecureContextConst \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */
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306 " str r0, [r2] \n" /* Restore the task's xSecureContext. */
\r
307 " cbz r0, restore_ns_context \n" /* If there is no secure context for the task, restore the non-secure context. */
\r
309 " bl SecureContext_LoadContext \n" /* Restore the secure context. */
\r
311 " mov lr, r3 \n" /* LR = r3. */
\r
312 " lsls r2, r3, #25 \n" /* r2 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
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313 " bpl restore_ns_context \n" /* bpl - branch if positive or zero. If r2 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
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314 " msr psp, r1 \n" /* Remember the new top of stack for the task. */
\r
316 #endif /* configENABLE_MPU */
\r
318 " restore_ns_context: \n"
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319 " ldmia r1!, {r4-r11} \n" /* Restore the registers that are not automatically restored. */
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320 #if( configENABLE_FPU == 1 )
\r
321 " tst lr, #0x10 \n" /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the FPU is in use. */
\r
323 " vldmiaeq r1!, {s16-s31} \n" /* Restore the FPU registers which are not restored automatically. */
\r
324 #endif /* configENABLE_FPU */
\r
325 " msr psp, r1 \n" /* Remember the new top of stack for the task. */
\r
329 "pxCurrentTCBConst: .word pxCurrentTCB \n"
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330 "xSecureContextConst: .word xSecureContext \n"
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331 #if( configENABLE_MPU == 1 )
\r
332 "xMAIR0Const: .word 0xe000edc0 \n"
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333 "xRNRConst: .word 0xe000ed98 \n"
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334 "xRBARConst: .word 0xe000ed9c \n"
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335 #endif /* configENABLE_MPU */
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338 /*-----------------------------------------------------------*/
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340 void SVC_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
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346 " mrseq r0, msp \n"
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347 " mrsne r0, psp \n"
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348 " ldr r1, svchandler_address_const \n"
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352 "svchandler_address_const: .word vPortSVCHandler_C \n"
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355 /*-----------------------------------------------------------*/
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357 void vPortAllocateSecureContext( uint32_t ulSecureStackSize ) /* __attribute__ (( naked )) */
\r
361 " svc %0 \n" /* Secure context is allocated in the supervisor call. */
\r
362 " bx lr \n" /* Return. */
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363 :: "i" ( portSVC_ALLOCATE_SECURE_CONTEXT ) : "memory"
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366 /*-----------------------------------------------------------*/
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368 void vPortFreeSecureContext( uint32_t *pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
\r
372 " ldr r1, [r0] \n" /* The first item in the TCB is the top of the stack. */
\r
373 " ldr r0, [r1] \n" /* The first item on the stack is the task's xSecureContext. */
\r
374 " cmp r0, #0 \n" /* Raise svc if task's xSecureContext is not NULL. */
\r
376 " svcne %0 \n" /* Secure context is freed in the supervisor call. */
\r
377 " bx lr \n" /* Return. */
\r
378 :: "i" ( portSVC_FREE_SECURE_CONTEXT ) : "memory"
\r
381 /*-----------------------------------------------------------*/
\r