git.sur5r.net Git - freertos/blob - FreeRTOS/Source/portable/ARMv8M/non_secure/portable/IAR/ARM_CM23_NTZ/portasm.s

   1 /*\r
   2  * FreeRTOS Kernel V10.2.1\r
   3  * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\r
   4  *\r
   5  * Permission is hereby granted, free of charge, to any person obtaining a copy of\r
   6  * this software and associated documentation files (the "Software"), to deal in\r
   7  * the Software without restriction, including without limitation the rights to\r
   8  * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\r
   9  * the Software, and to permit persons to whom the Software is furnished to do so,\r
  10  * subject to the following conditions:\r
  11  *\r
  12  * The above copyright notice and this permission notice shall be included in all\r
  13  * copies or substantial portions of the Software.\r
  14  *\r
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\r
  17  * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\r
  18  * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\r
  19  * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
  20  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r
  21  *\r
  22  * http://www.FreeRTOS.org\r
  23  * http://aws.amazon.com/freertos\r
  24  *\r
  25  * 1 tab == 4 spaces!\r
  26  */\r
  27 \r
  28         EXTERN pxCurrentTCB\r
  29         EXTERN vTaskSwitchContext\r
  30         EXTERN vPortSVCHandler_C\r
  31 \r
  32         PUBLIC xIsPrivileged\r
  33         PUBLIC vResetPrivilege\r
  34         PUBLIC vRestoreContextOfFirstTask\r
  35         PUBLIC vRaisePrivilege\r
  36         PUBLIC vStartFirstTask\r
  37         PUBLIC ulSetInterruptMaskFromISR\r
  38         PUBLIC vClearInterruptMaskFromISR\r
  39         PUBLIC PendSV_Handler\r
  40         PUBLIC SVC_Handler\r
  41 \r
  42 #if ( configENABLE_FPU == 1 )\r
  43         #error Cortex-M23 does not have a Floating Point Unit (FPU) and therefore configENABLE_FPU must be set to 0.\r
  44 #endif\r
  45 /*-----------------------------------------------------------*/\r
  46 \r
  47 /*---------------- Unprivileged Functions -------------------*/\r
  48 \r
  49 /*-----------------------------------------------------------*/\r
  50 \r
  51         SECTION .text:CODE:NOROOT(2)\r
  52         THUMB\r
  53 /*-----------------------------------------------------------*/\r
  54 \r
  55 xIsPrivileged:\r
  56         mrs r0, control                                                 /* r0 = CONTROL. */\r
  57         movs r1, #1                                                             /* r1 = 1. */\r
  58         tst r0, r1                                                              /* Perform r0 & r1 (bitwise AND) and update the conditions flag. */\r
  59         beq running_privileged                                  /* If the result of previous AND operation was 0, branch. */\r
  60         movs r0, #0                                                             /* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */\r
  61         bx lr                                                                   /* Return. */\r
  62         running_privileged:\r
  63                 movs r0, #1                                                     /* CONTROL[0]==0. Return true to indicate that the processor is privileged. */\r
  64                 bx lr                                                           /* Return. */\r
  65 \r
  66 /*-----------------------------------------------------------*/\r
  67 \r
  68 vResetPrivilege:\r
  69         mrs r0, control                                                 /* r0 = CONTROL. */\r
  70         movs r1, #1                                                             /* r1 = 1. */\r
  71         orrs r0, r1                                                             /* r0 = r0 | r1. */\r
  72         msr control, r0                                                 /* CONTROL = r0. */\r
  73         bx lr                                                                   /* Return to the caller. */\r
  74 /*-----------------------------------------------------------*/\r
  75 \r
  76 /*----------------- Privileged Functions --------------------*/\r
  77 \r
  78 /*-----------------------------------------------------------*/\r
  79 \r
  80         SECTION privileged_functions:CODE:NOROOT(2)\r
  81         THUMB\r
  82 /*-----------------------------------------------------------*/\r
  83 \r
  84 vRestoreContextOfFirstTask:\r
  85         ldr  r2, =pxCurrentTCB                                  /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */\r
  86         ldr  r1, [r2]                                                   /* Read pxCurrentTCB. */\r
  87         ldr  r0, [r1]                                                   /* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */\r
  88 \r
  89 #if ( configENABLE_MPU == 1 )\r
  90         dmb                                                                             /* Complete outstanding transfers before disabling MPU. */\r
  91         ldr r2, =0xe000ed94                                             /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */\r
  92         ldr r3, [r2]                                                    /* Read the value of MPU_CTRL. */\r
  93         movs r4, #1                                                             /* r4 = 1. */\r
  94         bics r3, r4                                                             /* r3 = r3 & ~r4 i.e. Clear the bit 0 in r3. */\r
  95         str r3, [r2]                                                    /* Disable MPU. */\r
  96 \r
  97         adds r1, #4                                                             /* r1 = r1 + 4. r1 now points to MAIR0 in TCB. */\r
  98         ldr  r4, [r1]                                                   /* r4 = *r1 i.e. r4 = MAIR0. */\r
  99         ldr  r2, =0xe000edc0                                    /* r2 = 0xe000edc0 [Location of MAIR0]. */\r
 100         str  r4, [r2]                                                   /* Program MAIR0. */\r
 101         ldr  r2, =0xe000ed98                                    /* r2 = 0xe000ed98 [Location of RNR]. */\r
 102         adds r1, #4                                                             /* r1 = r1 + 4. r1 now points to first RBAR in TCB. */\r
 103         movs r4, #4                                                             /* r4 = 4. */\r
 104         str  r4, [r2]                                                   /* Program RNR = 4. */\r
 105         ldmia r1!, {r5,r6}                                              /* Read first set of RBAR/RLAR from TCB. */\r
 106         ldr  r3, =0xe000ed9c                                    /* r3 = 0xe000ed9c [Location of RBAR]. */\r
 107         stmia r3!, {r5,r6}                                              /* Write first set of RBAR/RLAR registers. */\r
 108         movs r4, #5                                                             /* r4 = 5. */\r
 109         str  r4, [r2]                                                   /* Program RNR = 5. */\r
 110         ldmia r1!, {r5,r6}                                              /* Read second set of RBAR/RLAR from TCB. */\r
 111         ldr  r3, =0xe000ed9c                                    /* r3 = 0xe000ed9c [Location of RBAR]. */\r
 112         stmia r3!, {r5,r6}                                              /* Write second set of RBAR/RLAR registers. */\r
 113         movs r4, #6                                                             /* r4 = 6. */\r
 114         str  r4, [r2]                                                   /* Program RNR = 6. */\r
 115         ldmia r1!, {r5,r6}                                              /* Read third set of RBAR/RLAR from TCB. */\r
 116         ldr  r3, =0xe000ed9c                                    /* r3 = 0xe000ed9c [Location of RBAR]. */\r
 117         stmia r3!, {r5,r6}                                              /* Write third set of RBAR/RLAR registers. */\r
 118         movs r4, #7                                                             /* r4 = 7. */\r
 119         str  r4, [r2]                                                   /* Program RNR = 7. */\r
 120         ldmia r1!, {r5,r6}                                              /* Read fourth set of RBAR/RLAR from TCB. */\r
 121         ldr  r3, =0xe000ed9c                                    /* r3 = 0xe000ed9c [Location of RBAR]. */\r
 122         stmia r3!, {r5,r6}                                              /* Write fourth set of RBAR/RLAR registers. */\r
 123 \r
 124         ldr r2, =0xe000ed94                                             /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */\r
 125         ldr r3, [r2]                                                    /* Read the value of MPU_CTRL. */\r
 126         movs r4, #1                                                             /* r4 = 1. */\r
 127         orrs r3, r4                                                             /* r3 = r3 | r4 i.e. Set the bit 0 in r3. */\r
 128         str r3, [r2]                                                    /* Enable MPU. */\r
 129         dsb                                                                             /* Force memory writes before continuing. */\r
 130 #endif /* configENABLE_MPU */\r
 131 \r
 132 #if ( configENABLE_MPU == 1 )\r
 133         ldm  r0!, {r1-r3}                                               /* Read from stack - r1 = PSPLIM, r2 = CONTROL and r3 = EXC_RETURN. */\r
 134         msr  psplim, r1                                                 /* Set this task's PSPLIM value. */\r
 135         msr  control, r2                                                /* Set this task's CONTROL value. */\r
 136         adds r0, #32                                                    /* Discard everything up to r0. */\r
 137         msr  psp, r0                                                    /* This is now the new top of stack to use in the task. */\r
 138         isb\r
 139         bx   r3                                                                 /* Finally, branch to EXC_RETURN. */\r
 140 #else /* configENABLE_MPU */\r
 141         ldm  r0!, {r1-r2}                                               /* Read from stack - r1 = PSPLIM and r2 = EXC_RETURN. */\r
 142         msr  psplim, r1                                                 /* Set this task's PSPLIM value. */\r
 143         movs r1, #2                                                             /* r1 = 2. */\r
 144         msr  CONTROL, r1                                                /* Switch to use PSP in the thread mode. */\r
 145         adds r0, #32                                                    /* Discard everything up to r0. */\r
 146         msr  psp, r0                                                    /* This is now the new top of stack to use in the task. */\r
 147         isb\r
 148         bx   r2                                                                 /* Finally, branch to EXC_RETURN. */\r
 149 #endif /* configENABLE_MPU */\r
 150 /*-----------------------------------------------------------*/\r
 151 \r
 152 vRaisePrivilege:\r
 153         mrs  r0, control                                                /* Read the CONTROL register. */\r
 154         movs r1, #1                                                             /* r1 = 1. */\r
 155         bics r0, r1                                                             /* Clear the bit 0. */\r
 156         msr  control, r0                                                /* Write back the new CONTROL value. */\r
 157         bx lr                                                                   /* Return to the caller. */\r
 158 /*-----------------------------------------------------------*/\r
 159 \r
 160 vStartFirstTask:\r
 161         ldr r0, =0xe000ed08                                             /* Use the NVIC offset register to locate the stack. */\r
 162         ldr r0, [r0]                                                    /* Read the VTOR register which gives the address of vector table. */\r
 163         ldr r0, [r0]                                                    /* The first entry in vector table is stack pointer. */\r
 164         msr msp, r0                                                             /* Set the MSP back to the start of the stack. */\r
 165         cpsie i                                                                 /* Globally enable interrupts. */\r
 166         dsb\r
 167         isb\r
 168         svc 2                                                                   /* System call to start the first task. portSVC_START_SCHEDULER = 2. */\r
 169         nop\r
 170 /*-----------------------------------------------------------*/\r
 171 \r
 172 ulSetInterruptMaskFromISR:\r
 173         mrs r0, PRIMASK\r
 174         cpsid i\r
 175         bx lr\r
 176 /*-----------------------------------------------------------*/\r
 177 \r
 178 vClearInterruptMaskFromISR:\r
 179         msr PRIMASK, r0\r
 180         bx lr\r
 181 /*-----------------------------------------------------------*/\r
 182 \r
 183 PendSV_Handler:\r
 184         mrs r0, psp                                                             /* Read PSP in r0. */\r
 185         ldr r2, =pxCurrentTCB                                   /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */\r
 186         ldr r1, [r2]                                                    /* Read pxCurrentTCB. */\r
 187 #if ( configENABLE_MPU == 1 )\r
 188         subs r0, r0, #44                                                /* Make space for PSPLIM, CONTROL, LR and the remaining registers on the stack. */\r
 189         str r0, [r1]                                                    /* Save the new top of stack in TCB. */\r
 190         mrs r1, psplim                                                  /* r1 = PSPLIM. */\r
 191         mrs r2, control                                                 /* r2 = CONTROL. */\r
 192         mov r3, lr                                                              /* r3 = LR/EXC_RETURN. */\r
 193         stmia r0!, {r1-r7}                                              /* Store on the stack - PSPLIM, CONTROL, LR and low registers that are not automatically saved. */\r
 194         mov r4, r8                                                              /* r4 = r8. */\r
 195         mov r5, r9                                                              /* r5 = r9. */\r
 196         mov r6, r10                                                             /* r6 = r10. */\r
 197         mov r7, r11                                                             /* r7 = r11. */\r
 198         stmia r0!, {r4-r7}                                              /* Store the high registers that are not saved automatically. */\r
 199 #else /* configENABLE_MPU */\r
 200         subs r0, r0, #40                                                /* Make space for PSPLIM, LR and the remaining registers on the stack. */\r
 201         str r0, [r1]                                                    /* Save the new top of stack in TCB. */\r
 202         mrs r2, psplim                                                  /* r2 = PSPLIM. */\r
 203         mov r3, lr                                                              /* r3 = LR/EXC_RETURN. */\r
 204         stmia r0!, {r2-r7}                                              /* Store on the stack - PSPLIM, LR and low registers that are not automatically saved. */\r
 205         mov r4, r8                                                              /* r4 = r8. */\r
 206         mov r5, r9                                                              /* r5 = r9. */\r
 207         mov r6, r10                                                             /* r6 = r10. */\r
 208         mov r7, r11                                                             /* r7 = r11. */\r
 209         stmia r0!, {r4-r7}                                              /* Store the high registers that are not saved automatically. */\r
 210 #endif /* configENABLE_MPU */\r
 211 \r
 212         cpsid i\r
 213         bl vTaskSwitchContext\r
 214         cpsie i\r
 215 \r
 216         ldr r2, =pxCurrentTCB                                   /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */\r
 217         ldr r1, [r2]                                                    /* Read pxCurrentTCB. */\r
 218         ldr r0, [r1]                                                    /* The first item in pxCurrentTCB is the task top of stack. r0 now points to the top of stack. */\r
 219 \r
 220 #if ( configENABLE_MPU == 1 )\r
 221         dmb                                                                             /* Complete outstanding transfers before disabling MPU. */\r
 222         ldr r2, =0xe000ed94                                             /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */\r
 223         ldr r3, [r2]                                                    /* Read the value of MPU_CTRL. */\r
 224         movs r4, #1                                                             /* r4 = 1. */\r
 225         bics r3, r4                                                             /* r3 = r3 & ~r4 i.e. Clear the bit 0 in r3. */\r
 226         str r3, [r2]                                                    /* Disable MPU. */\r
 227 \r
 228         adds r1, #4                                                             /* r1 = r1 + 4. r1 now points to MAIR0 in TCB. */\r
 229         ldr  r4, [r1]                                                   /* r4 = *r1 i.e. r4 = MAIR0. */\r
 230         ldr  r2, =0xe000edc0                                    /* r2 = 0xe000edc0 [Location of MAIR0]. */\r
 231         str  r4, [r2]                                                   /* Program MAIR0. */\r
 232         ldr  r2, =0xe000ed98                                    /* r2 = 0xe000ed98 [Location of RNR]. */\r
 233         adds r1, #4                                                             /* r1 = r1 + 4. r1 now points to first RBAR in TCB. */\r
 234         movs r4, #4                                                             /* r4 = 4. */\r
 235         str  r4, [r2]                                                   /* Program RNR = 4. */\r
 236         ldmia r1!, {r5,r6}                                              /* Read first set of RBAR/RLAR from TCB. */\r
 237         ldr  r3, =0xe000ed9c                                    /* r3 = 0xe000ed9c [Location of RBAR]. */\r
 238         stmia r3!, {r5,r6}                                              /* Write first set of RBAR/RLAR registers. */\r
 239         movs r4, #5                                                             /* r4 = 5. */\r
 240         str  r4, [r2]                                                   /* Program RNR = 5. */\r
 241         ldmia r1!, {r5,r6}                                              /* Read second set of RBAR/RLAR from TCB. */\r
 242         ldr  r3, =0xe000ed9c                                    /* r3 = 0xe000ed9c [Location of RBAR]. */\r
 243         stmia r3!, {r5,r6}                                              /* Write second set of RBAR/RLAR registers. */\r
 244         movs r4, #6                                                             /* r4 = 6. */\r
 245         str  r4, [r2]                                                   /* Program RNR = 6. */\r
 246         ldmia r1!, {r5,r6}                                              /* Read third set of RBAR/RLAR from TCB. */\r
 247         ldr  r3, =0xe000ed9c                                    /* r3 = 0xe000ed9c [Location of RBAR]. */\r
 248         stmia r3!, {r5,r6}                                              /* Write third set of RBAR/RLAR registers. */\r
 249         movs r4, #7                                                             /* r4 = 7. */\r
 250         str  r4, [r2]                                                   /* Program RNR = 7. */\r
 251         ldmia r1!, {r5,r6}                                              /* Read fourth set of RBAR/RLAR from TCB. */\r
 252         ldr  r3, =0xe000ed9c                                    /* r3 = 0xe000ed9c [Location of RBAR]. */\r
 253         stmia r3!, {r5,r6}                                              /* Write fourth set of RBAR/RLAR registers. */\r
 254 \r
 255         ldr r2, =0xe000ed94                                             /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */\r
 256         ldr r3, [r2]                                                    /* Read the value of MPU_CTRL. */\r
 257         movs r4, #1                                                             /* r4 = 1. */\r
 258         orrs r3, r4                                                             /* r3 = r3 | r4 i.e. Set the bit 0 in r3. */\r
 259         str r3, [r2]                                                    /* Enable MPU. */\r
 260         dsb                                                                             /* Force memory writes before continuing. */\r
 261 #endif /* configENABLE_MPU */\r
 262 \r
 263 #if ( configENABLE_MPU == 1 )\r
 264         adds r0, r0, #28                                                /* Move to the high registers. */\r
 265         ldmia r0!, {r4-r7}                                              /* Restore the high registers that are not automatically restored. */\r
 266         mov r8, r4                                                              /* r8 = r4. */\r
 267         mov r9, r5                                                              /* r9 = r5. */\r
 268         mov r10, r6                                                             /* r10 = r6. */\r
 269         mov r11, r7                                                             /* r11 = r7. */\r
 270         msr psp, r0                                                             /* Remember the new top of stack for the task. */\r
 271         subs r0, r0, #44                                                /* Move to the starting of the saved context. */\r
 272         ldmia r0!, {r1-r7}                                              /* Read from stack - r1 = PSPLIM, r2 = CONTROL, r3 = LR and r4-r7 restored. */\r
 273         msr psplim, r1                                                  /* Restore the PSPLIM register value for the task. */\r
 274         msr control, r2                                                 /* Restore the CONTROL register value for the task. */\r
 275         bx r3\r
 276 #else /* configENABLE_MPU */\r
 277         adds r0, r0, #24                                                /* Move to the high registers. */\r
 278         ldmia r0!, {r4-r7}                                              /* Restore the high registers that are not automatically restored. */\r
 279         mov r8, r4                                                              /* r8 = r4. */\r
 280         mov r9, r5                                                              /* r9 = r5. */\r
 281         mov r10, r6                                                             /* r10 = r6. */\r
 282         mov r11, r7                                                             /* r11 = r7. */\r
 283         msr psp, r0                                                             /* Remember the new top of stack for the task. */\r
 284         subs r0, r0, #40                                                /* Move to the starting of the saved context. */\r
 285         ldmia r0!, {r2-r7}                                              /* Read from stack - r2 = PSPLIM, r3 = LR and r4-r7 restored. */\r
 286         msr psplim, r2                                                  /* Restore the PSPLIM register value for the task. */\r
 287         bx r3\r
 288 #endif /* configENABLE_MPU */\r
 289 /*-----------------------------------------------------------*/\r
 290 \r
 291 SVC_Handler:\r
 292         movs r0, #4\r
 293         mov r1, lr\r
 294         tst r0, r1\r
 295         beq stacking_used_msp\r
 296         mrs r0, psp\r
 297         b vPortSVCHandler_C\r
 298         stacking_used_msp:\r
 299                 mrs r0, msp\r
 300                 b vPortSVCHandler_C\r
 301 /*-----------------------------------------------------------*/\r
 302 \r
 303         END\r