2 FreeRTOS V8.2.0 - Copyright (C) 2015 Real Time Engineers Ltd.
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5 VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
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7 This file is part of the FreeRTOS distribution.
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9 FreeRTOS is free software; you can redistribute it and/or modify it under
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10 the terms of the GNU General Public License (version 2) as published by the
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11 Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.
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13 ***************************************************************************
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14 >>! NOTE: The modification to the GPL is included to allow you to !<<
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15 >>! distribute a combined work that includes FreeRTOS without being !<<
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16 >>! obliged to provide the source code for proprietary components !<<
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17 >>! outside of the FreeRTOS kernel. !<<
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18 ***************************************************************************
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20 FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
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21 WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
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22 FOR A PARTICULAR PURPOSE. Full license text is available on the following
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23 link: http://www.freertos.org/a00114.html
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25 ***************************************************************************
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27 * FreeRTOS provides completely free yet professionally developed, *
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28 * robust, strictly quality controlled, supported, and cross *
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29 * platform software that is more than just the market leader, it *
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30 * is the industry's de facto standard. *
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32 * Help yourself get started quickly while simultaneously helping *
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33 * to support the FreeRTOS project by purchasing a FreeRTOS *
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34 * tutorial book, reference manual, or both: *
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35 * http://www.FreeRTOS.org/Documentation *
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37 ***************************************************************************
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39 http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading
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40 the FAQ page "My application does not run, what could be wrong?". Have you
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41 defined configASSERT()?
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43 http://www.FreeRTOS.org/support - In return for receiving this top quality
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44 embedded software for free we request you assist our global community by
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45 participating in the support forum.
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47 http://www.FreeRTOS.org/training - Investing in training allows your team to
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48 be as productive as possible as early as possible. Now you can receive
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49 FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers
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50 Ltd, and the world's leading authority on the world's leading RTOS.
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52 http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
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53 including FreeRTOS+Trace - an indispensable productivity tool, a DOS
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54 compatible FAT file system, and our tiny thread aware UDP/IP stack.
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56 http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.
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57 Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.
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59 http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High
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60 Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS
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61 licenses offer ticketed support, indemnification and commercial middleware.
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63 http://www.SafeRTOS.com - High Integrity Systems also provide a safety
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64 engineered and independently SIL3 certified version for use in safety and
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65 mission critical applications that require provable dependability.
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70 /* FreeRTOS includes. */
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71 #include "FreeRTOS.h"
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74 /*-----------------------------------------------------------*/
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76 /* Count of the critical section nesting depth. */
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77 uint32_t ulCriticalNesting = 9999;
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79 /*-----------------------------------------------------------*/
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81 /* Registers required to configure the RTI. */
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82 #define portRTI_GCTRL_REG ( * ( ( volatile uint32_t * ) 0xFFFFFC00 ) )
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83 #define portRTI_TBCTRL_REG ( * ( ( volatile uint32_t * ) 0xFFFFFC04 ) )
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84 #define portRTI_COMPCTRL_REG ( * ( ( volatile uint32_t * ) 0xFFFFFC0C ) )
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85 #define portRTI_CNT0_FRC0_REG ( * ( ( volatile uint32_t * ) 0xFFFFFC10 ) )
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86 #define portRTI_CNT0_UC0_REG ( * ( ( volatile uint32_t * ) 0xFFFFFC14 ) )
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87 #define portRTI_CNT0_CPUC0_REG ( * ( ( volatile uint32_t * ) 0xFFFFFC18 ) )
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88 #define portRTI_CNT0_COMP0_REG ( * ( ( volatile uint32_t * ) 0xFFFFFC50 ) )
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89 #define portRTI_CNT0_UDCP0_REG ( * ( ( volatile uint32_t * ) 0xFFFFFC54 ) )
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90 #define portRTI_SETINTENA_REG ( * ( ( volatile uint32_t * ) 0xFFFFFC80 ) )
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91 #define portRTI_CLEARINTENA_REG ( * ( ( volatile uint32_t * ) 0xFFFFFC84 ) )
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92 #define portRTI_INTFLAG_REG ( * ( ( volatile uint32_t * ) 0xFFFFFC88 ) )
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95 /* Constants required to set up the initial stack of each task. */
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96 #define portINITIAL_SPSR ( ( StackType_t ) 0x1F )
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97 #define portINITIAL_FPSCR ( ( StackType_t ) 0x00 )
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98 #define portINSTRUCTION_SIZE ( ( StackType_t ) 0x04 )
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99 #define portTHUMB_MODE_BIT ( ( StackType_t ) 0x20 )
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101 /* The number of words on the stack frame between the saved Top Of Stack and
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102 R0 (in which the parameters are passed. */
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103 #define portSPACE_BETWEEN_TOS_AND_PARAMETERS ( 12 )
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105 /*-----------------------------------------------------------*/
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107 /* vPortStartFirstSTask() is defined in portASM.asm */
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108 extern void vPortStartFirstTask( void );
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110 /*-----------------------------------------------------------*/
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112 /* Saved as part of the task context. Set to pdFALSE if the task does not
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113 require an FPU context. */
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114 uint32_t ulTaskHasFPUContext = 0;
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116 /*-----------------------------------------------------------*/
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120 * See header file for description.
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122 StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
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124 StackType_t *pxOriginalTOS;
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126 pxOriginalTOS = pxTopOfStack;
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128 #if __TI_VFP_SUPPORT__
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130 /* Ensure the stack is correctly aligned on exit. */
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135 /* Setup the initial stack of the task. The stack is set exactly as
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136 expected by the portRESTORE_CONTEXT() macro. */
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138 /* First on the stack is the return address - which is the start of the as
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139 the task has not executed yet. The offset is added to make the return
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140 address appear as it would within an IRQ ISR. */
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141 *pxTopOfStack = ( StackType_t ) pxCode + portINSTRUCTION_SIZE;
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144 *pxTopOfStack = ( StackType_t ) 0x00000000; /* R14 */
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146 *pxTopOfStack = ( StackType_t ) pxOriginalTOS; /* Stack used when task starts goes in R13. */
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149 #ifdef portPRELOAD_TASK_REGISTERS
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151 *pxTopOfStack = ( StackType_t ) 0x12121212; /* R12 */
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153 *pxTopOfStack = ( StackType_t ) 0x11111111; /* R11 */
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155 *pxTopOfStack = ( StackType_t ) 0x10101010; /* R10 */
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157 *pxTopOfStack = ( StackType_t ) 0x09090909; /* R9 */
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159 *pxTopOfStack = ( StackType_t ) 0x08080808; /* R8 */
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161 *pxTopOfStack = ( StackType_t ) 0x07070707; /* R7 */
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163 *pxTopOfStack = ( StackType_t ) 0x06060606; /* R6 */
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165 *pxTopOfStack = ( StackType_t ) 0x05050505; /* R5 */
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167 *pxTopOfStack = ( StackType_t ) 0x04040404; /* R4 */
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169 *pxTopOfStack = ( StackType_t ) 0x03030303; /* R3 */
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171 *pxTopOfStack = ( StackType_t ) 0x02020202; /* R2 */
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173 *pxTopOfStack = ( StackType_t ) 0x01010101; /* R1 */
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178 pxTopOfStack -= portSPACE_BETWEEN_TOS_AND_PARAMETERS;
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182 /* Function parameters are passed in R0. */
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183 *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
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186 /* Set the status register for system mode, with interrupts enabled. */
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187 *pxTopOfStack = ( StackType_t ) ( ( _get_CPSR() & ~0xFF ) | portINITIAL_SPSR );
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189 if( ( ( uint32_t ) pxCode & 0x01UL ) != 0x00 )
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191 /* The task will start in thumb mode. */
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192 *pxTopOfStack |= portTHUMB_MODE_BIT;
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195 #ifdef __TI_VFP_SUPPORT__
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199 /* The last thing on the stack is the tasks ulUsingFPU value, which by
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200 default is set to indicate that the stack frame does not include FPU
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202 *pxTopOfStack = pdFALSE;
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206 return pxTopOfStack;
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208 /*-----------------------------------------------------------*/
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210 static void prvSetupTimerInterrupt(void)
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212 /* Disable timer 0. */
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213 portRTI_GCTRL_REG &= 0xFFFFFFFEUL;
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215 /* Use the internal counter. */
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216 portRTI_TBCTRL_REG = 0x00000000U;
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218 /* COMPSEL0 will use the RTIFRC0 counter. */
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219 portRTI_COMPCTRL_REG = 0x00000000U;
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221 /* Initialise the counter and the prescale counter registers. */
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222 portRTI_CNT0_UC0_REG = 0x00000000U;
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223 portRTI_CNT0_FRC0_REG = 0x00000000U;
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225 /* Set Prescalar for RTI clock. */
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226 portRTI_CNT0_CPUC0_REG = 0x00000001U;
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227 portRTI_CNT0_COMP0_REG = ( configCPU_CLOCK_HZ / 2 ) / configTICK_RATE_HZ;
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228 portRTI_CNT0_UDCP0_REG = ( configCPU_CLOCK_HZ / 2 ) / configTICK_RATE_HZ;
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230 /* Clear interrupts. */
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231 portRTI_INTFLAG_REG = 0x0007000FU;
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232 portRTI_CLEARINTENA_REG = 0x00070F0FU;
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234 /* Enable the compare 0 interrupt. */
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235 portRTI_SETINTENA_REG = 0x00000001U;
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236 portRTI_GCTRL_REG |= 0x00000001U;
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238 /*-----------------------------------------------------------*/
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241 * See header file for description.
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243 BaseType_t xPortStartScheduler(void)
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245 /* Start the timer that generates the tick ISR. */
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246 prvSetupTimerInterrupt();
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248 /* Reset the critical section nesting count read to execute the first task. */
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249 ulCriticalNesting = 0;
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251 /* Start the first task. This is done from portASM.asm as ARM mode must be
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253 vPortStartFirstTask();
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255 /* Should not get here! */
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258 /*-----------------------------------------------------------*/
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261 * See header file for description.
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263 void vPortEndScheduler(void)
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265 /* Not implemented in ports where there is nothing to return to.
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266 Artificially force an assert. */
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267 configASSERT( ulCriticalNesting == 1000UL );
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269 /*-----------------------------------------------------------*/
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271 #if configUSE_PREEMPTION == 0
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273 /* The cooperative scheduler requires a normal IRQ service routine to
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274 * simply increment the system tick. */
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275 __interrupt void vPortNonPreemptiveTick( void )
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277 /* clear clock interrupt flag */
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278 portRTI_INTFLAG_REG = 0x00000001;
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280 /* Increment the tick count - this may make a delaying task ready
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281 to run - but a context switch is not performed. */
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282 xTaskIncrementTick();
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288 **************************************************************************
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289 * The preemptive scheduler ISR is written in assembler and can be found
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290 * in the portASM.asm file. This will only get used if portUSE_PREEMPTION
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291 * is set to 1 in portmacro.h
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292 **************************************************************************
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294 void vPortPreemptiveTick( void );
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297 /*-----------------------------------------------------------*/
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301 * Disable interrupts, and keep a count of the nesting depth.
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303 void vPortEnterCritical( void )
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305 /* Disable interrupts as per portDISABLE_INTERRUPTS(); */
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306 portDISABLE_INTERRUPTS();
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308 /* Now interrupts are disabled ulCriticalNesting can be accessed
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309 directly. Increment ulCriticalNesting to keep a count of how many times
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310 portENTER_CRITICAL() has been called. */
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311 ulCriticalNesting++;
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313 /*-----------------------------------------------------------*/
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316 * Decrement the critical nesting count, and if it has reached zero, re-enable
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319 void vPortExitCritical( void )
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321 if( ulCriticalNesting > 0 )
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323 /* Decrement the nesting count as we are leaving a critical section. */
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324 ulCriticalNesting--;
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326 /* If the nesting level has reached zero then interrupts should be
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328 if( ulCriticalNesting == 0 )
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330 /* Enable interrupts as per portENABLE_INTERRUPTS(). */
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331 portENABLE_INTERRUPTS();
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335 /*-----------------------------------------------------------*/
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337 #if __TI_VFP_SUPPORT__
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339 void vPortTaskUsesFPU( void )
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341 extern void vPortInitialiseFPSCR( void );
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343 /* A task is registering the fact that it needs an FPU context. Set the
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344 FPU flag (saved as part of the task context. */
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345 ulTaskHasFPUContext = pdTRUE;
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347 /* Initialise the floating point status register. */
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348 vPortInitialiseFPSCR();
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351 #endif /* __TI_VFP_SUPPORT__ */
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353 /*-----------------------------------------------------------*/
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