2 * FreeRTOS Kernel V10.0.1
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3 * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved.
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5 * Permission is hereby granted, free of charge, to any person obtaining a copy of
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6 * this software and associated documentation files (the "Software"), to deal in
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7 * the Software without restriction, including without limitation the rights to
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8 * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
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9 * the Software, and to permit persons to whom the Software is furnished to do so,
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10 * subject to the following conditions:
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12 * The above copyright notice and this permission notice shall be included in all
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13 * copies or substantial portions of the Software.
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15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
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17 * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
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18 * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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19 * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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20 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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22 * http://www.FreeRTOS.org
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23 * http://aws.amazon.com/freertos
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25 * 1 tab == 4 spaces!
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28 /* FreeRTOS includes. */
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29 #include "FreeRTOS.h"
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32 /*-----------------------------------------------------------*/
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34 /* Count of the critical section nesting depth. */
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35 uint32_t ulCriticalNesting = 9999;
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37 /*-----------------------------------------------------------*/
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39 /* Registers required to configure the RTI. */
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40 #define portRTI_GCTRL_REG ( * ( ( volatile uint32_t * ) 0xFFFFFC00 ) )
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41 #define portRTI_TBCTRL_REG ( * ( ( volatile uint32_t * ) 0xFFFFFC04 ) )
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42 #define portRTI_COMPCTRL_REG ( * ( ( volatile uint32_t * ) 0xFFFFFC0C ) )
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43 #define portRTI_CNT0_FRC0_REG ( * ( ( volatile uint32_t * ) 0xFFFFFC10 ) )
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44 #define portRTI_CNT0_UC0_REG ( * ( ( volatile uint32_t * ) 0xFFFFFC14 ) )
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45 #define portRTI_CNT0_CPUC0_REG ( * ( ( volatile uint32_t * ) 0xFFFFFC18 ) )
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46 #define portRTI_CNT0_COMP0_REG ( * ( ( volatile uint32_t * ) 0xFFFFFC50 ) )
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47 #define portRTI_CNT0_UDCP0_REG ( * ( ( volatile uint32_t * ) 0xFFFFFC54 ) )
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48 #define portRTI_SETINTENA_REG ( * ( ( volatile uint32_t * ) 0xFFFFFC80 ) )
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49 #define portRTI_CLEARINTENA_REG ( * ( ( volatile uint32_t * ) 0xFFFFFC84 ) )
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50 #define portRTI_INTFLAG_REG ( * ( ( volatile uint32_t * ) 0xFFFFFC88 ) )
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53 /* Constants required to set up the initial stack of each task. */
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54 #define portINITIAL_SPSR ( ( StackType_t ) 0x1F )
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55 #define portINITIAL_FPSCR ( ( StackType_t ) 0x00 )
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56 #define portINSTRUCTION_SIZE ( ( StackType_t ) 0x04 )
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57 #define portTHUMB_MODE_BIT ( ( StackType_t ) 0x20 )
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59 /* The number of words on the stack frame between the saved Top Of Stack and
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60 R0 (in which the parameters are passed. */
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61 #define portSPACE_BETWEEN_TOS_AND_PARAMETERS ( 12 )
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63 /*-----------------------------------------------------------*/
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65 /* vPortStartFirstSTask() is defined in portASM.asm */
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66 extern void vPortStartFirstTask( void );
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68 /*-----------------------------------------------------------*/
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70 /* Saved as part of the task context. Set to pdFALSE if the task does not
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71 require an FPU context. */
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72 uint32_t ulTaskHasFPUContext = 0;
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74 /*-----------------------------------------------------------*/
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78 * See header file for description.
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80 StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
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82 StackType_t *pxOriginalTOS;
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84 pxOriginalTOS = pxTopOfStack;
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86 #if __TI_VFP_SUPPORT__
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88 /* Ensure the stack is correctly aligned on exit. */
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93 /* Setup the initial stack of the task. The stack is set exactly as
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94 expected by the portRESTORE_CONTEXT() macro. */
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96 /* First on the stack is the return address - which is the start of the as
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97 the task has not executed yet. The offset is added to make the return
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98 address appear as it would within an IRQ ISR. */
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99 *pxTopOfStack = ( StackType_t ) pxCode + portINSTRUCTION_SIZE;
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102 *pxTopOfStack = ( StackType_t ) 0x00000000; /* R14 */
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104 *pxTopOfStack = ( StackType_t ) pxOriginalTOS; /* Stack used when task starts goes in R13. */
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107 #ifdef portPRELOAD_TASK_REGISTERS
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109 *pxTopOfStack = ( StackType_t ) 0x12121212; /* R12 */
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111 *pxTopOfStack = ( StackType_t ) 0x11111111; /* R11 */
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113 *pxTopOfStack = ( StackType_t ) 0x10101010; /* R10 */
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115 *pxTopOfStack = ( StackType_t ) 0x09090909; /* R9 */
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117 *pxTopOfStack = ( StackType_t ) 0x08080808; /* R8 */
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119 *pxTopOfStack = ( StackType_t ) 0x07070707; /* R7 */
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121 *pxTopOfStack = ( StackType_t ) 0x06060606; /* R6 */
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123 *pxTopOfStack = ( StackType_t ) 0x05050505; /* R5 */
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125 *pxTopOfStack = ( StackType_t ) 0x04040404; /* R4 */
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127 *pxTopOfStack = ( StackType_t ) 0x03030303; /* R3 */
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129 *pxTopOfStack = ( StackType_t ) 0x02020202; /* R2 */
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131 *pxTopOfStack = ( StackType_t ) 0x01010101; /* R1 */
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136 pxTopOfStack -= portSPACE_BETWEEN_TOS_AND_PARAMETERS;
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140 /* Function parameters are passed in R0. */
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141 *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
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144 /* Set the status register for system mode, with interrupts enabled. */
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145 *pxTopOfStack = ( StackType_t ) ( ( _get_CPSR() & ~0xFF ) | portINITIAL_SPSR );
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147 if( ( ( uint32_t ) pxCode & 0x01UL ) != 0x00 )
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149 /* The task will start in thumb mode. */
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150 *pxTopOfStack |= portTHUMB_MODE_BIT;
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153 #ifdef __TI_VFP_SUPPORT__
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157 /* The last thing on the stack is the tasks ulUsingFPU value, which by
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158 default is set to indicate that the stack frame does not include FPU
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160 *pxTopOfStack = pdFALSE;
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164 return pxTopOfStack;
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166 /*-----------------------------------------------------------*/
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168 static void prvSetupTimerInterrupt(void)
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170 /* Disable timer 0. */
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171 portRTI_GCTRL_REG &= 0xFFFFFFFEUL;
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173 /* Use the internal counter. */
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174 portRTI_TBCTRL_REG = 0x00000000U;
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176 /* COMPSEL0 will use the RTIFRC0 counter. */
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177 portRTI_COMPCTRL_REG = 0x00000000U;
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179 /* Initialise the counter and the prescale counter registers. */
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180 portRTI_CNT0_UC0_REG = 0x00000000U;
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181 portRTI_CNT0_FRC0_REG = 0x00000000U;
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183 /* Set Prescalar for RTI clock. */
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184 portRTI_CNT0_CPUC0_REG = 0x00000001U;
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185 portRTI_CNT0_COMP0_REG = ( configCPU_CLOCK_HZ / 2 ) / configTICK_RATE_HZ;
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186 portRTI_CNT0_UDCP0_REG = ( configCPU_CLOCK_HZ / 2 ) / configTICK_RATE_HZ;
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188 /* Clear interrupts. */
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189 portRTI_INTFLAG_REG = 0x0007000FU;
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190 portRTI_CLEARINTENA_REG = 0x00070F0FU;
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192 /* Enable the compare 0 interrupt. */
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193 portRTI_SETINTENA_REG = 0x00000001U;
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194 portRTI_GCTRL_REG |= 0x00000001U;
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196 /*-----------------------------------------------------------*/
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199 * See header file for description.
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201 BaseType_t xPortStartScheduler(void)
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203 /* Start the timer that generates the tick ISR. */
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204 prvSetupTimerInterrupt();
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206 /* Reset the critical section nesting count read to execute the first task. */
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207 ulCriticalNesting = 0;
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209 /* Start the first task. This is done from portASM.asm as ARM mode must be
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211 vPortStartFirstTask();
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213 /* Should not get here! */
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216 /*-----------------------------------------------------------*/
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219 * See header file for description.
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221 void vPortEndScheduler(void)
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223 /* Not implemented in ports where there is nothing to return to.
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224 Artificially force an assert. */
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225 configASSERT( ulCriticalNesting == 1000UL );
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227 /*-----------------------------------------------------------*/
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229 #if configUSE_PREEMPTION == 0
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231 /* The cooperative scheduler requires a normal IRQ service routine to
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232 * simply increment the system tick. */
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233 __interrupt void vPortNonPreemptiveTick( void )
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235 /* clear clock interrupt flag */
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236 portRTI_INTFLAG_REG = 0x00000001;
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238 /* Increment the tick count - this may make a delaying task ready
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239 to run - but a context switch is not performed. */
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240 xTaskIncrementTick();
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246 **************************************************************************
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247 * The preemptive scheduler ISR is written in assembler and can be found
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248 * in the portASM.asm file. This will only get used if portUSE_PREEMPTION
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249 * is set to 1 in portmacro.h
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250 **************************************************************************
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252 void vPortPreemptiveTick( void );
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255 /*-----------------------------------------------------------*/
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259 * Disable interrupts, and keep a count of the nesting depth.
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261 void vPortEnterCritical( void )
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263 /* Disable interrupts as per portDISABLE_INTERRUPTS(); */
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264 portDISABLE_INTERRUPTS();
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266 /* Now interrupts are disabled ulCriticalNesting can be accessed
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267 directly. Increment ulCriticalNesting to keep a count of how many times
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268 portENTER_CRITICAL() has been called. */
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269 ulCriticalNesting++;
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271 /*-----------------------------------------------------------*/
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274 * Decrement the critical nesting count, and if it has reached zero, re-enable
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277 void vPortExitCritical( void )
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279 if( ulCriticalNesting > 0 )
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281 /* Decrement the nesting count as we are leaving a critical section. */
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282 ulCriticalNesting--;
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284 /* If the nesting level has reached zero then interrupts should be
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286 if( ulCriticalNesting == 0 )
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288 /* Enable interrupts as per portENABLE_INTERRUPTS(). */
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289 portENABLE_INTERRUPTS();
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293 /*-----------------------------------------------------------*/
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295 #if __TI_VFP_SUPPORT__
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297 void vPortTaskUsesFPU( void )
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299 extern void vPortInitialiseFPSCR( void );
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301 /* A task is registering the fact that it needs an FPU context. Set the
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302 FPU flag (saved as part of the task context. */
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303 ulTaskHasFPUContext = pdTRUE;
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305 /* Initialise the floating point status register. */
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306 vPortInitialiseFPSCR();
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309 #endif /* __TI_VFP_SUPPORT__ */
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311 /*-----------------------------------------------------------*/
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