2 FreeRTOS V7.3.0 - Copyright (C) 2012 Real Time Engineers Ltd.
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4 FEATURES AND PORTS ARE ADDED TO FREERTOS ALL THE TIME. PLEASE VISIT
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5 http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
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7 ***************************************************************************
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9 * FreeRTOS tutorial books are available in pdf and paperback. *
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10 * Complete, revised, and edited pdf reference manuals are also *
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13 * Purchasing FreeRTOS documentation will not only help you, by *
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14 * ensuring you get running as quickly as possible and with an *
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15 * in-depth knowledge of how to use FreeRTOS, it will also help *
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16 * the FreeRTOS project to continue with its mission of providing *
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17 * professional grade, cross platform, de facto standard solutions *
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18 * for microcontrollers - completely free of charge! *
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20 * >>> See http://www.FreeRTOS.org/Documentation for details. <<< *
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22 * Thank you for using FreeRTOS, and thank you for your support! *
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24 ***************************************************************************
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27 This file is part of the FreeRTOS distribution.
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29 FreeRTOS is free software; you can redistribute it and/or modify it under
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30 the terms of the GNU General Public License (version 2) as published by the
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31 Free Software Foundation AND MODIFIED BY the FreeRTOS exception.
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32 >>>NOTE<<< The modification to the GPL is included to allow you to
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33 distribute a combined work that includes FreeRTOS without being obliged to
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34 provide the source code for proprietary components outside of the FreeRTOS
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35 kernel. FreeRTOS is distributed in the hope that it will be useful, but
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36 WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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37 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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38 more details. You should have received a copy of the GNU General Public
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39 License and the FreeRTOS license exception along with FreeRTOS; if not it
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40 can be viewed here: http://www.freertos.org/a00114.html and also obtained
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41 by writing to Richard Barry, contact details for whom are available on the
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46 ***************************************************************************
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48 * Having a problem? Start by reading the FAQ "My application does *
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49 * not run, what could be wrong?" *
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51 * http://www.FreeRTOS.org/FAQHelp.html *
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53 ***************************************************************************
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56 http://www.FreeRTOS.org - Documentation, training, latest versions, license
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57 and contact details.
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59 http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
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60 including FreeRTOS+Trace - an indispensable productivity tool.
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62 Real Time Engineers ltd license FreeRTOS to High Integrity Systems, who sell
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63 the code with commercial support, indemnification, and middleware, under
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64 the OpenRTOS brand: http://www.OpenRTOS.com. High Integrity Systems also
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65 provide a safety engineered and independently SIL3 certified version under
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66 the SafeRTOS brand: http://www.SafeRTOS.com.
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69 /* FreeRTOS includes. */
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70 #include "FreeRTOS.h"
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73 /*-----------------------------------------------------------*/
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75 /* Count of the critical section nesting depth. */
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76 unsigned portLONG ulCriticalNesting = 9999;
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78 /*-----------------------------------------------------------*/
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80 /* Registers required to configure the RTI. */
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81 #define portRTI_GCTRL_REG ( * ( ( volatile unsigned long * ) 0xFFFFFC00 ) )
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82 #define portRTI_TBCTRL_REG ( * ( ( volatile unsigned long * ) 0xFFFFFC04 ) )
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83 #define portRTI_COMPCTRL_REG ( * ( ( volatile unsigned long * ) 0xFFFFFC0C ) )
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84 #define portRTI_CNT0_FRC0_REG ( * ( ( volatile unsigned long * ) 0xFFFFFC10 ) )
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85 #define portRTI_CNT0_UC0_REG ( * ( ( volatile unsigned long * ) 0xFFFFFC14 ) )
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86 #define portRTI_CNT0_CPUC0_REG ( * ( ( volatile unsigned long * ) 0xFFFFFC18 ) )
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87 #define portRTI_CNT0_COMP0_REG ( * ( ( volatile unsigned long * ) 0xFFFFFC50 ) )
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88 #define portRTI_CNT0_UDCP0_REG ( * ( ( volatile unsigned long * ) 0xFFFFFC54 ) )
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89 #define portRTI_SETINTENA_REG ( * ( ( volatile unsigned long * ) 0xFFFFFC80 ) )
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90 #define portRTI_CLEARINTENA_REG ( * ( ( volatile unsigned long * ) 0xFFFFFC84 ) )
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91 #define portRTI_INTFLAG_REG ( * ( ( volatile unsigned long * ) 0xFFFFFC88 ) )
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94 /* Constants required to set up the initial stack of each task. */
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95 #define portINITIAL_SPSR ( ( portSTACK_TYPE ) 0x1F )
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96 #define portINITIAL_FPSCR ( ( portSTACK_TYPE ) 0x00 )
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97 #define portINSTRUCTION_SIZE ( ( portSTACK_TYPE ) 0x04 )
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98 #define portTHUMB_MODE_BIT ( ( portSTACK_TYPE ) 0x20 )
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100 /* The number of words on the stack frame between the saved Top Of Stack and
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101 R0 (in which the parameters are passed. */
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102 #define portSPACE_BETWEEN_TOS_AND_PARAMETERS ( 12 )
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104 /*-----------------------------------------------------------*/
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106 /* vPortStartFirstSTask() is defined in portASM.asm */
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107 extern void vPortStartFirstTask( void );
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109 /*-----------------------------------------------------------*/
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111 /* Saved as part of the task context. Set to pdFALSE if the task does not
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112 require an FPU context. */
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113 unsigned long ulTaskHasFPUContext = 0;
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115 /*-----------------------------------------------------------*/
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119 * See header file for description.
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121 portSTACK_TYPE *pxPortInitialiseStack( portSTACK_TYPE *pxTopOfStack, pdTASK_CODE pxCode, void *pvParameters )
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123 portSTACK_TYPE *pxOriginalTOS;
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125 pxOriginalTOS = pxTopOfStack;
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127 #if __TI_VFP_SUPPORT__
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129 /* Ensure the stack is correctly aligned on exit. */
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134 /* Setup the initial stack of the task. The stack is set exactly as
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135 expected by the portRESTORE_CONTEXT() macro. */
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137 /* First on the stack is the return address - which is the start of the as
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138 the task has not executed yet. The offset is added to make the return
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139 address appear as it would within an IRQ ISR. */
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140 *pxTopOfStack = ( portSTACK_TYPE ) pxCode + portINSTRUCTION_SIZE;
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143 *pxTopOfStack = ( portSTACK_TYPE ) 0x00000000; /* R14 */
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145 *pxTopOfStack = ( portSTACK_TYPE ) pxOriginalTOS; /* Stack used when task starts goes in R13. */
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148 #ifdef portPRELOAD_TASK_REGISTERS
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150 *pxTopOfStack = ( portSTACK_TYPE ) 0x12121212; /* R12 */
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152 *pxTopOfStack = ( portSTACK_TYPE ) 0x11111111; /* R11 */
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154 *pxTopOfStack = ( portSTACK_TYPE ) 0x10101010; /* R10 */
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156 *pxTopOfStack = ( portSTACK_TYPE ) 0x09090909; /* R9 */
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158 *pxTopOfStack = ( portSTACK_TYPE ) 0x08080808; /* R8 */
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160 *pxTopOfStack = ( portSTACK_TYPE ) 0x07070707; /* R7 */
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162 *pxTopOfStack = ( portSTACK_TYPE ) 0x06060606; /* R6 */
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164 *pxTopOfStack = ( portSTACK_TYPE ) 0x05050505; /* R5 */
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166 *pxTopOfStack = ( portSTACK_TYPE ) 0x04040404; /* R4 */
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168 *pxTopOfStack = ( portSTACK_TYPE ) 0x03030303; /* R3 */
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170 *pxTopOfStack = ( portSTACK_TYPE ) 0x02020202; /* R2 */
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172 *pxTopOfStack = ( portSTACK_TYPE ) 0x01010101; /* R1 */
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177 pxTopOfStack -= portSPACE_BETWEEN_TOS_AND_PARAMETERS;
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181 /* Function parameters are passed in R0. */
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182 *pxTopOfStack = ( portSTACK_TYPE ) pvParameters; /* R0 */
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185 /* Set the status register for system mode, with interrupts enabled. */
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186 *pxTopOfStack = ( portSTACK_TYPE ) ( ( _get_CPSR() & ~0xFF ) | portINITIAL_SPSR );
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188 if( ( ( unsigned long ) pxCode & 0x01UL ) != 0x00 )
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190 /* The task will start in thumb mode. */
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191 *pxTopOfStack |= portTHUMB_MODE_BIT;
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194 #ifdef __TI_VFP_SUPPORT__
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198 /* The last thing on the stack is the tasks ulUsingFPU value, which by
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199 default is set to indicate that the stack frame does not include FPU
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201 *pxTopOfStack = pdFALSE;
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205 return pxTopOfStack;
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207 /*-----------------------------------------------------------*/
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209 static void prvSetupTimerInterrupt(void)
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211 /* Disable timer 0. */
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212 portRTI_GCTRL_REG &= 0xFFFFFFFEUL;
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214 /* Use the internal counter. */
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215 portRTI_TBCTRL_REG = 0x00000000U;
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217 /* COMPSEL0 will use the RTIFRC0 counter. */
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218 portRTI_COMPCTRL_REG = 0x00000000U;
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220 /* Initialise the counter and the prescale counter registers. */
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221 portRTI_CNT0_UC0_REG = 0x00000000U;
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222 portRTI_CNT0_FRC0_REG = 0x00000000U;
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224 /* Set Prescalar for RTI clock. */
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225 portRTI_CNT0_CPUC0_REG = 0x00000001U;
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226 portRTI_CNT0_COMP0_REG = ( configCPU_CLOCK_HZ / 2 ) / configTICK_RATE_HZ;
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227 portRTI_CNT0_UDCP0_REG = ( configCPU_CLOCK_HZ / 2 ) / configTICK_RATE_HZ;
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229 /* Clear interrupts. */
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230 portRTI_INTFLAG_REG = 0x0007000FU;
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231 portRTI_CLEARINTENA_REG = 0x00070F0FU;
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233 /* Enable the compare 0 interrupt. */
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234 portRTI_SETINTENA_REG = 0x00000001U;
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235 portRTI_GCTRL_REG |= 0x00000001U;
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237 /*-----------------------------------------------------------*/
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240 * See header file for description.
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242 portBASE_TYPE xPortStartScheduler(void)
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244 /* Start the timer that generates the tick ISR. */
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245 prvSetupTimerInterrupt();
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247 /* Reset the critical section nesting count read to execute the first task. */
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248 ulCriticalNesting = 0;
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250 /* Start the first task. This is done from portASM.asm as ARM mode must be
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252 vPortStartFirstTask();
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254 /* Should not get here! */
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257 /*-----------------------------------------------------------*/
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260 * See header file for description.
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262 void vPortEndScheduler(void)
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264 /* It is unlikely that the port will require this function as there
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265 is nothing to return to. */
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267 /*-----------------------------------------------------------*/
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269 #if configUSE_PREEMPTION == 0
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271 /* The cooperative scheduler requires a normal IRQ service routine to
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272 * simply increment the system tick. */
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273 __interrupt void vPortNonPreemptiveTick( void )
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275 /* clear clock interrupt flag */
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276 RTI->INTFLAG = 0x00000001;
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278 /* Increment the tick count - this may make a delaying task ready
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279 to run - but a context switch is not performed. */
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280 vTaskIncrementTick();
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286 **************************************************************************
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287 * The preemptive scheduler ISR is written in assembler and can be found
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288 * in the portASM.asm file. This will only get used if portUSE_PREEMPTION
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289 * is set to 1 in portmacro.h
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290 **************************************************************************
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292 void vPortPreemptiveTick( void );
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295 /*-----------------------------------------------------------*/
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299 * Disable interrupts, and keep a count of the nesting depth.
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301 void vPortEnterCritical( void )
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303 /* Disable interrupts as per portDISABLE_INTERRUPTS(); */
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304 portDISABLE_INTERRUPTS();
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306 /* Now interrupts are disabled ulCriticalNesting can be accessed
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307 directly. Increment ulCriticalNesting to keep a count of how many times
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308 portENTER_CRITICAL() has been called. */
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309 ulCriticalNesting++;
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311 /*-----------------------------------------------------------*/
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314 * Decrement the critical nesting count, and if it has reached zero, re-enable
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317 void vPortExitCritical( void )
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319 if( ulCriticalNesting > 0 )
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321 /* Decrement the nesting count as we are leaving a critical section. */
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322 ulCriticalNesting--;
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324 /* If the nesting level has reached zero then interrupts should be
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326 if( ulCriticalNesting == 0 )
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328 /* Enable interrupts as per portENABLE_INTERRUPTS(). */
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329 portENABLE_INTERRUPTS();
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333 /*-----------------------------------------------------------*/
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335 #if __TI_VFP_SUPPORT__
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337 void vPortTaskUsesFPU( void )
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339 extern void vPortInitialiseFPSCR( void );
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341 /* A task is registering the fact that it needs an FPU context. Set the
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342 FPU flag (saved as part of the task context. */
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343 ulTaskHasFPUContext = pdTRUE;
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345 /* Initialise the floating point status register. */
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346 vPortInitialiseFPSCR();
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349 #endif /* __TI_VFP_SUPPORT__ */
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351 /*-----------------------------------------------------------*/
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