2 FreeRTOS V7.5.2 - Copyright (C) 2013 Real Time Engineers Ltd.
\r
4 VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
\r
6 ***************************************************************************
\r
8 * FreeRTOS provides completely free yet professionally developed, *
\r
9 * robust, strictly quality controlled, supported, and cross *
\r
10 * platform software that has become a de facto standard. *
\r
12 * Help yourself get started quickly and support the FreeRTOS *
\r
13 * project by purchasing a FreeRTOS tutorial book, reference *
\r
14 * manual, or both from: http://www.FreeRTOS.org/Documentation *
\r
18 ***************************************************************************
\r
20 This file is part of the FreeRTOS distribution.
\r
22 FreeRTOS is free software; you can redistribute it and/or modify it under
\r
23 the terms of the GNU General Public License (version 2) as published by the
\r
24 Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.
\r
26 >>! NOTE: The modification to the GPL is included to allow you to distribute
\r
27 >>! a combined work that includes FreeRTOS without being obliged to provide
\r
28 >>! the source code for proprietary components outside of the FreeRTOS
\r
31 FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
\r
32 WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
\r
33 FOR A PARTICULAR PURPOSE. Full license text is available from the following
\r
34 link: http://www.freertos.org/a00114.html
\r
38 ***************************************************************************
\r
40 * Having a problem? Start by reading the FAQ "My application does *
\r
41 * not run, what could be wrong?" *
\r
43 * http://www.FreeRTOS.org/FAQHelp.html *
\r
45 ***************************************************************************
\r
47 http://www.FreeRTOS.org - Documentation, books, training, latest versions,
\r
48 license and Real Time Engineers Ltd. contact details.
\r
50 http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
\r
51 including FreeRTOS+Trace - an indispensable productivity tool, a DOS
\r
52 compatible FAT file system, and our tiny thread aware UDP/IP stack.
\r
54 http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High
\r
55 Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS
\r
56 licenses offer ticketed support, indemnification and middleware.
\r
58 http://www.SafeRTOS.com - High Integrity Systems also provide a safety
\r
59 engineered and independently SIL3 certified version for use in safety and
\r
60 mission critical applications that require provable dependability.
\r
66 /*-----------------------------------------------------------
\r
67 * Implementation of functions defined in portable.h for the Atmel AT91R40008
\r
70 * Components that can be compiled to either ARM or THUMB mode are
\r
71 * contained in this file. The ISR routines, which can only be compiled
\r
72 * to ARM mode are contained in portISR.c.
\r
73 *----------------------------------------------------------*/
\r
75 /* Standard includes. */
\r
78 /* Scheduler includes. */
\r
79 #include "FreeRTOS.h"
\r
82 /* Hardware specific definitions. */
\r
83 #include "AT91R40008.h"
\r
88 /* Constants required to setup the task context. */
\r
89 #define portINITIAL_SPSR ( ( portSTACK_TYPE ) 0x1f ) /* System mode, ARM mode, interrupts enabled. */
\r
90 #define portTHUMB_MODE_BIT ( ( portSTACK_TYPE ) 0x20 )
\r
91 #define portINSTRUCTION_SIZE ( ( portSTACK_TYPE ) 4 )
\r
92 #define portNO_CRITICAL_SECTION_NESTING ( ( portSTACK_TYPE ) 0 )
\r
93 #define portTICK_PRIORITY_6 ( 6 )
\r
94 /*-----------------------------------------------------------*/
\r
96 /* Setup the timer to generate the tick interrupts. */
\r
97 static void prvSetupTimerInterrupt( void );
\r
100 * The scheduler can only be started from ARM mode, so
\r
101 * vPortISRStartFirstSTask() is defined in portISR.c.
\r
103 extern void vPortISRStartFirstTask( void );
\r
105 /*-----------------------------------------------------------*/
\r
108 * Initialise the stack of a task to look exactly as if a call to
\r
109 * portSAVE_CONTEXT had been called.
\r
111 * See header file for description.
\r
113 portSTACK_TYPE *pxPortInitialiseStack( portSTACK_TYPE *pxTopOfStack, pdTASK_CODE pxCode, void *pvParameters )
\r
115 portSTACK_TYPE *pxOriginalTOS;
\r
117 pxOriginalTOS = pxTopOfStack;
\r
119 /* To ensure asserts in tasks.c don't fail, although in this case the assert
\r
120 is not really required. */
\r
123 /* Setup the initial stack of the task. The stack is set exactly as
\r
124 expected by the portRESTORE_CONTEXT() macro. */
\r
126 /* First on the stack is the return address - which in this case is the
\r
127 start of the task. The offset is added to make the return address appear
\r
128 as it would within an IRQ ISR. */
\r
129 *pxTopOfStack = ( portSTACK_TYPE ) pxCode + portINSTRUCTION_SIZE;
\r
132 *pxTopOfStack = ( portSTACK_TYPE ) 0xaaaaaaaa; /* R14 */
\r
134 *pxTopOfStack = ( portSTACK_TYPE ) pxOriginalTOS; /* Stack used when task starts goes in R13. */
\r
136 *pxTopOfStack = ( portSTACK_TYPE ) 0x12121212; /* R12 */
\r
138 *pxTopOfStack = ( portSTACK_TYPE ) 0x11111111; /* R11 */
\r
140 *pxTopOfStack = ( portSTACK_TYPE ) 0x10101010; /* R10 */
\r
142 *pxTopOfStack = ( portSTACK_TYPE ) 0x09090909; /* R9 */
\r
144 *pxTopOfStack = ( portSTACK_TYPE ) 0x08080808; /* R8 */
\r
146 *pxTopOfStack = ( portSTACK_TYPE ) 0x07070707; /* R7 */
\r
148 *pxTopOfStack = ( portSTACK_TYPE ) 0x06060606; /* R6 */
\r
150 *pxTopOfStack = ( portSTACK_TYPE ) 0x05050505; /* R5 */
\r
152 *pxTopOfStack = ( portSTACK_TYPE ) 0x04040404; /* R4 */
\r
154 *pxTopOfStack = ( portSTACK_TYPE ) 0x03030303; /* R3 */
\r
156 *pxTopOfStack = ( portSTACK_TYPE ) 0x02020202; /* R2 */
\r
158 *pxTopOfStack = ( portSTACK_TYPE ) 0x01010101; /* R1 */
\r
161 /* When the task starts is will expect to find the function parameter in
\r
163 *pxTopOfStack = ( portSTACK_TYPE ) pvParameters; /* R0 */
\r
166 /* The last thing onto the stack is the status register, which is set for
\r
167 system mode, with interrupts enabled. */
\r
168 *pxTopOfStack = ( portSTACK_TYPE ) portINITIAL_SPSR;
\r
170 #ifdef THUMB_INTERWORK
\r
172 /* We want the task to start in thumb mode. */
\r
173 *pxTopOfStack |= portTHUMB_MODE_BIT;
\r
179 /* Some optimisation levels use the stack differently to others. This
\r
180 means the interrupt flags cannot always be stored on the stack and will
\r
181 instead be stored in a variable, which is then saved as part of the
\r
183 *pxTopOfStack = portNO_CRITICAL_SECTION_NESTING;
\r
185 return pxTopOfStack;
\r
187 /*-----------------------------------------------------------*/
\r
189 portBASE_TYPE xPortStartScheduler( void )
\r
191 /* Start the timer that generates the tick ISR. Interrupts are disabled
\r
193 prvSetupTimerInterrupt();
\r
195 /* Start the first task. */
\r
196 vPortISRStartFirstTask();
\r
198 /* Should not get here! */
\r
201 /*-----------------------------------------------------------*/
\r
203 void vPortEndScheduler( void )
\r
205 /* It is unlikely that the ARM port will require this function as there
\r
206 is nothing to return to. */
\r
208 /*-----------------------------------------------------------*/
\r
211 * Setup the tick timer to generate the tick interrupts at the required frequency.
\r
213 static void prvSetupTimerInterrupt( void )
\r
215 volatile unsigned long ulDummy;
\r
217 /* Enable clock to the tick timer... */
\r
218 AT91C_BASE_PS->PS_PCER = portTIMER_CLK_ENABLE_BIT;
\r
220 /* Stop the tick timer... */
\r
221 portTIMER_REG_BASE_PTR->TC_CCR = TC_CLKDIS;
\r
223 /* Start with tick timer interrupts disabled... */
\r
224 portTIMER_REG_BASE_PTR->TC_IDR = 0xFFFFFFFF;
\r
226 /* Clear any pending tick timer interrupts... */
\r
227 ulDummy = portTIMER_REG_BASE_PTR->TC_SR;
\r
229 /* Store interrupt handler function address in tick timer vector register...
\r
230 The ISR installed depends on whether the preemptive or cooperative
\r
231 scheduler is being used. */
\r
232 #if configUSE_PREEMPTION == 1
\r
234 extern void ( vPreemptiveTick )( void );
\r
235 AT91C_BASE_AIC->AIC_SVR[portTIMER_AIC_CHANNEL] = ( unsigned long ) vPreemptiveTick;
\r
237 #else // else use cooperative scheduler
\r
239 extern void ( vNonPreemptiveTick )( void );
\r
240 AT91C_BASE_AIC->AIC_SVR[portTIMER_AIC_CHANNEL] = ( unsigned long ) vNonPreemptiveTick;
\r
244 /* Tick timer interrupt level-sensitive, priority 6... */
\r
245 AT91C_BASE_AIC->AIC_SMR[ portTIMER_AIC_CHANNEL ] = AIC_SRCTYPE_INT_LEVEL_SENSITIVE | portTICK_PRIORITY_6;
\r
247 /* Enable the tick timer interrupt...
\r
249 First at timer level */
\r
250 portTIMER_REG_BASE_PTR->TC_IER = TC_CPCS;
\r
252 /* Then at the AIC level. */
\r
253 AT91C_BASE_AIC->AIC_IECR = (1 << portTIMER_AIC_CHANNEL);
\r
255 /* Calculate timer compare value to achieve the desired tick rate... */
\r
256 if( (configCPU_CLOCK_HZ / (configTICK_RATE_HZ * 2) ) <= 0xFFFF )
\r
258 /* The tick rate is fast enough for us to use the faster timer input
\r
259 clock (main clock / 2). */
\r
260 portTIMER_REG_BASE_PTR->TC_CMR = TC_WAVE | TC_CLKS_MCK2 | TC_BURST_NONE | TC_CPCTRG;
\r
261 portTIMER_REG_BASE_PTR->TC_RC = configCPU_CLOCK_HZ / (configTICK_RATE_HZ * 2);
\r
265 /* We must use a slower timer input clock (main clock / 8) because the
\r
266 tick rate is too slow for the faster input clock. */
\r
267 portTIMER_REG_BASE_PTR->TC_CMR = TC_WAVE | TC_CLKS_MCK8 | TC_BURST_NONE | TC_CPCTRG;
\r
268 portTIMER_REG_BASE_PTR->TC_RC = configCPU_CLOCK_HZ / (configTICK_RATE_HZ * 8);
\r
271 /* Start tick timer... */
\r
272 portTIMER_REG_BASE_PTR->TC_CCR = TC_SWTRG | TC_CLKEN;
\r
274 /*-----------------------------------------------------------*/
\r