2 FreeRTOS V7.5.0 - Copyright (C) 2013 Real Time Engineers Ltd.
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4 VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
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6 ***************************************************************************
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8 * FreeRTOS provides completely free yet professionally developed, *
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9 * robust, strictly quality controlled, supported, and cross *
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10 * platform software that has become a de facto standard. *
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12 * Help yourself get started quickly and support the FreeRTOS *
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13 * project by purchasing a FreeRTOS tutorial book, reference *
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14 * manual, or both from: http://www.FreeRTOS.org/Documentation *
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18 ***************************************************************************
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20 This file is part of the FreeRTOS distribution.
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22 FreeRTOS is free software; you can redistribute it and/or modify it under
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23 the terms of the GNU General Public License (version 2) as published by the
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24 Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.
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26 >>! NOTE: The modification to the GPL is included to allow you to distribute
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27 >>! a combined work that includes FreeRTOS without being obliged to provide
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28 >>! the source code for proprietary components outside of the FreeRTOS
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31 FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
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32 WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
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33 FOR A PARTICULAR PURPOSE. Full license text is available from the following
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34 link: http://www.freertos.org/a00114.html
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38 ***************************************************************************
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40 * Having a problem? Start by reading the FAQ "My application does *
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41 * not run, what could be wrong?" *
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43 * http://www.FreeRTOS.org/FAQHelp.html *
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45 ***************************************************************************
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47 http://www.FreeRTOS.org - Documentation, books, training, latest versions,
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48 license and Real Time Engineers Ltd. contact details.
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50 http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
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51 including FreeRTOS+Trace - an indispensable productivity tool, a DOS
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52 compatible FAT file system, and our tiny thread aware UDP/IP stack.
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54 http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High
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55 Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS
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56 licenses offer ticketed support, indemnification and middleware.
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58 http://www.SafeRTOS.com - High Integrity Systems also provide a safety
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59 engineered and independently SIL3 certified version for use in safety and
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60 mission critical applications that require provable dependability.
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66 /*-----------------------------------------------------------
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67 * Components that can be compiled to either ARM or THUMB mode are
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68 * contained in port.c The ISR routines, which can only be compiled
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69 * to ARM mode, are contained in this file.
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70 *----------------------------------------------------------*/
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75 + The assembler statements are now included in a single asm block rather
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76 than each line having its own asm block.
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80 /* Scheduler includes. */
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81 #include "FreeRTOS.h"
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84 /* Constants required to handle interrupts. */
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85 #define portCLEAR_AIC_INTERRUPT ( ( unsigned long ) 0 )
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87 /* Constants required to handle critical sections. */
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88 #define portNO_CRITICAL_NESTING ( ( unsigned long ) 0 )
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89 volatile unsigned long ulCriticalNesting = 9999UL;
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91 /*-----------------------------------------------------------*/
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93 /* ISR to handle manual context switches (from a call to taskYIELD()). */
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94 void vPortYieldProcessor( void ) __attribute__((interrupt("SWI"), naked));
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97 * The scheduler can only be started from ARM mode, hence the inclusion of this
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100 void vPortISRStartFirstTask( void );
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101 /*-----------------------------------------------------------*/
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103 void vPortISRStartFirstTask( void )
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105 /* Simply start the scheduler. This is included here as it can only be
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106 called from ARM mode. */
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107 portRESTORE_CONTEXT();
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109 /*-----------------------------------------------------------*/
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112 * Called by portYIELD() or taskYIELD() to manually force a context switch.
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114 * When a context switch is performed from the task level the saved task
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115 * context is made to look as if it occurred from within the tick ISR. This
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116 * way the same restore context function can be used when restoring the context
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117 * saved from the ISR or that saved from a call to vPortYieldProcessor.
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119 void vPortYieldProcessor( void )
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121 /* Within an IRQ ISR the link register has an offset from the true return
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122 address, but an SWI ISR does not. Add the offset manually so the same
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123 ISR return code can be used in both cases. */
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124 asm volatile ( "ADD LR, LR, #4" );
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126 /* Perform the context switch. First save the context of the current task. */
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127 portSAVE_CONTEXT();
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129 /* Find the highest priority task that is ready to run. */
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130 vTaskSwitchContext();
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132 /* Restore the context of the new task. */
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133 portRESTORE_CONTEXT();
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135 /*-----------------------------------------------------------*/
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138 * The ISR used for the scheduler tick depends on whether the cooperative or
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139 * the preemptive scheduler is being used.
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142 #if configUSE_PREEMPTION == 0
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144 /* The cooperative scheduler requires a normal IRQ service routine to
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145 simply increment the system tick. */
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146 void vNonPreemptiveTick( void ) __attribute__ ((interrupt ("IRQ")));
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147 void vNonPreemptiveTick( void )
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149 static volatile unsigned long ulDummy;
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151 /* Clear tick timer interrupt indication. */
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152 ulDummy = portTIMER_REG_BASE_PTR->TC_SR;
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154 xTaskIncrementTick();
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156 /* Acknowledge the interrupt at AIC level... */
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157 AT91C_BASE_AIC->AIC_EOICR = portCLEAR_AIC_INTERRUPT;
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160 #else /* else preemption is turned on */
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162 /* The preemptive scheduler is defined as "naked" as the full context is
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163 saved on entry as part of the context switch. */
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164 void vPreemptiveTick( void ) __attribute__((naked));
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165 void vPreemptiveTick( void )
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167 /* Save the context of the interrupted task. */
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168 portSAVE_CONTEXT();
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170 /* WARNING - Do not use local (stack) variables here. Use globals
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172 static volatile unsigned long ulDummy;
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174 /* Clear tick timer interrupt indication. */
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175 ulDummy = portTIMER_REG_BASE_PTR->TC_SR;
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177 /* Increment the RTOS tick count, then look for the highest priority
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178 task that is ready to run. */
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179 if( xTaskIncrementTick() != pdFALSE )
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181 vTaskSwitchContext();
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184 /* Acknowledge the interrupt at AIC level... */
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185 AT91C_BASE_AIC->AIC_EOICR = portCLEAR_AIC_INTERRUPT;
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187 /* Restore the context of the new task. */
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188 portRESTORE_CONTEXT();
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192 /*-----------------------------------------------------------*/
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195 * The interrupt management utilities can only be called from ARM mode. When
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196 * THUMB_INTERWORK is defined the utilities are defined as functions here to
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197 * ensure a switch to ARM mode. When THUMB_INTERWORK is not defined then
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198 * the utilities are defined as macros in portmacro.h - as per other ports.
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200 #ifdef THUMB_INTERWORK
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202 void vPortDisableInterruptsFromThumb( void ) __attribute__ ((naked));
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203 void vPortEnableInterruptsFromThumb( void ) __attribute__ ((naked));
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205 void vPortDisableInterruptsFromThumb( void )
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208 "STMDB SP!, {R0} \n\t" /* Push R0. */
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209 "MRS R0, CPSR \n\t" /* Get CPSR. */
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210 "ORR R0, R0, #0xC0 \n\t" /* Disable IRQ, FIQ. */
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211 "MSR CPSR, R0 \n\t" /* Write back modified value. */
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212 "LDMIA SP!, {R0} \n\t" /* Pop R0. */
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213 "BX R14" ); /* Return back to thumb. */
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216 void vPortEnableInterruptsFromThumb( void )
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219 "STMDB SP!, {R0} \n\t" /* Push R0. */
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220 "MRS R0, CPSR \n\t" /* Get CPSR. */
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221 "BIC R0, R0, #0xC0 \n\t" /* Enable IRQ, FIQ. */
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222 "MSR CPSR, R0 \n\t" /* Write back modified value. */
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223 "LDMIA SP!, {R0} \n\t" /* Pop R0. */
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224 "BX R14" ); /* Return back to thumb. */
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227 #endif /* THUMB_INTERWORK */
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229 /* The code generated by the GCC compiler uses the stack in different ways at
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230 different optimisation levels. The interrupt flags can therefore not always
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231 be saved to the stack. Instead the critical section nesting level is stored
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232 in a variable, which is then saved as part of the stack context. */
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233 void vPortEnterCritical( void )
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235 /* Disable interrupts as per portDISABLE_INTERRUPTS(); */
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237 "STMDB SP!, {R0} \n\t" /* Push R0. */
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238 "MRS R0, CPSR \n\t" /* Get CPSR. */
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239 "ORR R0, R0, #0xC0 \n\t" /* Disable IRQ, FIQ. */
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240 "MSR CPSR, R0 \n\t" /* Write back modified value. */
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241 "LDMIA SP!, {R0}" ); /* Pop R0. */
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243 /* Now interrupts are disabled ulCriticalNesting can be accessed
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244 directly. Increment ulCriticalNesting to keep a count of how many times
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245 portENTER_CRITICAL() has been called. */
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246 ulCriticalNesting++;
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249 void vPortExitCritical( void )
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251 if( ulCriticalNesting > portNO_CRITICAL_NESTING )
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253 /* Decrement the nesting count as we are leaving a critical section. */
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254 ulCriticalNesting--;
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256 /* If the nesting level has reached zero then interrupts should be
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258 if( ulCriticalNesting == portNO_CRITICAL_NESTING )
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260 /* Enable interrupts as per portEXIT_CRITICAL(). */
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262 "STMDB SP!, {R0} \n\t" /* Push R0. */
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263 "MRS R0, CPSR \n\t" /* Get CPSR. */
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264 "BIC R0, R0, #0xC0 \n\t" /* Enable IRQ, FIQ. */
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265 "MSR CPSR, R0 \n\t" /* Write back modified value. */
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266 "LDMIA SP!, {R0}" ); /* Pop R0. */
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