2 * FreeRTOS Kernel V10.1.1
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3 * Copyright (C) 2018 Amazon.com, Inc. or its affiliates. All Rights Reserved.
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5 * Permission is hereby granted, free of charge, to any person obtaining a copy of
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6 * this software and associated documentation files (the "Software"), to deal in
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7 * the Software without restriction, including without limitation the rights to
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8 * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
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9 * the Software, and to permit persons to whom the Software is furnished to do so,
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10 * subject to the following conditions:
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12 * The above copyright notice and this permission notice shall be included in all
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13 * copies or substantial portions of the Software.
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15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
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17 * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
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18 * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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19 * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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20 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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22 * http://www.FreeRTOS.org
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23 * http://aws.amazon.com/freertos
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25 * 1 tab == 4 spaces!
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29 /*-----------------------------------------------------------
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30 * Implementation of functions defined in portable.h for the ARM7 port.
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32 * Components that can be compiled to either ARM or THUMB mode are
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33 * contained in this file. The ISR routines, which can only be compiled
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34 * to ARM mode are contained in portISR.c.
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35 *----------------------------------------------------------*/
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37 /* Standard includes. */
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40 /* Scheduler includes. */
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41 #include "FreeRTOS.h"
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44 /* Processor constants. */
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45 #include "AT91SAM7X256.h"
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47 /* Constants required to setup the task context. */
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48 #define portINITIAL_SPSR ( ( StackType_t ) 0x1f ) /* System mode, ARM mode, interrupts enabled. */
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49 #define portTHUMB_MODE_BIT ( ( StackType_t ) 0x20 )
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50 #define portINSTRUCTION_SIZE ( ( StackType_t ) 4 )
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51 #define portNO_CRITICAL_SECTION_NESTING ( ( StackType_t ) 0 )
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53 /* Constants required to setup the tick ISR. */
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54 #define portENABLE_TIMER ( ( uint8_t ) 0x01 )
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55 #define portPRESCALE_VALUE 0x00
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56 #define portINTERRUPT_ON_MATCH ( ( uint32_t ) 0x01 )
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57 #define portRESET_COUNT_ON_MATCH ( ( uint32_t ) 0x02 )
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59 /* Constants required to setup the PIT. */
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60 #define portPIT_CLOCK_DIVISOR ( ( uint32_t ) 16 )
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61 #define portPIT_COUNTER_VALUE ( ( ( configCPU_CLOCK_HZ / portPIT_CLOCK_DIVISOR ) / 1000UL ) * portTICK_PERIOD_MS )
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63 #define portINT_LEVEL_SENSITIVE 0
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64 #define portPIT_ENABLE ( ( uint16_t ) 0x1 << 24 )
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65 #define portPIT_INT_ENABLE ( ( uint16_t ) 0x1 << 25 )
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66 /*-----------------------------------------------------------*/
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68 /* Setup the timer to generate the tick interrupts. */
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69 static void prvSetupTimerInterrupt( void );
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72 * The scheduler can only be started from ARM mode, so
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73 * vPortISRStartFirstSTask() is defined in portISR.c.
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75 extern void vPortISRStartFirstTask( void );
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77 /*-----------------------------------------------------------*/
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80 * Initialise the stack of a task to look exactly as if a call to
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81 * portSAVE_CONTEXT had been called.
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83 * See header file for description.
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85 StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
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87 StackType_t *pxOriginalTOS;
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89 pxOriginalTOS = pxTopOfStack;
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91 /* To ensure asserts in tasks.c don't fail, although in this case the assert
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92 is not really required. */
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95 /* Setup the initial stack of the task. The stack is set exactly as
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96 expected by the portRESTORE_CONTEXT() macro. */
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98 /* First on the stack is the return address - which in this case is the
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99 start of the task. The offset is added to make the return address appear
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100 as it would within an IRQ ISR. */
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101 *pxTopOfStack = ( StackType_t ) pxCode + portINSTRUCTION_SIZE;
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104 *pxTopOfStack = ( StackType_t ) 0x00000000; /* R14 */
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106 *pxTopOfStack = ( StackType_t ) pxOriginalTOS; /* Stack used when task starts goes in R13. */
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108 *pxTopOfStack = ( StackType_t ) 0x12121212; /* R12 */
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110 *pxTopOfStack = ( StackType_t ) 0x11111111; /* R11 */
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112 *pxTopOfStack = ( StackType_t ) 0x10101010; /* R10 */
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114 *pxTopOfStack = ( StackType_t ) 0x09090909; /* R9 */
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116 *pxTopOfStack = ( StackType_t ) 0x08080808; /* R8 */
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118 *pxTopOfStack = ( StackType_t ) 0x07070707; /* R7 */
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120 *pxTopOfStack = ( StackType_t ) 0x06060606; /* R6 */
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122 *pxTopOfStack = ( StackType_t ) 0x05050505; /* R5 */
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124 *pxTopOfStack = ( StackType_t ) 0x04040404; /* R4 */
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126 *pxTopOfStack = ( StackType_t ) 0x03030303; /* R3 */
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128 *pxTopOfStack = ( StackType_t ) 0x02020202; /* R2 */
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130 *pxTopOfStack = ( StackType_t ) 0x01010101; /* R1 */
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133 /* When the task starts is will expect to find the function parameter in
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135 *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
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138 /* The last thing onto the stack is the status register, which is set for
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139 system mode, with interrupts enabled. */
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140 *pxTopOfStack = ( StackType_t ) portINITIAL_SPSR;
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142 #ifdef THUMB_INTERWORK
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144 /* We want the task to start in thumb mode. */
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145 *pxTopOfStack |= portTHUMB_MODE_BIT;
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151 /* Some optimisation levels use the stack differently to others. This
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152 means the interrupt flags cannot always be stored on the stack and will
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153 instead be stored in a variable, which is then saved as part of the
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155 *pxTopOfStack = portNO_CRITICAL_SECTION_NESTING;
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157 return pxTopOfStack;
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159 /*-----------------------------------------------------------*/
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161 BaseType_t xPortStartScheduler( void )
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163 /* Start the timer that generates the tick ISR. Interrupts are disabled
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165 prvSetupTimerInterrupt();
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167 /* Start the first task. */
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168 vPortISRStartFirstTask();
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170 /* Should not get here! */
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173 /*-----------------------------------------------------------*/
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175 void vPortEndScheduler( void )
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177 /* It is unlikely that the ARM port will require this function as there
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178 is nothing to return to. */
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180 /*-----------------------------------------------------------*/
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183 * Setup the timer 0 to generate the tick interrupts at the required frequency.
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185 static void prvSetupTimerInterrupt( void )
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187 AT91PS_PITC pxPIT = AT91C_BASE_PITC;
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189 /* Setup the AIC for PIT interrupts. The interrupt routine chosen depends
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190 on whether the preemptive or cooperative scheduler is being used. */
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191 #if configUSE_PREEMPTION == 0
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193 extern void ( vNonPreemptiveTick ) ( void );
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194 AT91F_AIC_ConfigureIt( AT91C_ID_SYS, AT91C_AIC_PRIOR_HIGHEST, portINT_LEVEL_SENSITIVE, ( void (*)(void) ) vNonPreemptiveTick );
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198 extern void ( vPreemptiveTick )( void );
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199 AT91F_AIC_ConfigureIt( AT91C_ID_SYS, AT91C_AIC_PRIOR_HIGHEST, portINT_LEVEL_SENSITIVE, ( void (*)(void) ) vPreemptiveTick );
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203 /* Configure the PIT period. */
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204 pxPIT->PITC_PIMR = portPIT_ENABLE | portPIT_INT_ENABLE | portPIT_COUNTER_VALUE;
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206 /* Enable the interrupt. Global interrupts are disables at this point so
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208 AT91C_BASE_AIC->AIC_IECR = 0x1 << AT91C_ID_SYS;
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210 /*-----------------------------------------------------------*/
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