2 FreeRTOS V7.5.3 - Copyright (C) 2013 Real Time Engineers Ltd.
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5 VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
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7 ***************************************************************************
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9 * FreeRTOS provides completely free yet professionally developed, *
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10 * robust, strictly quality controlled, supported, and cross *
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11 * platform software that has become a de facto standard. *
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13 * Help yourself get started quickly and support the FreeRTOS *
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14 * project by purchasing a FreeRTOS tutorial book, reference *
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15 * manual, or both from: http://www.FreeRTOS.org/Documentation *
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19 ***************************************************************************
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21 This file is part of the FreeRTOS distribution.
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23 FreeRTOS is free software; you can redistribute it and/or modify it under
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24 the terms of the GNU General Public License (version 2) as published by the
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25 Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.
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27 >>! NOTE: The modification to the GPL is included to allow you to distribute
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28 >>! a combined work that includes FreeRTOS without being obliged to provide
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29 >>! the source code for proprietary components outside of the FreeRTOS
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32 FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
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33 WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
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34 FOR A PARTICULAR PURPOSE. Full license text is available from the following
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35 link: http://www.freertos.org/a00114.html
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39 ***************************************************************************
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41 * Having a problem? Start by reading the FAQ "My application does *
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42 * not run, what could be wrong?" *
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44 * http://www.FreeRTOS.org/FAQHelp.html *
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46 ***************************************************************************
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48 http://www.FreeRTOS.org - Documentation, books, training, latest versions,
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49 license and Real Time Engineers Ltd. contact details.
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51 http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
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52 including FreeRTOS+Trace - an indispensable productivity tool, a DOS
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53 compatible FAT file system, and our tiny thread aware UDP/IP stack.
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55 http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High
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56 Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS
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57 licenses offer ticketed support, indemnification and middleware.
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59 http://www.SafeRTOS.com - High Integrity Systems also provide a safety
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60 engineered and independently SIL3 certified version for use in safety and
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61 mission critical applications that require provable dependability.
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67 /*-----------------------------------------------------------
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68 * Components that can be compiled to either ARM or THUMB mode are
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69 * contained in port.c The ISR routines, which can only be compiled
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70 * to ARM mode, are contained in this file.
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71 *----------------------------------------------------------*/
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76 + The critical section management functions have been changed. These no
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77 longer modify the stack and are safe to use at all optimisation levels.
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78 The functions are now also the same for both ARM and THUMB modes.
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82 + Removed the 'static' from the definition of vNonPreemptiveTick() to
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83 allow the demo to link when using the cooperative scheduler.
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87 + The assembler statements are now included in a single asm block rather
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88 than each line having its own asm block.
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92 /* Scheduler includes. */
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93 #include "FreeRTOS.h"
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95 /* Constants required to handle interrupts. */
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96 #define portTIMER_MATCH_ISR_BIT ( ( unsigned char ) 0x01 )
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97 #define portCLEAR_VIC_INTERRUPT ( ( unsigned long ) 0 )
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99 /* Constants required to handle critical sections. */
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100 #define portNO_CRITICAL_NESTING ( ( unsigned long ) 0 )
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101 volatile unsigned long ulCriticalNesting = 9999UL;
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103 /*-----------------------------------------------------------*/
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105 /* ISR to handle manual context switches (from a call to taskYIELD()). */
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106 void vPortYieldProcessor( void ) __attribute__((interrupt("SWI"), naked));
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109 * The scheduler can only be started from ARM mode, hence the inclusion of this
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112 void vPortISRStartFirstTask( void );
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113 /*-----------------------------------------------------------*/
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115 void vPortISRStartFirstTask( void )
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117 /* Simply start the scheduler. This is included here as it can only be
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118 called from ARM mode. */
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119 portRESTORE_CONTEXT();
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121 /*-----------------------------------------------------------*/
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124 * Called by portYIELD() or taskYIELD() to manually force a context switch.
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126 * When a context switch is performed from the task level the saved task
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127 * context is made to look as if it occurred from within the tick ISR. This
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128 * way the same restore context function can be used when restoring the context
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129 * saved from the ISR or that saved from a call to vPortYieldProcessor.
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131 void vPortYieldProcessor( void )
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133 /* Within an IRQ ISR the link register has an offset from the true return
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134 address, but an SWI ISR does not. Add the offset manually so the same
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135 ISR return code can be used in both cases. */
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136 __asm volatile ( "ADD LR, LR, #4" );
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138 /* Perform the context switch. First save the context of the current task. */
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139 portSAVE_CONTEXT();
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141 /* Find the highest priority task that is ready to run. */
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142 __asm volatile ( "bl vTaskSwitchContext" );
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144 /* Restore the context of the new task. */
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145 portRESTORE_CONTEXT();
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147 /*-----------------------------------------------------------*/
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150 * The ISR used for the scheduler tick.
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152 void vTickISR( void ) __attribute__((naked));
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153 void vTickISR( void )
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155 /* Save the context of the interrupted task. */
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156 portSAVE_CONTEXT();
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158 /* Increment the RTOS tick count, then look for the highest priority
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159 task that is ready to run. */
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162 " bl xTaskIncrementTick \t\n" \
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163 " cmp r0, #0 \t\n" \
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164 " beq SkipContextSwitch \t\n" \
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165 " bl vTaskSwitchContext \t\n" \
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166 "SkipContextSwitch: \t\n"
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169 /* Ready for the next interrupt. */
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170 T0_IR = portTIMER_MATCH_ISR_BIT;
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171 VICVectAddr = portCLEAR_VIC_INTERRUPT;
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173 /* Restore the context of the new task. */
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174 portRESTORE_CONTEXT();
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176 /*-----------------------------------------------------------*/
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179 * The interrupt management utilities can only be called from ARM mode. When
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180 * THUMB_INTERWORK is defined the utilities are defined as functions here to
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181 * ensure a switch to ARM mode. When THUMB_INTERWORK is not defined then
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182 * the utilities are defined as macros in portmacro.h - as per other ports.
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184 #ifdef THUMB_INTERWORK
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186 void vPortDisableInterruptsFromThumb( void ) __attribute__ ((naked));
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187 void vPortEnableInterruptsFromThumb( void ) __attribute__ ((naked));
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189 void vPortDisableInterruptsFromThumb( void )
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192 "STMDB SP!, {R0} \n\t" /* Push R0. */
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193 "MRS R0, CPSR \n\t" /* Get CPSR. */
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194 "ORR R0, R0, #0xC0 \n\t" /* Disable IRQ, FIQ. */
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195 "MSR CPSR, R0 \n\t" /* Write back modified value. */
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196 "LDMIA SP!, {R0} \n\t" /* Pop R0. */
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197 "BX R14" ); /* Return back to thumb. */
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200 void vPortEnableInterruptsFromThumb( void )
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203 "STMDB SP!, {R0} \n\t" /* Push R0. */
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204 "MRS R0, CPSR \n\t" /* Get CPSR. */
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205 "BIC R0, R0, #0xC0 \n\t" /* Enable IRQ, FIQ. */
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206 "MSR CPSR, R0 \n\t" /* Write back modified value. */
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207 "LDMIA SP!, {R0} \n\t" /* Pop R0. */
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208 "BX R14" ); /* Return back to thumb. */
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211 #endif /* THUMB_INTERWORK */
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213 /* The code generated by the GCC compiler uses the stack in different ways at
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214 different optimisation levels. The interrupt flags can therefore not always
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215 be saved to the stack. Instead the critical section nesting level is stored
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216 in a variable, which is then saved as part of the stack context. */
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217 void vPortEnterCritical( void )
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219 /* Disable interrupts as per portDISABLE_INTERRUPTS(); */
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221 "STMDB SP!, {R0} \n\t" /* Push R0. */
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222 "MRS R0, CPSR \n\t" /* Get CPSR. */
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223 "ORR R0, R0, #0xC0 \n\t" /* Disable IRQ, FIQ. */
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224 "MSR CPSR, R0 \n\t" /* Write back modified value. */
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225 "LDMIA SP!, {R0}" ); /* Pop R0. */
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227 /* Now interrupts are disabled ulCriticalNesting can be accessed
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228 directly. Increment ulCriticalNesting to keep a count of how many times
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229 portENTER_CRITICAL() has been called. */
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230 ulCriticalNesting++;
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233 void vPortExitCritical( void )
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235 if( ulCriticalNesting > portNO_CRITICAL_NESTING )
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237 /* Decrement the nesting count as we are leaving a critical section. */
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238 ulCriticalNesting--;
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240 /* If the nesting level has reached zero then interrupts should be
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242 if( ulCriticalNesting == portNO_CRITICAL_NESTING )
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244 /* Enable interrupts as per portEXIT_CRITICAL(). */
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246 "STMDB SP!, {R0} \n\t" /* Push R0. */
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247 "MRS R0, CPSR \n\t" /* Get CPSR. */
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248 "BIC R0, R0, #0xC0 \n\t" /* Enable IRQ, FIQ. */
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249 "MSR CPSR, R0 \n\t" /* Write back modified value. */
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250 "LDMIA SP!, {R0}" ); /* Pop R0. */
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