2 FreeRTOS V7.1.1 - Copyright (C) 2012 Real Time Engineers Ltd.
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5 ***************************************************************************
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7 * FreeRTOS tutorial books are available in pdf and paperback. *
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8 * Complete, revised, and edited pdf reference manuals are also *
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11 * Purchasing FreeRTOS documentation will not only help you, by *
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12 * ensuring you get running as quickly as possible and with an *
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13 * in-depth knowledge of how to use FreeRTOS, it will also help *
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14 * the FreeRTOS project to continue with its mission of providing *
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15 * professional grade, cross platform, de facto standard solutions *
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16 * for microcontrollers - completely free of charge! *
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18 * >>> See http://www.FreeRTOS.org/Documentation for details. <<< *
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20 * Thank you for using FreeRTOS, and thank you for your support! *
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22 ***************************************************************************
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25 This file is part of the FreeRTOS distribution.
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27 FreeRTOS is free software; you can redistribute it and/or modify it under
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28 the terms of the GNU General Public License (version 2) as published by the
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29 Free Software Foundation AND MODIFIED BY the FreeRTOS exception.
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30 >>>NOTE<<< The modification to the GPL is included to allow you to
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31 distribute a combined work that includes FreeRTOS without being obliged to
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32 provide the source code for proprietary components outside of the FreeRTOS
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33 kernel. FreeRTOS is distributed in the hope that it will be useful, but
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34 WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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35 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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36 more details. You should have received a copy of the GNU General Public
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37 License and the FreeRTOS license exception along with FreeRTOS; if not it
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38 can be viewed here: http://www.freertos.org/a00114.html and also obtained
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39 by writing to Richard Barry, contact details for whom are available on the
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44 ***************************************************************************
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46 * Having a problem? Start by reading the FAQ "My application does *
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47 * not run, what could be wrong? *
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49 * http://www.FreeRTOS.org/FAQHelp.html *
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51 ***************************************************************************
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54 http://www.FreeRTOS.org - Documentation, training, latest information,
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55 license and contact details.
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57 http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
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58 including FreeRTOS+Trace - an indispensable productivity tool.
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60 Real Time Engineers ltd license FreeRTOS to High Integrity Systems, who sell
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61 the code with commercial support, indemnification, and middleware, under
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62 the OpenRTOS brand: http://www.OpenRTOS.com. High Integrity Systems also
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63 provide a safety engineered and independently SIL3 certified version under
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64 the SafeRTOS brand: http://www.SafeRTOS.com.
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68 /*-----------------------------------------------------------
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69 * Components that can be compiled to either ARM or THUMB mode are
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70 * contained in port.c The ISR routines, which can only be compiled
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71 * to ARM mode, are contained in this file.
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72 *----------------------------------------------------------*/
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77 + The critical section management functions have been changed. These no
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78 longer modify the stack and are safe to use at all optimisation levels.
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79 The functions are now also the same for both ARM and THUMB modes.
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83 + Removed the 'static' from the definition of vNonPreemptiveTick() to
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84 allow the demo to link when using the cooperative scheduler.
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88 + The assembler statements are now included in a single asm block rather
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89 than each line having its own asm block.
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93 /* Scheduler includes. */
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94 #include "FreeRTOS.h"
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96 /* Constants required to handle interrupts. */
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97 #define portTIMER_MATCH_ISR_BIT ( ( unsigned char ) 0x01 )
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98 #define portCLEAR_VIC_INTERRUPT ( ( unsigned long ) 0 )
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100 /* Constants required to handle critical sections. */
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101 #define portNO_CRITICAL_NESTING ( ( unsigned long ) 0 )
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102 volatile unsigned long ulCriticalNesting = 9999UL;
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104 /*-----------------------------------------------------------*/
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106 /* ISR to handle manual context switches (from a call to taskYIELD()). */
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107 void vPortYieldProcessor( void ) __attribute__((interrupt("SWI"), naked));
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110 * The scheduler can only be started from ARM mode, hence the inclusion of this
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113 void vPortISRStartFirstTask( void );
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114 /*-----------------------------------------------------------*/
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116 void vPortISRStartFirstTask( void )
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118 /* Simply start the scheduler. This is included here as it can only be
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119 called from ARM mode. */
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120 portRESTORE_CONTEXT();
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122 /*-----------------------------------------------------------*/
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125 * Called by portYIELD() or taskYIELD() to manually force a context switch.
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127 * When a context switch is performed from the task level the saved task
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128 * context is made to look as if it occurred from within the tick ISR. This
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129 * way the same restore context function can be used when restoring the context
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130 * saved from the ISR or that saved from a call to vPortYieldProcessor.
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132 void vPortYieldProcessor( void )
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134 /* Within an IRQ ISR the link register has an offset from the true return
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135 address, but an SWI ISR does not. Add the offset manually so the same
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136 ISR return code can be used in both cases. */
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137 __asm volatile ( "ADD LR, LR, #4" );
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139 /* Perform the context switch. First save the context of the current task. */
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140 portSAVE_CONTEXT();
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142 /* Find the highest priority task that is ready to run. */
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143 __asm volatile ( "bl vTaskSwitchContext" );
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145 /* Restore the context of the new task. */
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146 portRESTORE_CONTEXT();
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148 /*-----------------------------------------------------------*/
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151 * The ISR used for the scheduler tick.
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153 void vTickISR( void ) __attribute__((naked));
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154 void vTickISR( void )
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156 /* Save the context of the interrupted task. */
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157 portSAVE_CONTEXT();
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159 /* Increment the RTOS tick count, then look for the highest priority
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160 task that is ready to run. */
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161 __asm volatile( "bl vTaskIncrementTick" );
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163 #if configUSE_PREEMPTION == 1
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164 __asm volatile( "bl vTaskSwitchContext" );
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167 /* Ready for the next interrupt. */
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168 T0_IR = portTIMER_MATCH_ISR_BIT;
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169 VICVectAddr = portCLEAR_VIC_INTERRUPT;
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171 /* Restore the context of the new task. */
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172 portRESTORE_CONTEXT();
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174 /*-----------------------------------------------------------*/
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177 * The interrupt management utilities can only be called from ARM mode. When
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178 * THUMB_INTERWORK is defined the utilities are defined as functions here to
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179 * ensure a switch to ARM mode. When THUMB_INTERWORK is not defined then
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180 * the utilities are defined as macros in portmacro.h - as per other ports.
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182 #ifdef THUMB_INTERWORK
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184 void vPortDisableInterruptsFromThumb( void ) __attribute__ ((naked));
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185 void vPortEnableInterruptsFromThumb( void ) __attribute__ ((naked));
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187 void vPortDisableInterruptsFromThumb( void )
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190 "STMDB SP!, {R0} \n\t" /* Push R0. */
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191 "MRS R0, CPSR \n\t" /* Get CPSR. */
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192 "ORR R0, R0, #0xC0 \n\t" /* Disable IRQ, FIQ. */
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193 "MSR CPSR, R0 \n\t" /* Write back modified value. */
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194 "LDMIA SP!, {R0} \n\t" /* Pop R0. */
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195 "BX R14" ); /* Return back to thumb. */
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198 void vPortEnableInterruptsFromThumb( void )
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201 "STMDB SP!, {R0} \n\t" /* Push R0. */
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202 "MRS R0, CPSR \n\t" /* Get CPSR. */
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203 "BIC R0, R0, #0xC0 \n\t" /* Enable IRQ, FIQ. */
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204 "MSR CPSR, R0 \n\t" /* Write back modified value. */
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205 "LDMIA SP!, {R0} \n\t" /* Pop R0. */
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206 "BX R14" ); /* Return back to thumb. */
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209 #endif /* THUMB_INTERWORK */
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211 /* The code generated by the GCC compiler uses the stack in different ways at
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212 different optimisation levels. The interrupt flags can therefore not always
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213 be saved to the stack. Instead the critical section nesting level is stored
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214 in a variable, which is then saved as part of the stack context. */
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215 void vPortEnterCritical( void )
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217 /* Disable interrupts as per portDISABLE_INTERRUPTS(); */
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219 "STMDB SP!, {R0} \n\t" /* Push R0. */
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220 "MRS R0, CPSR \n\t" /* Get CPSR. */
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221 "ORR R0, R0, #0xC0 \n\t" /* Disable IRQ, FIQ. */
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222 "MSR CPSR, R0 \n\t" /* Write back modified value. */
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223 "LDMIA SP!, {R0}" ); /* Pop R0. */
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225 /* Now interrupts are disabled ulCriticalNesting can be accessed
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226 directly. Increment ulCriticalNesting to keep a count of how many times
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227 portENTER_CRITICAL() has been called. */
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228 ulCriticalNesting++;
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231 void vPortExitCritical( void )
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233 if( ulCriticalNesting > portNO_CRITICAL_NESTING )
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235 /* Decrement the nesting count as we are leaving a critical section. */
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236 ulCriticalNesting--;
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238 /* If the nesting level has reached zero then interrupts should be
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240 if( ulCriticalNesting == portNO_CRITICAL_NESTING )
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242 /* Enable interrupts as per portEXIT_CRITICAL(). */
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244 "STMDB SP!, {R0} \n\t" /* Push R0. */
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245 "MRS R0, CPSR \n\t" /* Get CPSR. */
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246 "BIC R0, R0, #0xC0 \n\t" /* Enable IRQ, FIQ. */
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247 "MSR CPSR, R0 \n\t" /* Write back modified value. */
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248 "LDMIA SP!, {R0}" ); /* Pop R0. */
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