2 FreeRTOS V7.4.2 - Copyright (C) 2013 Real Time Engineers Ltd.
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4 FEATURES AND PORTS ARE ADDED TO FREERTOS ALL THE TIME. PLEASE VISIT
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5 http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
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7 ***************************************************************************
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9 * FreeRTOS tutorial books are available in pdf and paperback. *
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10 * Complete, revised, and edited pdf reference manuals are also *
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13 * Purchasing FreeRTOS documentation will not only help you, by *
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14 * ensuring you get running as quickly as possible and with an *
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15 * in-depth knowledge of how to use FreeRTOS, it will also help *
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16 * the FreeRTOS project to continue with its mission of providing *
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17 * professional grade, cross platform, de facto standard solutions *
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18 * for microcontrollers - completely free of charge! *
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20 * >>> See http://www.FreeRTOS.org/Documentation for details. <<< *
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22 * Thank you for using FreeRTOS, and thank you for your support! *
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24 ***************************************************************************
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27 This file is part of the FreeRTOS distribution.
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29 FreeRTOS is free software; you can redistribute it and/or modify it under
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30 the terms of the GNU General Public License (version 2) as published by the
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31 Free Software Foundation AND MODIFIED BY the FreeRTOS exception.
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33 >>>>>>NOTE<<<<<< The modification to the GPL is included to allow you to
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34 distribute a combined work that includes FreeRTOS without being obliged to
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35 provide the source code for proprietary components outside of the FreeRTOS
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38 FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
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39 WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
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40 FOR A PARTICULAR PURPOSE. See the GNU General Public License for more
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41 details. You should have received a copy of the GNU General Public License
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42 and the FreeRTOS license exception along with FreeRTOS; if not it can be
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43 viewed here: http://www.freertos.org/a00114.html and also obtained by
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44 writing to Real Time Engineers Ltd., contact details for whom are available
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45 on the FreeRTOS WEB site.
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49 ***************************************************************************
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51 * Having a problem? Start by reading the FAQ "My application does *
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52 * not run, what could be wrong?" *
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54 * http://www.FreeRTOS.org/FAQHelp.html *
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56 ***************************************************************************
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59 http://www.FreeRTOS.org - Documentation, books, training, latest versions,
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60 license and Real Time Engineers Ltd. contact details.
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62 http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
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63 including FreeRTOS+Trace - an indispensable productivity tool, and our new
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64 fully thread aware and reentrant UDP/IP stack.
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66 http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High
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67 Integrity Systems, who sell the code with commercial support,
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68 indemnification and middleware, under the OpenRTOS brand.
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70 http://www.SafeRTOS.com - High Integrity Systems also provide a safety
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71 engineered and independently SIL3 certified version for use in safety and
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72 mission critical applications that require provable dependability.
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76 /*-----------------------------------------------------------
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77 * Components that can be compiled to either ARM or THUMB mode are
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78 * contained in port.c The ISR routines, which can only be compiled
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79 * to ARM mode, are contained in this file.
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80 *----------------------------------------------------------*/
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85 + The critical section management functions have been changed. These no
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86 longer modify the stack and are safe to use at all optimisation levels.
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87 The functions are now also the same for both ARM and THUMB modes.
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91 + Removed the 'static' from the definition of vNonPreemptiveTick() to
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92 allow the demo to link when using the cooperative scheduler.
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96 + The assembler statements are now included in a single asm block rather
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97 than each line having its own asm block.
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101 /* Scheduler includes. */
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102 #include "FreeRTOS.h"
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104 /* Constants required to handle interrupts. */
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105 #define portTIMER_MATCH_ISR_BIT ( ( unsigned char ) 0x01 )
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106 #define portCLEAR_VIC_INTERRUPT ( ( unsigned long ) 0 )
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108 /* Constants required to handle critical sections. */
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109 #define portNO_CRITICAL_NESTING ( ( unsigned long ) 0 )
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110 volatile unsigned long ulCriticalNesting = 9999UL;
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112 /*-----------------------------------------------------------*/
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114 /* ISR to handle manual context switches (from a call to taskYIELD()). */
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115 void vPortYieldProcessor( void ) __attribute__((interrupt("SWI"), naked));
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118 * The scheduler can only be started from ARM mode, hence the inclusion of this
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121 void vPortISRStartFirstTask( void );
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122 /*-----------------------------------------------------------*/
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124 void vPortISRStartFirstTask( void )
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126 /* Simply start the scheduler. This is included here as it can only be
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127 called from ARM mode. */
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128 portRESTORE_CONTEXT();
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130 /*-----------------------------------------------------------*/
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133 * Called by portYIELD() or taskYIELD() to manually force a context switch.
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135 * When a context switch is performed from the task level the saved task
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136 * context is made to look as if it occurred from within the tick ISR. This
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137 * way the same restore context function can be used when restoring the context
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138 * saved from the ISR or that saved from a call to vPortYieldProcessor.
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140 void vPortYieldProcessor( void )
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142 /* Within an IRQ ISR the link register has an offset from the true return
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143 address, but an SWI ISR does not. Add the offset manually so the same
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144 ISR return code can be used in both cases. */
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145 __asm volatile ( "ADD LR, LR, #4" );
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147 /* Perform the context switch. First save the context of the current task. */
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148 portSAVE_CONTEXT();
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150 /* Find the highest priority task that is ready to run. */
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151 __asm volatile ( "bl vTaskSwitchContext" );
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153 /* Restore the context of the new task. */
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154 portRESTORE_CONTEXT();
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156 /*-----------------------------------------------------------*/
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159 * The ISR used for the scheduler tick.
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161 void vTickISR( void ) __attribute__((naked));
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162 void vTickISR( void )
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164 /* Save the context of the interrupted task. */
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165 portSAVE_CONTEXT();
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167 /* Increment the RTOS tick count, then look for the highest priority
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168 task that is ready to run. */
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171 " bl xTaskIncrementTick \t\n" \
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172 " cmp r0, #0 \t\n" \
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173 " beq SkipContextSwitch \t\n" \
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174 " bl vTaskSwitchContext \t\n" \
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175 "SkipContextSwitch: \t\n"
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178 /* Ready for the next interrupt. */
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179 T0_IR = portTIMER_MATCH_ISR_BIT;
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180 VICVectAddr = portCLEAR_VIC_INTERRUPT;
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182 /* Restore the context of the new task. */
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183 portRESTORE_CONTEXT();
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185 /*-----------------------------------------------------------*/
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188 * The interrupt management utilities can only be called from ARM mode. When
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189 * THUMB_INTERWORK is defined the utilities are defined as functions here to
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190 * ensure a switch to ARM mode. When THUMB_INTERWORK is not defined then
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191 * the utilities are defined as macros in portmacro.h - as per other ports.
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193 #ifdef THUMB_INTERWORK
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195 void vPortDisableInterruptsFromThumb( void ) __attribute__ ((naked));
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196 void vPortEnableInterruptsFromThumb( void ) __attribute__ ((naked));
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198 void vPortDisableInterruptsFromThumb( void )
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201 "STMDB SP!, {R0} \n\t" /* Push R0. */
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202 "MRS R0, CPSR \n\t" /* Get CPSR. */
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203 "ORR R0, R0, #0xC0 \n\t" /* Disable IRQ, FIQ. */
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204 "MSR CPSR, R0 \n\t" /* Write back modified value. */
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205 "LDMIA SP!, {R0} \n\t" /* Pop R0. */
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206 "BX R14" ); /* Return back to thumb. */
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209 void vPortEnableInterruptsFromThumb( void )
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212 "STMDB SP!, {R0} \n\t" /* Push R0. */
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213 "MRS R0, CPSR \n\t" /* Get CPSR. */
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214 "BIC R0, R0, #0xC0 \n\t" /* Enable IRQ, FIQ. */
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215 "MSR CPSR, R0 \n\t" /* Write back modified value. */
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216 "LDMIA SP!, {R0} \n\t" /* Pop R0. */
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217 "BX R14" ); /* Return back to thumb. */
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220 #endif /* THUMB_INTERWORK */
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222 /* The code generated by the GCC compiler uses the stack in different ways at
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223 different optimisation levels. The interrupt flags can therefore not always
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224 be saved to the stack. Instead the critical section nesting level is stored
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225 in a variable, which is then saved as part of the stack context. */
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226 void vPortEnterCritical( void )
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228 /* Disable interrupts as per portDISABLE_INTERRUPTS(); */
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230 "STMDB SP!, {R0} \n\t" /* Push R0. */
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231 "MRS R0, CPSR \n\t" /* Get CPSR. */
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232 "ORR R0, R0, #0xC0 \n\t" /* Disable IRQ, FIQ. */
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233 "MSR CPSR, R0 \n\t" /* Write back modified value. */
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234 "LDMIA SP!, {R0}" ); /* Pop R0. */
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236 /* Now interrupts are disabled ulCriticalNesting can be accessed
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237 directly. Increment ulCriticalNesting to keep a count of how many times
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238 portENTER_CRITICAL() has been called. */
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239 ulCriticalNesting++;
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242 void vPortExitCritical( void )
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244 if( ulCriticalNesting > portNO_CRITICAL_NESTING )
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246 /* Decrement the nesting count as we are leaving a critical section. */
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247 ulCriticalNesting--;
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249 /* If the nesting level has reached zero then interrupts should be
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251 if( ulCriticalNesting == portNO_CRITICAL_NESTING )
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253 /* Enable interrupts as per portEXIT_CRITICAL(). */
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255 "STMDB SP!, {R0} \n\t" /* Push R0. */
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256 "MRS R0, CPSR \n\t" /* Get CPSR. */
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257 "BIC R0, R0, #0xC0 \n\t" /* Enable IRQ, FIQ. */
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258 "MSR CPSR, R0 \n\t" /* Write back modified value. */
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259 "LDMIA SP!, {R0}" ); /* Pop R0. */
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