2 FreeRTOS V8.2.0rc1 - Copyright (C) 2014 Real Time Engineers Ltd.
\r
5 VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
\r
7 This file is part of the FreeRTOS distribution.
\r
9 FreeRTOS is free software; you can redistribute it and/or modify it under
\r
10 the terms of the GNU General Public License (version 2) as published by the
\r
11 Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.
\r
13 >>! NOTE: The modification to the GPL is included to allow you to !<<
\r
14 >>! distribute a combined work that includes FreeRTOS without being !<<
\r
15 >>! obliged to provide the source code for proprietary components !<<
\r
16 >>! outside of the FreeRTOS kernel. !<<
\r
18 FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
\r
19 WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
\r
20 FOR A PARTICULAR PURPOSE. Full license text is available on the following
\r
21 link: http://www.freertos.org/a00114.html
\r
25 ***************************************************************************
\r
27 * Having a problem? Start by reading the FAQ "My application does *
\r
28 * not run, what could be wrong?". Have you defined configASSERT()? *
\r
30 * http://www.FreeRTOS.org/FAQHelp.html *
\r
32 ***************************************************************************
\r
34 ***************************************************************************
\r
36 * FreeRTOS provides completely free yet professionally developed, *
\r
37 * robust, strictly quality controlled, supported, and cross *
\r
38 * platform software that is more than just the market leader, it *
\r
39 * is the industry's de facto standard. *
\r
41 * Help yourself get started quickly while simultaneously helping *
\r
42 * to support the FreeRTOS project by purchasing a FreeRTOS *
\r
43 * tutorial book, reference manual, or both: *
\r
44 * http://www.FreeRTOS.org/Documentation *
\r
46 ***************************************************************************
\r
48 ***************************************************************************
\r
50 * Investing in training allows your team to be as productive as *
\r
51 * possible as early as possible, lowering your overall development *
\r
52 * cost, and enabling you to bring a more robust product to market *
\r
53 * earlier than would otherwise be possible. Richard Barry is both *
\r
54 * the architect and key author of FreeRTOS, and so also the world's *
\r
55 * leading authority on what is the world's most popular real time *
\r
56 * kernel for deeply embedded MCU designs. Obtaining your training *
\r
57 * from Richard ensures your team will gain directly from his in-depth *
\r
58 * product knowledge and years of usage experience. Contact Real Time *
\r
59 * Engineers Ltd to enquire about the FreeRTOS Masterclass, presented *
\r
60 * by Richard Barry: http://www.FreeRTOS.org/contact
\r
62 ***************************************************************************
\r
64 ***************************************************************************
\r
66 * You are receiving this top quality software for free. Please play *
\r
67 * fair and reciprocate by reporting any suspected issues and *
\r
68 * participating in the community forum: *
\r
69 * http://www.FreeRTOS.org/support *
\r
73 ***************************************************************************
\r
75 http://www.FreeRTOS.org - Documentation, books, training, latest versions,
\r
76 license and Real Time Engineers Ltd. contact details.
\r
78 http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
\r
79 including FreeRTOS+Trace - an indispensable productivity tool, a DOS
\r
80 compatible FAT file system, and our tiny thread aware UDP/IP stack.
\r
82 http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.
\r
83 Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.
\r
85 http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High
\r
86 Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS
\r
87 licenses offer ticketed support, indemnification and commercial middleware.
\r
89 http://www.SafeRTOS.com - High Integrity Systems also provide a safety
\r
90 engineered and independently SIL3 certified version for use in safety and
\r
91 mission critical applications that require provable dependability.
\r
97 /*-----------------------------------------------------------
\r
98 * Components that can be compiled to either ARM or THUMB mode are
\r
99 * contained in port.c The ISR routines, which can only be compiled
\r
100 * to ARM mode, are contained in this file.
\r
101 *----------------------------------------------------------*/
\r
104 Changes from V2.5.2
\r
106 + The critical section management functions have been changed. These no
\r
107 longer modify the stack and are safe to use at all optimisation levels.
\r
108 The functions are now also the same for both ARM and THUMB modes.
\r
110 Changes from V2.6.0
\r
112 + Removed the 'static' from the definition of vNonPreemptiveTick() to
\r
113 allow the demo to link when using the cooperative scheduler.
\r
115 Changes from V3.2.4
\r
117 + The assembler statements are now included in a single asm block rather
\r
118 than each line having its own asm block.
\r
122 /* Scheduler includes. */
\r
123 #include "FreeRTOS.h"
\r
125 /* Constants required to handle interrupts. */
\r
126 #define portTIMER_MATCH_ISR_BIT ( ( uint8_t ) 0x01 )
\r
127 #define portCLEAR_VIC_INTERRUPT ( ( uint32_t ) 0 )
\r
129 /* Constants required to handle critical sections. */
\r
130 #define portNO_CRITICAL_NESTING ( ( uint32_t ) 0 )
\r
131 volatile uint32_t ulCriticalNesting = 9999UL;
\r
133 /*-----------------------------------------------------------*/
\r
135 /* ISR to handle manual context switches (from a call to taskYIELD()). */
\r
136 void vPortYieldProcessor( void ) __attribute__((interrupt("SWI"), naked));
\r
139 * The scheduler can only be started from ARM mode, hence the inclusion of this
\r
142 void vPortISRStartFirstTask( void );
\r
143 /*-----------------------------------------------------------*/
\r
145 void vPortISRStartFirstTask( void )
\r
147 /* Simply start the scheduler. This is included here as it can only be
\r
148 called from ARM mode. */
\r
149 portRESTORE_CONTEXT();
\r
151 /*-----------------------------------------------------------*/
\r
154 * Called by portYIELD() or taskYIELD() to manually force a context switch.
\r
156 * When a context switch is performed from the task level the saved task
\r
157 * context is made to look as if it occurred from within the tick ISR. This
\r
158 * way the same restore context function can be used when restoring the context
\r
159 * saved from the ISR or that saved from a call to vPortYieldProcessor.
\r
161 void vPortYieldProcessor( void )
\r
163 /* Within an IRQ ISR the link register has an offset from the true return
\r
164 address, but an SWI ISR does not. Add the offset manually so the same
\r
165 ISR return code can be used in both cases. */
\r
166 __asm volatile ( "ADD LR, LR, #4" );
\r
168 /* Perform the context switch. First save the context of the current task. */
\r
169 portSAVE_CONTEXT();
\r
171 /* Find the highest priority task that is ready to run. */
\r
172 __asm volatile ( "bl vTaskSwitchContext" );
\r
174 /* Restore the context of the new task. */
\r
175 portRESTORE_CONTEXT();
\r
177 /*-----------------------------------------------------------*/
\r
180 * The ISR used for the scheduler tick.
\r
182 void vTickISR( void ) __attribute__((naked));
\r
183 void vTickISR( void )
\r
185 /* Save the context of the interrupted task. */
\r
186 portSAVE_CONTEXT();
\r
188 /* Increment the RTOS tick count, then look for the highest priority
\r
189 task that is ready to run. */
\r
192 " bl xTaskIncrementTick \t\n" \
\r
193 " cmp r0, #0 \t\n" \
\r
194 " beq SkipContextSwitch \t\n" \
\r
195 " bl vTaskSwitchContext \t\n" \
\r
196 "SkipContextSwitch: \t\n"
\r
199 /* Ready for the next interrupt. */
\r
200 T0_IR = portTIMER_MATCH_ISR_BIT;
\r
201 VICVectAddr = portCLEAR_VIC_INTERRUPT;
\r
203 /* Restore the context of the new task. */
\r
204 portRESTORE_CONTEXT();
\r
206 /*-----------------------------------------------------------*/
\r
209 * The interrupt management utilities can only be called from ARM mode. When
\r
210 * THUMB_INTERWORK is defined the utilities are defined as functions here to
\r
211 * ensure a switch to ARM mode. When THUMB_INTERWORK is not defined then
\r
212 * the utilities are defined as macros in portmacro.h - as per other ports.
\r
214 #ifdef THUMB_INTERWORK
\r
216 void vPortDisableInterruptsFromThumb( void ) __attribute__ ((naked));
\r
217 void vPortEnableInterruptsFromThumb( void ) __attribute__ ((naked));
\r
219 void vPortDisableInterruptsFromThumb( void )
\r
222 "STMDB SP!, {R0} \n\t" /* Push R0. */
\r
223 "MRS R0, CPSR \n\t" /* Get CPSR. */
\r
224 "ORR R0, R0, #0xC0 \n\t" /* Disable IRQ, FIQ. */
\r
225 "MSR CPSR, R0 \n\t" /* Write back modified value. */
\r
226 "LDMIA SP!, {R0} \n\t" /* Pop R0. */
\r
227 "BX R14" ); /* Return back to thumb. */
\r
230 void vPortEnableInterruptsFromThumb( void )
\r
233 "STMDB SP!, {R0} \n\t" /* Push R0. */
\r
234 "MRS R0, CPSR \n\t" /* Get CPSR. */
\r
235 "BIC R0, R0, #0xC0 \n\t" /* Enable IRQ, FIQ. */
\r
236 "MSR CPSR, R0 \n\t" /* Write back modified value. */
\r
237 "LDMIA SP!, {R0} \n\t" /* Pop R0. */
\r
238 "BX R14" ); /* Return back to thumb. */
\r
241 #endif /* THUMB_INTERWORK */
\r
243 /* The code generated by the GCC compiler uses the stack in different ways at
\r
244 different optimisation levels. The interrupt flags can therefore not always
\r
245 be saved to the stack. Instead the critical section nesting level is stored
\r
246 in a variable, which is then saved as part of the stack context. */
\r
247 void vPortEnterCritical( void )
\r
249 /* Disable interrupts as per portDISABLE_INTERRUPTS(); */
\r
251 "STMDB SP!, {R0} \n\t" /* Push R0. */
\r
252 "MRS R0, CPSR \n\t" /* Get CPSR. */
\r
253 "ORR R0, R0, #0xC0 \n\t" /* Disable IRQ, FIQ. */
\r
254 "MSR CPSR, R0 \n\t" /* Write back modified value. */
\r
255 "LDMIA SP!, {R0}" ); /* Pop R0. */
\r
257 /* Now interrupts are disabled ulCriticalNesting can be accessed
\r
258 directly. Increment ulCriticalNesting to keep a count of how many times
\r
259 portENTER_CRITICAL() has been called. */
\r
260 ulCriticalNesting++;
\r
263 void vPortExitCritical( void )
\r
265 if( ulCriticalNesting > portNO_CRITICAL_NESTING )
\r
267 /* Decrement the nesting count as we are leaving a critical section. */
\r
268 ulCriticalNesting--;
\r
270 /* If the nesting level has reached zero then interrupts should be
\r
272 if( ulCriticalNesting == portNO_CRITICAL_NESTING )
\r
274 /* Enable interrupts as per portEXIT_CRITICAL(). */
\r
276 "STMDB SP!, {R0} \n\t" /* Push R0. */
\r
277 "MRS R0, CPSR \n\t" /* Get CPSR. */
\r
278 "BIC R0, R0, #0xC0 \n\t" /* Enable IRQ, FIQ. */
\r
279 "MSR CPSR, R0 \n\t" /* Write back modified value. */
\r
280 "LDMIA SP!, {R0}" ); /* Pop R0. */
\r