2 * FreeRTOS Kernel V10.3.0
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3 * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
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5 * Permission is hereby granted, free of charge, to any person obtaining a copy of
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6 * this software and associated documentation files (the "Software"), to deal in
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7 * the Software without restriction, including without limitation the rights to
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8 * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
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9 * the Software, and to permit persons to whom the Software is furnished to do so,
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10 * subject to the following conditions:
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12 * The above copyright notice and this permission notice shall be included in all
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13 * copies or substantial portions of the Software.
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15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
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17 * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
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18 * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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19 * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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20 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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22 * http://www.FreeRTOS.org
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23 * http://aws.amazon.com/freertos
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25 * 1 tab == 4 spaces!
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29 /*-----------------------------------------------------------
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30 * Implementation of functions defined in portable.h for the ARM7 port.
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32 * Components that can be compiled to either ARM or THUMB mode are
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33 * contained in this file. The ISR routines, which can only be compiled
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34 * to ARM mode are contained in portISR.c.
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35 *----------------------------------------------------------*/
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38 /* Standard includes. */
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41 /* Scheduler includes. */
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42 #include "FreeRTOS.h"
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45 /* Constants required to setup the task context. */
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46 #define portINITIAL_SPSR ( ( StackType_t ) 0x1f ) /* System mode, ARM mode, interrupts enabled. */
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47 #define portTHUMB_MODE_BIT ( ( StackType_t ) 0x20 )
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48 #define portINSTRUCTION_SIZE ( ( StackType_t ) 4 )
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49 #define portNO_CRITICAL_SECTION_NESTING ( ( StackType_t ) 0 )
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51 /* Constants required to setup the tick ISR. */
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52 #define portENABLE_TIMER ( ( uint8_t ) 0x01 )
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53 #define portPRESCALE_VALUE 0x00
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54 #define portINTERRUPT_ON_MATCH ( ( uint32_t ) 0x01 )
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55 #define portRESET_COUNT_ON_MATCH ( ( uint32_t ) 0x02 )
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57 /* Constants required to setup the VIC for the tick ISR. */
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58 #define portTIMER_VIC_CHANNEL ( ( uint32_t ) 0x0004 )
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59 #define portTIMER_VIC_CHANNEL_BIT ( ( uint32_t ) 0x0010 )
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60 #define portTIMER_VIC_ENABLE ( ( uint32_t ) 0x0020 )
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62 /*-----------------------------------------------------------*/
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64 /* Setup the timer to generate the tick interrupts. */
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65 static void prvSetupTimerInterrupt( void );
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68 * The scheduler can only be started from ARM mode, so
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69 * vPortISRStartFirstSTask() is defined in portISR.c.
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71 extern void vPortISRStartFirstTask( void );
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73 /*-----------------------------------------------------------*/
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76 * Initialise the stack of a task to look exactly as if a call to
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77 * portSAVE_CONTEXT had been called.
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79 * See header file for description.
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81 StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
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83 StackType_t *pxOriginalTOS;
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85 pxOriginalTOS = pxTopOfStack;
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87 /* To ensure asserts in tasks.c don't fail, although in this case the assert
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88 is not really required. */
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91 /* Setup the initial stack of the task. The stack is set exactly as
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92 expected by the portRESTORE_CONTEXT() macro. */
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94 /* First on the stack is the return address - which in this case is the
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95 start of the task. The offset is added to make the return address appear
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96 as it would within an IRQ ISR. */
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97 *pxTopOfStack = ( StackType_t ) pxCode + portINSTRUCTION_SIZE;
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100 *pxTopOfStack = ( StackType_t ) 0x00000000; /* R14 */
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102 *pxTopOfStack = ( StackType_t ) pxOriginalTOS; /* Stack used when task starts goes in R13. */
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104 *pxTopOfStack = ( StackType_t ) 0x12121212; /* R12 */
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106 *pxTopOfStack = ( StackType_t ) 0x11111111; /* R11 */
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108 *pxTopOfStack = ( StackType_t ) 0x10101010; /* R10 */
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110 *pxTopOfStack = ( StackType_t ) 0x09090909; /* R9 */
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112 *pxTopOfStack = ( StackType_t ) 0x08080808; /* R8 */
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114 *pxTopOfStack = ( StackType_t ) 0x07070707; /* R7 */
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116 *pxTopOfStack = ( StackType_t ) 0x06060606; /* R6 */
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118 *pxTopOfStack = ( StackType_t ) 0x05050505; /* R5 */
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120 *pxTopOfStack = ( StackType_t ) 0x04040404; /* R4 */
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122 *pxTopOfStack = ( StackType_t ) 0x03030303; /* R3 */
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124 *pxTopOfStack = ( StackType_t ) 0x02020202; /* R2 */
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126 *pxTopOfStack = ( StackType_t ) 0x01010101; /* R1 */
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129 /* When the task starts is will expect to find the function parameter in
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131 *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
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134 /* The last thing onto the stack is the status register, which is set for
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135 system mode, with interrupts enabled. */
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136 *pxTopOfStack = ( StackType_t ) portINITIAL_SPSR;
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138 if( ( ( uint32_t ) pxCode & 0x01UL ) != 0x00 )
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140 /* We want the task to start in thumb mode. */
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141 *pxTopOfStack |= portTHUMB_MODE_BIT;
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146 /* Some optimisation levels use the stack differently to others. This
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147 means the interrupt flags cannot always be stored on the stack and will
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148 instead be stored in a variable, which is then saved as part of the
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150 *pxTopOfStack = portNO_CRITICAL_SECTION_NESTING;
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152 return pxTopOfStack;
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154 /*-----------------------------------------------------------*/
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156 BaseType_t xPortStartScheduler( void )
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158 /* Start the timer that generates the tick ISR. Interrupts are disabled
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160 prvSetupTimerInterrupt();
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162 /* Start the first task. */
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163 vPortISRStartFirstTask();
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165 /* Should not get here! */
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168 /*-----------------------------------------------------------*/
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170 void vPortEndScheduler( void )
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172 /* It is unlikely that the ARM port will require this function as there
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173 is nothing to return to. */
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175 /*-----------------------------------------------------------*/
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178 * Setup the timer 0 to generate the tick interrupts at the required frequency.
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180 static void prvSetupTimerInterrupt( void )
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182 uint32_t ulCompareMatch;
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184 PCLKSEL0 = (PCLKSEL0 & (~(0x3<<2))) | (0x01 << 2);
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185 T0TCR = 2; /* Stop and reset the timer */
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186 T0CTCR = 0; /* Timer mode */
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188 /* A 1ms tick does not require the use of the timer prescale. This is
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189 defaulted to zero but can be used if necessary. */
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190 T0PR = portPRESCALE_VALUE;
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192 /* Calculate the match value required for our wanted tick rate. */
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193 ulCompareMatch = configCPU_CLOCK_HZ / configTICK_RATE_HZ;
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195 /* Protect against divide by zero. Using an if() statement still results
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196 in a warning - hence the #if. */
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197 #if portPRESCALE_VALUE != 0
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199 ulCompareMatch /= ( portPRESCALE_VALUE + 1 );
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202 T0MR1 = ulCompareMatch;
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204 /* Generate tick with timer 0 compare match. */
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205 T0MCR = (3 << 3); /* Reset timer on match and generate interrupt */
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207 /* Setup the VIC for the timer. */
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208 VICIntEnable = 0x00000010;
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210 /* The ISR installed depends on whether the preemptive or cooperative
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211 scheduler is being used. */
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212 #if configUSE_PREEMPTION == 1
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214 extern void ( vPreemptiveTick )( void );
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215 VICVectAddr4 = ( int32_t ) vPreemptiveTick;
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219 extern void ( vNonPreemptiveTick )( void );
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220 VICVectAddr4 = ( int32_t ) vNonPreemptiveTick;
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226 /* Start the timer - interrupts are disabled when this function is called
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227 so it is okay to do this here. */
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228 T0TCR = portENABLE_TIMER;
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230 /*-----------------------------------------------------------*/
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