2 FreeRTOS V9.0.0rc2 - Copyright (C) 2016 Real Time Engineers Ltd.
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5 VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
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7 This file is part of the FreeRTOS distribution.
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9 FreeRTOS is free software; you can redistribute it and/or modify it under
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10 the terms of the GNU General Public License (version 2) as published by the
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11 Free Software Foundation >>>> AND MODIFIED BY <<<< the FreeRTOS exception.
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13 ***************************************************************************
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14 >>! NOTE: The modification to the GPL is included to allow you to !<<
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15 >>! distribute a combined work that includes FreeRTOS without being !<<
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16 >>! obliged to provide the source code for proprietary components !<<
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17 >>! outside of the FreeRTOS kernel. !<<
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18 ***************************************************************************
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20 FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
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21 WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
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22 FOR A PARTICULAR PURPOSE. Full license text is available on the following
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23 link: http://www.freertos.org/a00114.html
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25 ***************************************************************************
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27 * FreeRTOS provides completely free yet professionally developed, *
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28 * robust, strictly quality controlled, supported, and cross *
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29 * platform software that is more than just the market leader, it *
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30 * is the industry's de facto standard. *
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32 * Help yourself get started quickly while simultaneously helping *
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33 * to support the FreeRTOS project by purchasing a FreeRTOS *
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34 * tutorial book, reference manual, or both: *
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35 * http://www.FreeRTOS.org/Documentation *
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37 ***************************************************************************
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39 http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading
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40 the FAQ page "My application does not run, what could be wrong?". Have you
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41 defined configASSERT()?
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43 http://www.FreeRTOS.org/support - In return for receiving this top quality
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44 embedded software for free we request you assist our global community by
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45 participating in the support forum.
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47 http://www.FreeRTOS.org/training - Investing in training allows your team to
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48 be as productive as possible as early as possible. Now you can receive
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49 FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers
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50 Ltd, and the world's leading authority on the world's leading RTOS.
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52 http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
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53 including FreeRTOS+Trace - an indispensable productivity tool, a DOS
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54 compatible FAT file system, and our tiny thread aware UDP/IP stack.
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56 http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.
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57 Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.
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59 http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High
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60 Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS
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61 licenses offer ticketed support, indemnification and commercial middleware.
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63 http://www.SafeRTOS.com - High Integrity Systems also provide a safety
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64 engineered and independently SIL3 certified version for use in safety and
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65 mission critical applications that require provable dependability.
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71 /*-----------------------------------------------------------
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72 * Components that can be compiled to either ARM or THUMB mode are
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73 * contained in port.c The ISR routines, which can only be compiled
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74 * to ARM mode, are contained in this file.
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75 *----------------------------------------------------------*/
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77 /* Scheduler includes. */
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78 #include "FreeRTOS.h"
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81 /* Constants required to handle interrupts. */
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82 #define portTIMER_MATCH_ISR_BIT ( ( uint8_t ) 0x01 )
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83 #define portCLEAR_VIC_INTERRUPT ( ( uint32_t ) 0 )
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85 /* Constants required to handle critical sections. */
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86 #define portNO_CRITICAL_NESTING ( ( uint32_t ) 0 )
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87 volatile uint32_t ulCriticalNesting = 9999UL;
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89 /*-----------------------------------------------------------*/
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91 /* ISR to handle manual context switches (from a call to taskYIELD()). */
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92 void vPortYieldProcessor( void ) __attribute__((interrupt("SWI"), naked));
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95 * The scheduler can only be started from ARM mode, hence the inclusion of this
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98 void vPortISRStartFirstTask( void );
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99 /*-----------------------------------------------------------*/
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101 void vPortISRStartFirstTask( void )
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103 /* Simply start the scheduler. This is included here as it can only be
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104 called from ARM mode. */
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105 portRESTORE_CONTEXT();
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107 /*-----------------------------------------------------------*/
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110 * Called by portYIELD() or taskYIELD() to manually force a context switch.
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112 * When a context switch is performed from the task level the saved task
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113 * context is made to look as if it occurred from within the tick ISR. This
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114 * way the same restore context function can be used when restoring the context
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115 * saved from the ISR or that saved from a call to vPortYieldProcessor.
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117 void vPortYieldProcessor( void )
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119 /* Within an IRQ ISR the link register has an offset from the true return
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120 address, but an SWI ISR does not. Add the offset manually so the same
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121 ISR return code can be used in both cases. */
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122 __asm volatile ( "ADD LR, LR, #4" );
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124 /* Perform the context switch. First save the context of the current task. */
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125 portSAVE_CONTEXT();
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127 /* Find the highest priority task that is ready to run. */
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128 __asm volatile( "bl vTaskSwitchContext" );
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130 /* Restore the context of the new task. */
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131 portRESTORE_CONTEXT();
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133 /*-----------------------------------------------------------*/
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136 * The ISR used for the scheduler tick depends on whether the cooperative or
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137 * the preemptive scheduler is being used.
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141 #if configUSE_PREEMPTION == 0
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143 /* The cooperative scheduler requires a normal IRQ service routine to
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144 simply increment the system tick. */
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145 void vNonPreemptiveTick( void ) __attribute__ ((interrupt ("IRQ")));
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146 void vNonPreemptiveTick( void )
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148 xTaskIncrementTick();
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150 VICVectAddr = portCLEAR_VIC_INTERRUPT;
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155 /* The preemptive scheduler is defined as "naked" as the full context is
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156 saved on entry as part of the context switch. */
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157 void vPreemptiveTick( void ) __attribute__((naked));
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158 void vPreemptiveTick( void )
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160 /* Save the context of the interrupted task. */
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161 portSAVE_CONTEXT();
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163 /* Increment the RTOS tick count, then look for the highest priority
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164 task that is ready to run. */
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167 " bl xTaskIncrementTick \t\n" \
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168 " cmp r0, #0 \t\n" \
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169 " beq SkipContextSwitch \t\n" \
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170 " bl vTaskSwitchContext \t\n" \
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171 "SkipContextSwitch: \t\n"
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174 /* Ready for the next interrupt. */
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176 VICVectAddr = portCLEAR_VIC_INTERRUPT;
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178 /* Restore the context of the new task. */
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179 portRESTORE_CONTEXT();
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183 /*-----------------------------------------------------------*/
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186 * The interrupt management utilities can only be called from ARM mode. When
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187 * THUMB_INTERWORK is defined the utilities are defined as functions here to
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188 * ensure a switch to ARM mode. When THUMB_INTERWORK is not defined then
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189 * the utilities are defined as macros in portmacro.h - as per other ports.
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191 #ifdef THUMB_INTERWORK
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193 void vPortDisableInterruptsFromThumb( void ) __attribute__ ((naked));
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194 void vPortEnableInterruptsFromThumb( void ) __attribute__ ((naked));
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196 void vPortDisableInterruptsFromThumb( void )
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199 "STMDB SP!, {R0} \n\t" /* Push R0. */
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200 "MRS R0, CPSR \n\t" /* Get CPSR. */
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201 "ORR R0, R0, #0xC0 \n\t" /* Disable IRQ, FIQ. */
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202 "MSR CPSR, R0 \n\t" /* Write back modified value. */
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203 "LDMIA SP!, {R0} \n\t" /* Pop R0. */
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204 "BX R14" ); /* Return back to thumb. */
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207 void vPortEnableInterruptsFromThumb( void )
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210 "STMDB SP!, {R0} \n\t" /* Push R0. */
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211 "MRS R0, CPSR \n\t" /* Get CPSR. */
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212 "BIC R0, R0, #0xC0 \n\t" /* Enable IRQ, FIQ. */
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213 "MSR CPSR, R0 \n\t" /* Write back modified value. */
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214 "LDMIA SP!, {R0} \n\t" /* Pop R0. */
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215 "BX R14" ); /* Return back to thumb. */
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218 #endif /* THUMB_INTERWORK */
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220 /* The code generated by the GCC compiler uses the stack in different ways at
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221 different optimisation levels. The interrupt flags can therefore not always
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222 be saved to the stack. Instead the critical section nesting level is stored
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223 in a variable, which is then saved as part of the stack context. */
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224 void vPortEnterCritical( void )
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226 /* Disable interrupts as per portDISABLE_INTERRUPTS(); */
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228 "STMDB SP!, {R0} \n\t" /* Push R0. */
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229 "MRS R0, CPSR \n\t" /* Get CPSR. */
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230 "ORR R0, R0, #0xC0 \n\t" /* Disable IRQ, FIQ. */
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231 "MSR CPSR, R0 \n\t" /* Write back modified value. */
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232 "LDMIA SP!, {R0}" ); /* Pop R0. */
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234 /* Now interrupts are disabled ulCriticalNesting can be accessed
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235 directly. Increment ulCriticalNesting to keep a count of how many times
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236 portENTER_CRITICAL() has been called. */
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237 ulCriticalNesting++;
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240 void vPortExitCritical( void )
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242 if( ulCriticalNesting > portNO_CRITICAL_NESTING )
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244 /* Decrement the nesting count as we are leaving a critical section. */
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245 ulCriticalNesting--;
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247 /* If the nesting level has reached zero then interrupts should be
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249 if( ulCriticalNesting == portNO_CRITICAL_NESTING )
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251 /* Enable interrupts as per portEXIT_CRITICAL(). */
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253 "STMDB SP!, {R0} \n\t" /* Push R0. */
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254 "MRS R0, CPSR \n\t" /* Get CPSR. */
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255 "BIC R0, R0, #0xC0 \n\t" /* Enable IRQ, FIQ. */
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256 "MSR CPSR, R0 \n\t" /* Write back modified value. */
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257 "LDMIA SP!, {R0}" ); /* Pop R0. */
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