2 * FreeRTOS Kernel V10.3.0
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3 * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
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5 * Permission is hereby granted, free of charge, to any person obtaining a copy of
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6 * this software and associated documentation files (the "Software"), to deal in
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7 * the Software without restriction, including without limitation the rights to
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8 * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
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9 * the Software, and to permit persons to whom the Software is furnished to do so,
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10 * subject to the following conditions:
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12 * The above copyright notice and this permission notice shall be included in all
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13 * copies or substantial portions of the Software.
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15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
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17 * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
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18 * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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19 * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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20 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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22 * http://www.FreeRTOS.org
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23 * http://aws.amazon.com/freertos
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25 * 1 tab == 4 spaces!
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28 /* Standard includes. */
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31 /* Scheduler includes. */
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32 #include "FreeRTOS.h"
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35 #ifndef configINTERRUPT_CONTROLLER_BASE_ADDRESS
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36 #error configINTERRUPT_CONTROLLER_BASE_ADDRESS must be defined. See http://www.freertos.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html
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39 #ifndef configINTERRUPT_CONTROLLER_CPU_INTERFACE_OFFSET
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40 #error configINTERRUPT_CONTROLLER_CPU_INTERFACE_OFFSET must be defined. See http://www.freertos.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html
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43 #ifndef configUNIQUE_INTERRUPT_PRIORITIES
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44 #error configUNIQUE_INTERRUPT_PRIORITIES must be defined. See http://www.freertos.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html
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47 #ifndef configSETUP_TICK_INTERRUPT
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48 #error configSETUP_TICK_INTERRUPT() must be defined. See http://www.freertos.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html
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49 #endif /* configSETUP_TICK_INTERRUPT */
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51 #ifndef configMAX_API_CALL_INTERRUPT_PRIORITY
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52 #error configMAX_API_CALL_INTERRUPT_PRIORITY must be defined. See http://www.freertos.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html
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55 #if configMAX_API_CALL_INTERRUPT_PRIORITY == 0
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56 #error configMAX_API_CALL_INTERRUPT_PRIORITY must not be set to 0
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59 #if configMAX_API_CALL_INTERRUPT_PRIORITY > configUNIQUE_INTERRUPT_PRIORITIES
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60 #error configMAX_API_CALL_INTERRUPT_PRIORITY must be less than or equal to configUNIQUE_INTERRUPT_PRIORITIES as the lower the numeric priority value the higher the logical interrupt priority
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63 #if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
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64 /* Check the configuration. */
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65 #if( configMAX_PRIORITIES > 32 )
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66 #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
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68 #endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
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70 /* In case security extensions are implemented. */
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71 #if configMAX_API_CALL_INTERRUPT_PRIORITY <= ( configUNIQUE_INTERRUPT_PRIORITIES / 2 )
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72 #error configMAX_API_CALL_INTERRUPT_PRIORITY must be greater than ( configUNIQUE_INTERRUPT_PRIORITIES / 2 )
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75 /* Some vendor specific files default configCLEAR_TICK_INTERRUPT() in
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77 #ifndef configCLEAR_TICK_INTERRUPT
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78 #define configCLEAR_TICK_INTERRUPT()
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81 /* A critical section is exited when the critical section nesting count reaches
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83 #define portNO_CRITICAL_NESTING ( ( uint32_t ) 0 )
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85 /* In all GICs 255 can be written to the priority mask register to unmask all
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86 (but the lowest) interrupt priority. */
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87 #define portUNMASK_VALUE ( 0xFFUL )
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89 /* Tasks are not created with a floating point context, but can be given a
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90 floating point context after they have been created. A variable is stored as
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91 part of the tasks context that holds portNO_FLOATING_POINT_CONTEXT if the task
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92 does not have an FPU context, or any other value if the task does have an FPU
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94 #define portNO_FLOATING_POINT_CONTEXT ( ( StackType_t ) 0 )
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96 /* Constants required to setup the initial task context. */
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97 #define portINITIAL_SPSR ( ( StackType_t ) 0x1f ) /* System mode, ARM mode, IRQ enabled FIQ enabled. */
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98 #define portTHUMB_MODE_BIT ( ( StackType_t ) 0x20 )
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99 #define portINTERRUPT_ENABLE_BIT ( 0x80UL )
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100 #define portTHUMB_MODE_ADDRESS ( 0x01UL )
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102 /* Used by portASSERT_IF_INTERRUPT_PRIORITY_INVALID() when ensuring the binary
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104 #define portBINARY_POINT_BITS ( ( uint8_t ) 0x03 )
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106 /* Masks all bits in the APSR other than the mode bits. */
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107 #define portAPSR_MODE_BITS_MASK ( 0x1F )
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109 /* The value of the mode bits in the APSR when the CPU is executing in user
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111 #define portAPSR_USER_MODE ( 0x10 )
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113 /* The critical section macros only mask interrupts up to an application
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114 determined priority level. Sometimes it is necessary to turn interrupt off in
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115 the CPU itself before modifying certain hardware registers. */
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116 #define portCPU_IRQ_DISABLE() \
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117 __asm volatile ( "CPSID i" ::: "memory" ); \
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118 __asm volatile ( "DSB" ); \
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119 __asm volatile ( "ISB" );
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121 #define portCPU_IRQ_ENABLE() \
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122 __asm volatile ( "CPSIE i" ::: "memory" ); \
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123 __asm volatile ( "DSB" ); \
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124 __asm volatile ( "ISB" );
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127 /* Macro to unmask all interrupt priorities. */
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128 #define portCLEAR_INTERRUPT_MASK() \
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130 portCPU_IRQ_DISABLE(); \
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131 portICCPMR_PRIORITY_MASK_REGISTER = portUNMASK_VALUE; \
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132 __asm volatile ( "DSB \n" \
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134 portCPU_IRQ_ENABLE(); \
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137 #define portINTERRUPT_PRIORITY_REGISTER_OFFSET 0x400UL
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138 #define portMAX_8_BIT_VALUE ( ( uint8_t ) 0xff )
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139 #define portBIT_0_SET ( ( uint8_t ) 0x01 )
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141 /* Let the user override the pre-loading of the initial LR with the address of
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142 prvTaskExitError() in case it messes up unwinding of the stack in the
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144 #ifdef configTASK_RETURN_ADDRESS
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145 #define portTASK_RETURN_ADDRESS configTASK_RETURN_ADDRESS
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147 #define portTASK_RETURN_ADDRESS prvTaskExitError
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150 /* The space on the stack required to hold the FPU registers. This is 32 64-bit
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151 registers, plus a 32-bit status register. */
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152 #define portFPU_REGISTER_WORDS ( ( 32 * 2 ) + 1 )
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154 /*-----------------------------------------------------------*/
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157 * Starts the first task executing. This function is necessarily written in
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158 * assembly code so is implemented in portASM.s.
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160 extern void vPortRestoreTaskContext( void );
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163 * Used to catch tasks that attempt to return from their implementing function.
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165 static void prvTaskExitError( void );
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168 * If the application provides an implementation of vApplicationIRQHandler(),
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169 * then it will get called directly without saving the FPU registers on
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170 * interrupt entry, and this weak implementation of
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171 * vApplicationFPUSafeIRQHandler() is just provided to remove linkage errors -
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172 * it should never actually get called so its implementation contains a
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173 * call to configASSERT() that will always fail.
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175 * If the application provides its own implementation of
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176 * vApplicationFPUSafeIRQHandler() then the implementation of
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177 * vApplicationIRQHandler() provided in portASM.S will save the FPU registers
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178 * before calling it.
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180 * Therefore, if the application writer wants FPU registers to be saved on
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181 * interrupt entry their IRQ handler must be called
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182 * vApplicationFPUSafeIRQHandler(), and if the application writer does not want
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183 * FPU registers to be saved on interrupt entry their IRQ handler must be
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184 * called vApplicationIRQHandler().
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186 void vApplicationFPUSafeIRQHandler( uint32_t ulICCIAR ) __attribute__((weak) );
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188 /*-----------------------------------------------------------*/
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190 /* A variable is used to keep track of the critical section nesting. This
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191 variable has to be stored as part of the task context and must be initialised to
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192 a non zero value to ensure interrupts don't inadvertently become unmasked before
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193 the scheduler starts. As it is stored as part of the task context it will
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194 automatically be set to 0 when the first task is started. */
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195 volatile uint32_t ulCriticalNesting = 9999UL;
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197 /* Saved as part of the task context. If ulPortTaskHasFPUContext is non-zero then
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198 a floating point context must be saved and restored for the task. */
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199 volatile uint32_t ulPortTaskHasFPUContext = pdFALSE;
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201 /* Set to 1 to pend a context switch from an ISR. */
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202 volatile uint32_t ulPortYieldRequired = pdFALSE;
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204 /* Counts the interrupt nesting depth. A context switch is only performed if
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205 if the nesting depth is 0. */
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206 volatile uint32_t ulPortInterruptNesting = 0UL;
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208 /* Used in the asm file. */
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209 __attribute__(( used )) const uint32_t ulICCIAR = portICCIAR_INTERRUPT_ACKNOWLEDGE_REGISTER_ADDRESS;
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210 __attribute__(( used )) const uint32_t ulICCEOIR = portICCEOIR_END_OF_INTERRUPT_REGISTER_ADDRESS;
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211 __attribute__(( used )) const uint32_t ulICCPMR = portICCPMR_PRIORITY_MASK_REGISTER_ADDRESS;
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212 __attribute__(( used )) const uint32_t ulMaxAPIPriorityMask = ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT );
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214 /*-----------------------------------------------------------*/
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217 * See header file for description.
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219 StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
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221 /* Setup the initial stack of the task. The stack is set exactly as
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222 expected by the portRESTORE_CONTEXT() macro.
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224 The fist real value on the stack is the status register, which is set for
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225 system mode, with interrupts enabled. A few NULLs are added first to ensure
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226 GDB does not try decoding a non-existent return address. */
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227 *pxTopOfStack = ( StackType_t ) NULL;
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229 *pxTopOfStack = ( StackType_t ) NULL;
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231 *pxTopOfStack = ( StackType_t ) NULL;
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233 *pxTopOfStack = ( StackType_t ) portINITIAL_SPSR;
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235 if( ( ( uint32_t ) pxCode & portTHUMB_MODE_ADDRESS ) != 0x00UL )
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237 /* The task will start in THUMB mode. */
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238 *pxTopOfStack |= portTHUMB_MODE_BIT;
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243 /* Next the return address, which in this case is the start of the task. */
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244 *pxTopOfStack = ( StackType_t ) pxCode;
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247 /* Next all the registers other than the stack pointer. */
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248 *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* R14 */
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250 *pxTopOfStack = ( StackType_t ) 0x12121212; /* R12 */
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252 *pxTopOfStack = ( StackType_t ) 0x11111111; /* R11 */
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254 *pxTopOfStack = ( StackType_t ) 0x10101010; /* R10 */
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256 *pxTopOfStack = ( StackType_t ) 0x09090909; /* R9 */
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258 *pxTopOfStack = ( StackType_t ) 0x08080808; /* R8 */
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260 *pxTopOfStack = ( StackType_t ) 0x07070707; /* R7 */
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262 *pxTopOfStack = ( StackType_t ) 0x06060606; /* R6 */
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264 *pxTopOfStack = ( StackType_t ) 0x05050505; /* R5 */
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266 *pxTopOfStack = ( StackType_t ) 0x04040404; /* R4 */
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268 *pxTopOfStack = ( StackType_t ) 0x03030303; /* R3 */
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270 *pxTopOfStack = ( StackType_t ) 0x02020202; /* R2 */
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272 *pxTopOfStack = ( StackType_t ) 0x01010101; /* R1 */
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274 *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
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277 /* The task will start with a critical nesting count of 0 as interrupts are
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279 *pxTopOfStack = portNO_CRITICAL_NESTING;
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281 #if( configUSE_TASK_FPU_SUPPORT == 1 )
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283 /* The task will start without a floating point context. A task that
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284 uses the floating point hardware must call vPortTaskUsesFPU() before
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285 executing any floating point instructions. */
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287 *pxTopOfStack = portNO_FLOATING_POINT_CONTEXT;
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289 #elif( configUSE_TASK_FPU_SUPPORT == 2 )
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291 /* The task will start with a floating point context. Leave enough
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292 space for the registers - and ensure they are initialised to 0. */
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293 pxTopOfStack -= portFPU_REGISTER_WORDS;
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294 memset( pxTopOfStack, 0x00, portFPU_REGISTER_WORDS * sizeof( StackType_t ) );
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297 *pxTopOfStack = pdTRUE;
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298 ulPortTaskHasFPUContext = pdTRUE;
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302 #error Invalid configUSE_TASK_FPU_SUPPORT setting - configUSE_TASK_FPU_SUPPORT must be set to 1, 2, or left undefined.
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306 return pxTopOfStack;
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308 /*-----------------------------------------------------------*/
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310 static void prvTaskExitError( void )
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312 /* A function that implements a task must not exit or attempt to return to
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313 its caller as there is nothing to return to. If a task wants to exit it
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314 should instead call vTaskDelete( NULL ).
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316 Artificially force an assert() to be triggered if configASSERT() is
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317 defined, then stop here so application writers can catch the error. */
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318 configASSERT( ulPortInterruptNesting == ~0UL );
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319 portDISABLE_INTERRUPTS();
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322 /*-----------------------------------------------------------*/
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324 BaseType_t xPortStartScheduler( void )
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328 #if( configASSERT_DEFINED == 1 )
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330 volatile uint32_t ulOriginalPriority;
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331 volatile uint8_t * const pucFirstUserPriorityRegister = ( volatile uint8_t * const ) ( configINTERRUPT_CONTROLLER_BASE_ADDRESS + portINTERRUPT_PRIORITY_REGISTER_OFFSET );
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332 volatile uint8_t ucMaxPriorityValue;
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334 /* Determine how many priority bits are implemented in the GIC.
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336 Save the interrupt priority value that is about to be clobbered. */
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337 ulOriginalPriority = *pucFirstUserPriorityRegister;
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339 /* Determine the number of priority bits available. First write to
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340 all possible bits. */
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341 *pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE;
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343 /* Read the value back to see how many bits stuck. */
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344 ucMaxPriorityValue = *pucFirstUserPriorityRegister;
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346 /* Shift to the least significant bits. */
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347 while( ( ucMaxPriorityValue & portBIT_0_SET ) != portBIT_0_SET )
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349 ucMaxPriorityValue >>= ( uint8_t ) 0x01;
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352 /* Sanity check configUNIQUE_INTERRUPT_PRIORITIES matches the read
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354 configASSERT( ucMaxPriorityValue == portLOWEST_INTERRUPT_PRIORITY );
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356 /* Restore the clobbered interrupt priority register to its original
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358 *pucFirstUserPriorityRegister = ulOriginalPriority;
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360 #endif /* conifgASSERT_DEFINED */
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363 /* Only continue if the CPU is not in User mode. The CPU must be in a
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364 Privileged mode for the scheduler to start. */
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365 __asm volatile ( "MRS %0, APSR" : "=r" ( ulAPSR ) :: "memory" );
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366 ulAPSR &= portAPSR_MODE_BITS_MASK;
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367 configASSERT( ulAPSR != portAPSR_USER_MODE );
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369 if( ulAPSR != portAPSR_USER_MODE )
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371 /* Only continue if the binary point value is set to its lowest possible
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372 setting. See the comments in vPortValidateInterruptPriority() below for
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373 more information. */
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374 configASSERT( ( portICCBPR_BINARY_POINT_REGISTER & portBINARY_POINT_BITS ) <= portMAX_BINARY_POINT_VALUE );
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376 if( ( portICCBPR_BINARY_POINT_REGISTER & portBINARY_POINT_BITS ) <= portMAX_BINARY_POINT_VALUE )
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378 /* Interrupts are turned off in the CPU itself to ensure tick does
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379 not execute while the scheduler is being started. Interrupts are
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380 automatically turned back on in the CPU when the first task starts
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382 portCPU_IRQ_DISABLE();
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384 /* Start the timer that generates the tick ISR. */
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385 configSETUP_TICK_INTERRUPT();
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387 /* Start the first task executing. */
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388 vPortRestoreTaskContext();
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392 /* Will only get here if vTaskStartScheduler() was called with the CPU in
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393 a non-privileged mode or the binary point register was not set to its lowest
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394 possible value. prvTaskExitError() is referenced to prevent a compiler
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395 warning about it being defined but not referenced in the case that the user
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396 defines their own exit address. */
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397 ( void ) prvTaskExitError;
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400 /*-----------------------------------------------------------*/
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402 void vPortEndScheduler( void )
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404 /* Not implemented in ports where there is nothing to return to.
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405 Artificially force an assert. */
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406 configASSERT( ulCriticalNesting == 1000UL );
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408 /*-----------------------------------------------------------*/
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410 void vPortEnterCritical( void )
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412 /* Mask interrupts up to the max syscall interrupt priority. */
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413 ulPortSetInterruptMask();
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415 /* Now interrupts are disabled ulCriticalNesting can be accessed
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416 directly. Increment ulCriticalNesting to keep a count of how many times
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417 portENTER_CRITICAL() has been called. */
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418 ulCriticalNesting++;
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420 /* This is not the interrupt safe version of the enter critical function so
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421 assert() if it is being called from an interrupt context. Only API
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422 functions that end in "FromISR" can be used in an interrupt. Only assert if
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423 the critical nesting count is 1 to protect against recursive calls if the
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424 assert function also uses a critical section. */
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425 if( ulCriticalNesting == 1 )
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427 configASSERT( ulPortInterruptNesting == 0 );
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430 /*-----------------------------------------------------------*/
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432 void vPortExitCritical( void )
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434 if( ulCriticalNesting > portNO_CRITICAL_NESTING )
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436 /* Decrement the nesting count as the critical section is being
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438 ulCriticalNesting--;
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440 /* If the nesting level has reached zero then all interrupt
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441 priorities must be re-enabled. */
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442 if( ulCriticalNesting == portNO_CRITICAL_NESTING )
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444 /* Critical nesting has reached zero so all interrupt priorities
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445 should be unmasked. */
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446 portCLEAR_INTERRUPT_MASK();
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450 /*-----------------------------------------------------------*/
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452 void FreeRTOS_Tick_Handler( void )
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454 /* Set interrupt mask before altering scheduler structures. The tick
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455 handler runs at the lowest priority, so interrupts cannot already be masked,
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456 so there is no need to save and restore the current mask value. It is
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457 necessary to turn off interrupts in the CPU itself while the ICCPMR is being
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459 portCPU_IRQ_DISABLE();
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460 portICCPMR_PRIORITY_MASK_REGISTER = ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT );
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461 __asm volatile ( "dsb \n"
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462 "isb \n" ::: "memory" );
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463 portCPU_IRQ_ENABLE();
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465 /* Increment the RTOS tick. */
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466 if( xTaskIncrementTick() != pdFALSE )
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468 ulPortYieldRequired = pdTRUE;
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471 /* Ensure all interrupt priorities are active again. */
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472 portCLEAR_INTERRUPT_MASK();
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473 configCLEAR_TICK_INTERRUPT();
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475 /*-----------------------------------------------------------*/
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477 #if( configUSE_TASK_FPU_SUPPORT != 2 )
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479 void vPortTaskUsesFPU( void )
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481 uint32_t ulInitialFPSCR = 0;
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483 /* A task is registering the fact that it needs an FPU context. Set the
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484 FPU flag (which is saved as part of the task context). */
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485 ulPortTaskHasFPUContext = pdTRUE;
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487 /* Initialise the floating point status register. */
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488 __asm volatile ( "FMXR FPSCR, %0" :: "r" (ulInitialFPSCR) : "memory" );
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491 #endif /* configUSE_TASK_FPU_SUPPORT */
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492 /*-----------------------------------------------------------*/
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494 void vPortClearInterruptMask( uint32_t ulNewMaskValue )
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496 if( ulNewMaskValue == pdFALSE )
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498 portCLEAR_INTERRUPT_MASK();
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501 /*-----------------------------------------------------------*/
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503 uint32_t ulPortSetInterruptMask( void )
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507 /* Interrupt in the CPU must be turned off while the ICCPMR is being
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509 portCPU_IRQ_DISABLE();
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510 if( portICCPMR_PRIORITY_MASK_REGISTER == ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ) )
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512 /* Interrupts were already masked. */
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517 ulReturn = pdFALSE;
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518 portICCPMR_PRIORITY_MASK_REGISTER = ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT );
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519 __asm volatile ( "dsb \n"
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520 "isb \n" ::: "memory" );
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522 portCPU_IRQ_ENABLE();
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526 /*-----------------------------------------------------------*/
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528 #if( configASSERT_DEFINED == 1 )
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530 void vPortValidateInterruptPriority( void )
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532 /* The following assertion will fail if a service routine (ISR) for
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533 an interrupt that has been assigned a priority above
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534 configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API
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535 function. ISR safe FreeRTOS API functions must *only* be called
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536 from interrupts that have been assigned a priority at or below
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537 configMAX_SYSCALL_INTERRUPT_PRIORITY.
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539 Numerically low interrupt priority numbers represent logically high
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540 interrupt priorities, therefore the priority of the interrupt must
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541 be set to a value equal to or numerically *higher* than
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542 configMAX_SYSCALL_INTERRUPT_PRIORITY.
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544 FreeRTOS maintains separate thread and ISR API functions to ensure
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545 interrupt entry is as fast and simple as possible. */
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546 configASSERT( portICCRPR_RUNNING_PRIORITY_REGISTER >= ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ) );
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548 /* Priority grouping: The interrupt controller (GIC) allows the bits
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549 that define each interrupt's priority to be split between bits that
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550 define the interrupt's pre-emption priority bits and bits that define
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551 the interrupt's sub-priority. For simplicity all bits must be defined
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552 to be pre-emption priority bits. The following assertion will fail if
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553 this is not the case (if some bits represent a sub-priority).
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555 The priority grouping is configured by the GIC's binary point register
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556 (ICCBPR). Writting 0 to ICCBPR will ensure it is set to its lowest
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557 possible value (which may be above 0). */
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558 configASSERT( ( portICCBPR_BINARY_POINT_REGISTER & portBINARY_POINT_BITS ) <= portMAX_BINARY_POINT_VALUE );
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561 #endif /* configASSERT_DEFINED */
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562 /*-----------------------------------------------------------*/
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564 void vApplicationFPUSafeIRQHandler( uint32_t ulICCIAR )
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567 configASSERT( ( volatile void * ) NULL );
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