2 FreeRTOS V9.0.0rc2 - Copyright (C) 2016 Real Time Engineers Ltd.
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5 VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
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7 This file is part of the FreeRTOS distribution.
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9 FreeRTOS is free software; you can redistribute it and/or modify it under
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10 the terms of the GNU General Public License (version 2) as published by the
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11 Free Software Foundation >>>> AND MODIFIED BY <<<< the FreeRTOS exception.
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13 ***************************************************************************
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14 >>! NOTE: The modification to the GPL is included to allow you to !<<
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15 >>! distribute a combined work that includes FreeRTOS without being !<<
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16 >>! obliged to provide the source code for proprietary components !<<
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17 >>! outside of the FreeRTOS kernel. !<<
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18 ***************************************************************************
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20 FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
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21 WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
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22 FOR A PARTICULAR PURPOSE. Full license text is available on the following
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23 link: http://www.freertos.org/a00114.html
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25 ***************************************************************************
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27 * FreeRTOS provides completely free yet professionally developed, *
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28 * robust, strictly quality controlled, supported, and cross *
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29 * platform software that is more than just the market leader, it *
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30 * is the industry's de facto standard. *
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32 * Help yourself get started quickly while simultaneously helping *
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33 * to support the FreeRTOS project by purchasing a FreeRTOS *
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34 * tutorial book, reference manual, or both: *
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35 * http://www.FreeRTOS.org/Documentation *
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37 ***************************************************************************
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39 http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading
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40 the FAQ page "My application does not run, what could be wrong?". Have you
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41 defined configASSERT()?
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43 http://www.FreeRTOS.org/support - In return for receiving this top quality
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44 embedded software for free we request you assist our global community by
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45 participating in the support forum.
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47 http://www.FreeRTOS.org/training - Investing in training allows your team to
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48 be as productive as possible as early as possible. Now you can receive
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49 FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers
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50 Ltd, and the world's leading authority on the world's leading RTOS.
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52 http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
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53 including FreeRTOS+Trace - an indispensable productivity tool, a DOS
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54 compatible FAT file system, and our tiny thread aware UDP/IP stack.
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56 http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.
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57 Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.
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59 http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High
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60 Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS
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61 licenses offer ticketed support, indemnification and commercial middleware.
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63 http://www.SafeRTOS.com - High Integrity Systems also provide a safety
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64 engineered and independently SIL3 certified version for use in safety and
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65 mission critical applications that require provable dependability.
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70 /* Standard includes. */
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73 /* Scheduler includes. */
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74 #include "FreeRTOS.h"
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77 #ifndef configINTERRUPT_CONTROLLER_BASE_ADDRESS
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78 #error configINTERRUPT_CONTROLLER_BASE_ADDRESS must be defined. See http://www.freertos.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html
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81 #ifndef configINTERRUPT_CONTROLLER_CPU_INTERFACE_OFFSET
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82 #error configINTERRUPT_CONTROLLER_CPU_INTERFACE_OFFSET must be defined. See http://www.freertos.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html
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85 #ifndef configUNIQUE_INTERRUPT_PRIORITIES
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86 #error configUNIQUE_INTERRUPT_PRIORITIES must be defined. See http://www.freertos.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html
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89 #ifndef configSETUP_TICK_INTERRUPT
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90 #error configSETUP_TICK_INTERRUPT() must be defined. See http://www.freertos.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html
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91 #endif /* configSETUP_TICK_INTERRUPT */
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93 #ifndef configMAX_API_CALL_INTERRUPT_PRIORITY
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94 #error configMAX_API_CALL_INTERRUPT_PRIORITY must be defined. See http://www.freertos.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html
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97 #if configMAX_API_CALL_INTERRUPT_PRIORITY == 0
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98 #error configMAX_API_CALL_INTERRUPT_PRIORITY must not be set to 0
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101 #if configMAX_API_CALL_INTERRUPT_PRIORITY > configUNIQUE_INTERRUPT_PRIORITIES
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102 #error configMAX_API_CALL_INTERRUPT_PRIORITY must be less than or equal to configUNIQUE_INTERRUPT_PRIORITIES as the lower the numeric priority value the higher the logical interrupt priority
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105 #if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
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106 /* Check the configuration. */
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107 #if( configMAX_PRIORITIES > 32 )
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108 #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
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110 #endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
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112 /* In case security extensions are implemented. */
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113 #if configMAX_API_CALL_INTERRUPT_PRIORITY <= ( configUNIQUE_INTERRUPT_PRIORITIES / 2 )
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114 #error configMAX_API_CALL_INTERRUPT_PRIORITY must be greater than ( configUNIQUE_INTERRUPT_PRIORITIES / 2 )
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117 /* Some vendor specific files default configCLEAR_TICK_INTERRUPT() in
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119 #ifndef configCLEAR_TICK_INTERRUPT
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120 #define configCLEAR_TICK_INTERRUPT()
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123 /* A critical section is exited when the critical section nesting count reaches
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125 #define portNO_CRITICAL_NESTING ( ( uint32_t ) 0 )
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127 /* In all GICs 255 can be written to the priority mask register to unmask all
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128 (but the lowest) interrupt priority. */
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129 #define portUNMASK_VALUE ( 0xFFUL )
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131 /* Tasks are not created with a floating point context, but can be given a
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132 floating point context after they have been created. A variable is stored as
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133 part of the tasks context that holds portNO_FLOATING_POINT_CONTEXT if the task
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134 does not have an FPU context, or any other value if the task does have an FPU
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136 #define portNO_FLOATING_POINT_CONTEXT ( ( StackType_t ) 0 )
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138 /* Constants required to setup the initial task context. */
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139 #define portINITIAL_SPSR ( ( StackType_t ) 0x1f ) /* System mode, ARM mode, IRQ enabled FIQ enabled. */
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140 #define portTHUMB_MODE_BIT ( ( StackType_t ) 0x20 )
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141 #define portINTERRUPT_ENABLE_BIT ( 0x80UL )
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142 #define portTHUMB_MODE_ADDRESS ( 0x01UL )
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144 /* Used by portASSERT_IF_INTERRUPT_PRIORITY_INVALID() when ensuring the binary
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146 #define portBINARY_POINT_BITS ( ( uint8_t ) 0x03 )
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148 /* Masks all bits in the APSR other than the mode bits. */
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149 #define portAPSR_MODE_BITS_MASK ( 0x1F )
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151 /* The value of the mode bits in the APSR when the CPU is executing in user
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153 #define portAPSR_USER_MODE ( 0x10 )
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155 /* The critical section macros only mask interrupts up to an application
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156 determined priority level. Sometimes it is necessary to turn interrupt off in
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157 the CPU itself before modifying certain hardware registers. */
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158 #define portCPU_IRQ_DISABLE() \
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159 __asm volatile ( "CPSID i" ); \
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160 __asm volatile ( "DSB" ); \
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161 __asm volatile ( "ISB" );
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163 #define portCPU_IRQ_ENABLE() \
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164 __asm volatile ( "CPSIE i" ); \
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165 __asm volatile ( "DSB" ); \
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166 __asm volatile ( "ISB" );
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169 /* Macro to unmask all interrupt priorities. */
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170 #define portCLEAR_INTERRUPT_MASK() \
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172 portCPU_IRQ_DISABLE(); \
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173 portICCPMR_PRIORITY_MASK_REGISTER = portUNMASK_VALUE; \
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174 __asm volatile ( "DSB \n" \
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176 portCPU_IRQ_ENABLE(); \
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179 #define portINTERRUPT_PRIORITY_REGISTER_OFFSET 0x400UL
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180 #define portMAX_8_BIT_VALUE ( ( uint8_t ) 0xff )
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181 #define portBIT_0_SET ( ( uint8_t ) 0x01 )
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183 /* Let the user override the pre-loading of the initial LR with the address of
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184 prvTaskExitError() in case it messes up unwinding of the stack in the
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186 #ifdef configTASK_RETURN_ADDRESS
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187 #define portTASK_RETURN_ADDRESS configTASK_RETURN_ADDRESS
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189 #define portTASK_RETURN_ADDRESS prvTaskExitError
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192 /* The space on the stack required to hold the FPU registers. This is 32 64-bit
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193 registers, plus a 32-bit status register. */
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194 #define portFPU_REGISTER_WORDS ( ( 32 * 2 ) + 1 )
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196 /*-----------------------------------------------------------*/
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199 * Starts the first task executing. This function is necessarily written in
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200 * assembly code so is implemented in portASM.s.
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202 extern void vPortRestoreTaskContext( void );
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205 * Used to catch tasks that attempt to return from their implementing function.
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207 static void prvTaskExitError( void );
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210 * If the application provides an implementation of vApplicationIRQHandler(),
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211 * then it will get called directly without saving the FPU registers on
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212 * interrupt entry, and this weak implementation of
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213 * vApplicationFPUSafeIRQHandler() is just provided to remove linkage errors -
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214 * it should never actually get called so its implementation contains a
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215 * call to configASSERT() that will always fail.
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217 * If the application provides its own implementation of
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218 * vApplicationFPUSafeIRQHandler() then the implementation of
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219 * vApplicationIRQHandler() provided in portASM.S will save the FPU registers
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220 * before calling it.
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222 * Therefore, if the application writer wants FPU registers to be saved on
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223 * interrupt entry their IRQ handler must be called
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224 * vApplicationFPUSafeIRQHandler(), and if the application writer does not want
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225 * FPU registers to be saved on interrupt entry their IRQ handler must be
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226 * called vApplicationIRQHandler().
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228 void vApplicationFPUSafeIRQHandler( uint32_t ulICCIAR ) __attribute__((weak) );
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230 /*-----------------------------------------------------------*/
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232 /* A variable is used to keep track of the critical section nesting. This
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233 variable has to be stored as part of the task context and must be initialised to
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234 a non zero value to ensure interrupts don't inadvertently become unmasked before
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235 the scheduler starts. As it is stored as part of the task context it will
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236 automatically be set to 0 when the first task is started. */
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237 volatile uint32_t ulCriticalNesting = 9999UL;
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239 /* Saved as part of the task context. If ulPortTaskHasFPUContext is non-zero then
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240 a floating point context must be saved and restored for the task. */
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241 volatile uint32_t ulPortTaskHasFPUContext = pdFALSE;
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243 /* Set to 1 to pend a context switch from an ISR. */
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244 volatile uint32_t ulPortYieldRequired = pdFALSE;
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246 /* Counts the interrupt nesting depth. A context switch is only performed if
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247 if the nesting depth is 0. */
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248 volatile uint32_t ulPortInterruptNesting = 0UL;
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250 /* Used in the asm file. */
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251 __attribute__(( used )) const uint32_t ulICCIAR = portICCIAR_INTERRUPT_ACKNOWLEDGE_REGISTER_ADDRESS;
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252 __attribute__(( used )) const uint32_t ulICCEOIR = portICCEOIR_END_OF_INTERRUPT_REGISTER_ADDRESS;
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253 __attribute__(( used )) const uint32_t ulICCPMR = portICCPMR_PRIORITY_MASK_REGISTER_ADDRESS;
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254 __attribute__(( used )) const uint32_t ulMaxAPIPriorityMask = ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT );
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256 /*-----------------------------------------------------------*/
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259 * See header file for description.
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261 StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
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263 /* Setup the initial stack of the task. The stack is set exactly as
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264 expected by the portRESTORE_CONTEXT() macro.
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266 The fist real value on the stack is the status register, which is set for
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267 system mode, with interrupts enabled. A few NULLs are added first to ensure
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268 GDB does not try decoding a non-existent return address. */
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269 *pxTopOfStack = ( StackType_t ) NULL;
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271 *pxTopOfStack = ( StackType_t ) NULL;
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273 *pxTopOfStack = ( StackType_t ) NULL;
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275 *pxTopOfStack = ( StackType_t ) portINITIAL_SPSR;
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277 if( ( ( uint32_t ) pxCode & portTHUMB_MODE_ADDRESS ) != 0x00UL )
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279 /* The task will start in THUMB mode. */
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280 *pxTopOfStack |= portTHUMB_MODE_BIT;
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285 /* Next the return address, which in this case is the start of the task. */
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286 *pxTopOfStack = ( StackType_t ) pxCode;
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289 /* Next all the registers other than the stack pointer. */
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290 *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* R14 */
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292 *pxTopOfStack = ( StackType_t ) 0x12121212; /* R12 */
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294 *pxTopOfStack = ( StackType_t ) 0x11111111; /* R11 */
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296 *pxTopOfStack = ( StackType_t ) 0x10101010; /* R10 */
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298 *pxTopOfStack = ( StackType_t ) 0x09090909; /* R9 */
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300 *pxTopOfStack = ( StackType_t ) 0x08080808; /* R8 */
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302 *pxTopOfStack = ( StackType_t ) 0x07070707; /* R7 */
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304 *pxTopOfStack = ( StackType_t ) 0x06060606; /* R6 */
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306 *pxTopOfStack = ( StackType_t ) 0x05050505; /* R5 */
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308 *pxTopOfStack = ( StackType_t ) 0x04040404; /* R4 */
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310 *pxTopOfStack = ( StackType_t ) 0x03030303; /* R3 */
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312 *pxTopOfStack = ( StackType_t ) 0x02020202; /* R2 */
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314 *pxTopOfStack = ( StackType_t ) 0x01010101; /* R1 */
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316 *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
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319 /* The task will start with a critical nesting count of 0 as interrupts are
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321 *pxTopOfStack = portNO_CRITICAL_NESTING;
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323 #if( configUSE_TASK_FPU_SUPPORT == 1 )
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325 /* The task will start without a floating point context. A task that
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326 uses the floating point hardware must call vPortTaskUsesFPU() before
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327 executing any floating point instructions. */
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329 *pxTopOfStack = portNO_FLOATING_POINT_CONTEXT;
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331 #elif( configUSE_TASK_FPU_SUPPORT == 2 )
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333 /* The task will start with a floating point context. Leave enough
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334 space for the registers - and ensure they are initialised to 0. */
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335 pxTopOfStack -= portFPU_REGISTER_WORDS;
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336 memset( pxTopOfStack, 0x00, portFPU_REGISTER_WORDS * sizeof( StackType_t ) );
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339 *pxTopOfStack = pdTRUE;
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340 ulPortTaskHasFPUContext = pdTRUE;
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344 #error Invalid configUSE_TASK_FPU_SUPPORT setting - configUSE_TASK_FPU_SUPPORT must be set to 1, 2, or left undefined.
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348 return pxTopOfStack;
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350 /*-----------------------------------------------------------*/
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352 static void prvTaskExitError( void )
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354 /* A function that implements a task must not exit or attempt to return to
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355 its caller as there is nothing to return to. If a task wants to exit it
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356 should instead call vTaskDelete( NULL ).
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358 Artificially force an assert() to be triggered if configASSERT() is
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359 defined, then stop here so application writers can catch the error. */
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360 configASSERT( ulPortInterruptNesting == ~0UL );
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361 portDISABLE_INTERRUPTS();
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364 /*-----------------------------------------------------------*/
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366 BaseType_t xPortStartScheduler( void )
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370 #if( configASSERT_DEFINED == 1 )
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372 volatile uint32_t ulOriginalPriority;
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373 volatile uint8_t * const pucFirstUserPriorityRegister = ( volatile uint8_t * const ) ( configINTERRUPT_CONTROLLER_BASE_ADDRESS + portINTERRUPT_PRIORITY_REGISTER_OFFSET );
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374 volatile uint8_t ucMaxPriorityValue;
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376 /* Determine how many priority bits are implemented in the GIC.
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378 Save the interrupt priority value that is about to be clobbered. */
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379 ulOriginalPriority = *pucFirstUserPriorityRegister;
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381 /* Determine the number of priority bits available. First write to
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382 all possible bits. */
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383 *pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE;
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385 /* Read the value back to see how many bits stuck. */
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386 ucMaxPriorityValue = *pucFirstUserPriorityRegister;
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388 /* Shift to the least significant bits. */
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389 while( ( ucMaxPriorityValue & portBIT_0_SET ) != portBIT_0_SET )
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391 ucMaxPriorityValue >>= ( uint8_t ) 0x01;
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394 /* Sanity check configUNIQUE_INTERRUPT_PRIORITIES matches the read
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396 configASSERT( ucMaxPriorityValue == portLOWEST_INTERRUPT_PRIORITY );
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398 /* Restore the clobbered interrupt priority register to its original
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400 *pucFirstUserPriorityRegister = ulOriginalPriority;
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402 #endif /* conifgASSERT_DEFINED */
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405 /* Only continue if the CPU is not in User mode. The CPU must be in a
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406 Privileged mode for the scheduler to start. */
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407 __asm volatile ( "MRS %0, APSR" : "=r" ( ulAPSR ) );
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408 ulAPSR &= portAPSR_MODE_BITS_MASK;
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409 configASSERT( ulAPSR != portAPSR_USER_MODE );
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411 if( ulAPSR != portAPSR_USER_MODE )
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413 /* Only continue if the binary point value is set to its lowest possible
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414 setting. See the comments in vPortValidateInterruptPriority() below for
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415 more information. */
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416 configASSERT( ( portICCBPR_BINARY_POINT_REGISTER & portBINARY_POINT_BITS ) <= portMAX_BINARY_POINT_VALUE );
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418 if( ( portICCBPR_BINARY_POINT_REGISTER & portBINARY_POINT_BITS ) <= portMAX_BINARY_POINT_VALUE )
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420 /* Interrupts are turned off in the CPU itself to ensure tick does
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421 not execute while the scheduler is being started. Interrupts are
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422 automatically turned back on in the CPU when the first task starts
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424 portCPU_IRQ_DISABLE();
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426 /* Start the timer that generates the tick ISR. */
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427 configSETUP_TICK_INTERRUPT();
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429 /* Start the first task executing. */
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430 vPortRestoreTaskContext();
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434 /* Will only get here if vTaskStartScheduler() was called with the CPU in
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435 a non-privileged mode or the binary point register was not set to its lowest
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436 possible value. prvTaskExitError() is referenced to prevent a compiler
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437 warning about it being defined but not referenced in the case that the user
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438 defines their own exit address. */
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439 ( void ) prvTaskExitError;
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442 /*-----------------------------------------------------------*/
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444 void vPortEndScheduler( void )
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446 /* Not implemented in ports where there is nothing to return to.
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447 Artificially force an assert. */
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448 configASSERT( ulCriticalNesting == 1000UL );
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450 /*-----------------------------------------------------------*/
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452 void vPortEnterCritical( void )
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454 /* Mask interrupts up to the max syscall interrupt priority. */
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455 ulPortSetInterruptMask();
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457 /* Now interrupts are disabled ulCriticalNesting can be accessed
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458 directly. Increment ulCriticalNesting to keep a count of how many times
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459 portENTER_CRITICAL() has been called. */
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460 ulCriticalNesting++;
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462 /* This is not the interrupt safe version of the enter critical function so
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463 assert() if it is being called from an interrupt context. Only API
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464 functions that end in "FromISR" can be used in an interrupt. Only assert if
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465 the critical nesting count is 1 to protect against recursive calls if the
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466 assert function also uses a critical section. */
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467 if( ulCriticalNesting == 1 )
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469 configASSERT( ulPortInterruptNesting == 0 );
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472 /*-----------------------------------------------------------*/
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474 void vPortExitCritical( void )
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476 if( ulCriticalNesting > portNO_CRITICAL_NESTING )
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478 /* Decrement the nesting count as the critical section is being
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480 ulCriticalNesting--;
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482 /* If the nesting level has reached zero then all interrupt
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483 priorities must be re-enabled. */
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484 if( ulCriticalNesting == portNO_CRITICAL_NESTING )
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486 /* Critical nesting has reached zero so all interrupt priorities
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487 should be unmasked. */
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488 portCLEAR_INTERRUPT_MASK();
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492 /*-----------------------------------------------------------*/
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494 void FreeRTOS_Tick_Handler( void )
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496 /* Set interrupt mask before altering scheduler structures. The tick
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497 handler runs at the lowest priority, so interrupts cannot already be masked,
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498 so there is no need to save and restore the current mask value. It is
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499 necessary to turn off interrupts in the CPU itself while the ICCPMR is being
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501 portCPU_IRQ_DISABLE();
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502 portICCPMR_PRIORITY_MASK_REGISTER = ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT );
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503 __asm volatile ( "dsb \n"
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505 portCPU_IRQ_ENABLE();
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507 /* Increment the RTOS tick. */
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508 if( xTaskIncrementTick() != pdFALSE )
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510 ulPortYieldRequired = pdTRUE;
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513 /* Ensure all interrupt priorities are active again. */
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514 portCLEAR_INTERRUPT_MASK();
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515 configCLEAR_TICK_INTERRUPT();
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517 /*-----------------------------------------------------------*/
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519 #if( configUSE_TASK_FPU_SUPPORT != 2 )
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521 void vPortTaskUsesFPU( void )
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523 uint32_t ulInitialFPSCR = 0;
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525 /* A task is registering the fact that it needs an FPU context. Set the
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526 FPU flag (which is saved as part of the task context). */
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527 ulPortTaskHasFPUContext = pdTRUE;
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529 /* Initialise the floating point status register. */
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530 __asm volatile ( "FMXR FPSCR, %0" :: "r" (ulInitialFPSCR) );
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533 #endif /* configUSE_TASK_FPU_SUPPORT */
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534 /*-----------------------------------------------------------*/
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536 void vPortClearInterruptMask( uint32_t ulNewMaskValue )
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538 if( ulNewMaskValue == pdFALSE )
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540 portCLEAR_INTERRUPT_MASK();
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543 /*-----------------------------------------------------------*/
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545 uint32_t ulPortSetInterruptMask( void )
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549 /* Interrupt in the CPU must be turned off while the ICCPMR is being
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551 portCPU_IRQ_DISABLE();
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552 if( portICCPMR_PRIORITY_MASK_REGISTER == ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ) )
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554 /* Interrupts were already masked. */
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559 ulReturn = pdFALSE;
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560 portICCPMR_PRIORITY_MASK_REGISTER = ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT );
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561 __asm volatile ( "dsb \n"
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564 portCPU_IRQ_ENABLE();
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568 /*-----------------------------------------------------------*/
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570 #if( configASSERT_DEFINED == 1 )
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572 void vPortValidateInterruptPriority( void )
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574 /* The following assertion will fail if a service routine (ISR) for
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575 an interrupt that has been assigned a priority above
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576 configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API
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577 function. ISR safe FreeRTOS API functions must *only* be called
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578 from interrupts that have been assigned a priority at or below
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579 configMAX_SYSCALL_INTERRUPT_PRIORITY.
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581 Numerically low interrupt priority numbers represent logically high
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582 interrupt priorities, therefore the priority of the interrupt must
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583 be set to a value equal to or numerically *higher* than
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584 configMAX_SYSCALL_INTERRUPT_PRIORITY.
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586 FreeRTOS maintains separate thread and ISR API functions to ensure
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587 interrupt entry is as fast and simple as possible. */
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588 configASSERT( portICCRPR_RUNNING_PRIORITY_REGISTER >= ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ) );
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590 /* Priority grouping: The interrupt controller (GIC) allows the bits
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591 that define each interrupt's priority to be split between bits that
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592 define the interrupt's pre-emption priority bits and bits that define
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593 the interrupt's sub-priority. For simplicity all bits must be defined
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594 to be pre-emption priority bits. The following assertion will fail if
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595 this is not the case (if some bits represent a sub-priority).
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597 The priority grouping is configured by the GIC's binary point register
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598 (ICCBPR). Writting 0 to ICCBPR will ensure it is set to its lowest
\r
599 possible value (which may be above 0). */
\r
600 configASSERT( ( portICCBPR_BINARY_POINT_REGISTER & portBINARY_POINT_BITS ) <= portMAX_BINARY_POINT_VALUE );
\r
603 #endif /* configASSERT_DEFINED */
\r
604 /*-----------------------------------------------------------*/
\r
606 void vApplicationFPUSafeIRQHandler( uint32_t ulICCIAR )
\r
609 configASSERT( ( volatile void * ) NULL );
\r