2 FreeRTOS V8.0.1 - Copyright (C) 2014 Real Time Engineers Ltd.
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5 VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
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7 ***************************************************************************
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9 * FreeRTOS provides completely free yet professionally developed, *
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10 * robust, strictly quality controlled, supported, and cross *
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11 * platform software that has become a de facto standard. *
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13 * Help yourself get started quickly and support the FreeRTOS *
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14 * project by purchasing a FreeRTOS tutorial book, reference *
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15 * manual, or both from: http://www.FreeRTOS.org/Documentation *
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19 ***************************************************************************
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21 This file is part of the FreeRTOS distribution.
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23 FreeRTOS is free software; you can redistribute it and/or modify it under
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24 the terms of the GNU General Public License (version 2) as published by the
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25 Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.
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27 >>! NOTE: The modification to the GPL is included to allow you to !<<
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28 >>! distribute a combined work that includes FreeRTOS without being !<<
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29 >>! obliged to provide the source code for proprietary components !<<
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30 >>! outside of the FreeRTOS kernel. !<<
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32 FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
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33 WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
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34 FOR A PARTICULAR PURPOSE. Full license text is available from the following
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35 link: http://www.freertos.org/a00114.html
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39 ***************************************************************************
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41 * Having a problem? Start by reading the FAQ "My application does *
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42 * not run, what could be wrong?" *
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44 * http://www.FreeRTOS.org/FAQHelp.html *
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46 ***************************************************************************
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48 http://www.FreeRTOS.org - Documentation, books, training, latest versions,
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49 license and Real Time Engineers Ltd. contact details.
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51 http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
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52 including FreeRTOS+Trace - an indispensable productivity tool, a DOS
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53 compatible FAT file system, and our tiny thread aware UDP/IP stack.
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55 http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High
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56 Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS
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57 licenses offer ticketed support, indemnification and middleware.
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59 http://www.SafeRTOS.com - High Integrity Systems also provide a safety
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60 engineered and independently SIL3 certified version for use in safety and
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61 mission critical applications that require provable dependability.
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66 /* Standard includes. */
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69 /* Scheduler includes. */
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70 #include "FreeRTOS.h"
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73 #ifndef configINTERRUPT_CONTROLLER_BASE_ADDRESS
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74 #error configINTERRUPT_CONTROLLER_BASE_ADDRESS must be defined. See http://www.freertos.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html
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77 #ifndef configINTERRUPT_CONTROLLER_CPU_INTERFACE_OFFSET
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78 #error configINTERRUPT_CONTROLLER_CPU_INTERFACE_OFFSET must be defined. See http://www.freertos.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html
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81 #ifndef configUNIQUE_INTERRUPT_PRIORITIES
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82 #error configUNIQUE_INTERRUPT_PRIORITIES must be defined. See http://www.freertos.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html
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85 #ifndef configSETUP_TICK_INTERRUPT
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86 #error configSETUP_TICK_INTERRUPT() must be defined. See http://www.freertos.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html
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87 #endif /* configSETUP_TICK_INTERRUPT */
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89 #ifndef configMAX_API_CALL_INTERRUPT_PRIORITY
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90 #error configMAX_API_CALL_INTERRUPT_PRIORITY must be defined. See http://www.freertos.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html
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93 #if configMAX_API_CALL_INTERRUPT_PRIORITY == 0
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94 #error configMAX_API_CALL_INTERRUPT_PRIORITY must not be set to 0
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97 #if configMAX_API_CALL_INTERRUPT_PRIORITY > configUNIQUE_INTERRUPT_PRIORITIES
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98 #error configMAX_API_CALL_INTERRUPT_PRIORITY must be less than or equal to configUNIQUE_INTERRUPT_PRIORITIES as the lower the numeric priority value the higher the logical interrupt priority
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101 #if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
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102 /* Check the configuration. */
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103 #if( configMAX_PRIORITIES > 32 )
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104 #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
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106 #endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
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108 /* In case security extensions are implemented. */
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109 #if configMAX_API_CALL_INTERRUPT_PRIORITY <= ( configUNIQUE_INTERRUPT_PRIORITIES / 2 )
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110 #error configMAX_API_CALL_INTERRUPT_PRIORITY must be greater than ( configUNIQUE_INTERRUPT_PRIORITIES / 2 )
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113 /* Some vendor specific files default configCLEAR_TICK_INTERRUPT() in
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115 #ifndef configCLEAR_TICK_INTERRUPT
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116 #define configCLEAR_TICK_INTERRUPT()
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119 /* A critical section is exited when the critical section nesting count reaches
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121 #define portNO_CRITICAL_NESTING ( ( uint32_t ) 0 )
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123 /* In all GICs 255 can be written to the priority mask register to unmask all
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124 (but the lowest) interrupt priority. */
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125 #define portUNMASK_VALUE ( 0xFFUL )
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127 /* Tasks are not created with a floating point context, but can be given a
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128 floating point context after they have been created. A variable is stored as
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129 part of the tasks context that holds portNO_FLOATING_POINT_CONTEXT if the task
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130 does not have an FPU context, or any other value if the task does have an FPU
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132 #define portNO_FLOATING_POINT_CONTEXT ( ( StackType_t ) 0 )
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134 /* Constants required to setup the initial task context. */
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135 #define portINITIAL_SPSR ( ( StackType_t ) 0x1f ) /* System mode, ARM mode, IRQ enabled FIQ enabled. */
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136 #define portTHUMB_MODE_BIT ( ( StackType_t ) 0x20 )
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137 #define portINTERRUPT_ENABLE_BIT ( 0x80UL )
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138 #define portTHUMB_MODE_ADDRESS ( 0x01UL )
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140 /* Used by portASSERT_IF_INTERRUPT_PRIORITY_INVALID() when ensuring the binary
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142 #define portBINARY_POINT_BITS ( ( uint8_t ) 0x03 )
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144 /* Masks all bits in the APSR other than the mode bits. */
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145 #define portAPSR_MODE_BITS_MASK ( 0x1F )
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147 /* The value of the mode bits in the APSR when the CPU is executing in user
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149 #define portAPSR_USER_MODE ( 0x10 )
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151 /* The critical section macros only mask interrupts up to an application
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152 determined priority level. Sometimes it is necessary to turn interrupt off in
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153 the CPU itself before modifying certain hardware registers. */
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154 #define portCPU_IRQ_DISABLE() \
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155 __asm volatile ( "CPSID i" ); \
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156 __asm volatile ( "DSB" ); \
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157 __asm volatile ( "ISB" );
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159 #define portCPU_IRQ_ENABLE() \
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160 __asm volatile ( "CPSIE i" ); \
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161 __asm volatile ( "DSB" ); \
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162 __asm volatile ( "ISB" );
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165 /* Macro to unmask all interrupt priorities. */
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166 #define portCLEAR_INTERRUPT_MASK() \
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168 portCPU_IRQ_DISABLE(); \
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169 portICCPMR_PRIORITY_MASK_REGISTER = portUNMASK_VALUE; \
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172 portCPU_IRQ_ENABLE(); \
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175 #define portINTERRUPT_PRIORITY_REGISTER_OFFSET 0x400UL
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176 #define portMAX_8_BIT_VALUE ( ( uint8_t ) 0xff )
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177 #define portBIT_0_SET ( ( uint8_t ) 0x01 )
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179 /*-----------------------------------------------------------*/
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182 * Starts the first task executing. This function is necessarily written in
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183 * assembly code so is implemented in portASM.s.
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185 extern void vPortRestoreTaskContext( void );
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187 /*-----------------------------------------------------------*/
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189 /* A variable is used to keep track of the critical section nesting. This
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190 variable has to be stored as part of the task context and must be initialised to
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191 a non zero value to ensure interrupts don't inadvertently become unmasked before
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192 the scheduler starts. As it is stored as part of the task context it will
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193 automatically be set to 0 when the first task is started. */
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194 volatile uint32_t ulCriticalNesting = 9999UL;
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196 /* Saved as part of the task context. If ulPortTaskHasFPUContext is non-zero then
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197 a floating point context must be saved and restored for the task. */
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198 uint32_t ulPortTaskHasFPUContext = pdFALSE;
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200 /* Set to 1 to pend a context switch from an ISR. */
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201 uint32_t ulPortYieldRequired = pdFALSE;
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203 /* Counts the interrupt nesting depth. A context switch is only performed if
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204 if the nesting depth is 0. */
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205 uint32_t ulPortInterruptNesting = 0UL;
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207 __attribute__(( used )) const uint32_t ulICCIAR = portICCIAR_INTERRUPT_ACKNOWLEDGE_REGISTER_ADDRESS;
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208 __attribute__(( used )) const uint32_t ulICCEOIR = portICCEOIR_END_OF_INTERRUPT_REGISTER_ADDRESS;
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209 __attribute__(( used )) const uint32_t ulICCPMR = portICCPMR_PRIORITY_MASK_REGISTER_ADDRESS;
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210 __attribute__(( used )) const uint32_t ulMaxAPIPriorityMask = ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT );
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212 /*-----------------------------------------------------------*/
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215 * See header file for description.
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217 StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
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219 /* Setup the initial stack of the task. The stack is set exactly as
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220 expected by the portRESTORE_CONTEXT() macro.
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222 The fist real value on the stack is the status register, which is set for
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223 system mode, with interrupts enabled. A few NULLs are added first to ensure
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224 GDB does not try decoding a non-existent return address. */
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225 *pxTopOfStack = ( StackType_t ) NULL;
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227 *pxTopOfStack = ( StackType_t ) NULL;
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229 *pxTopOfStack = ( StackType_t ) NULL;
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231 *pxTopOfStack = ( StackType_t ) portINITIAL_SPSR;
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233 if( ( ( uint32_t ) pxCode & portTHUMB_MODE_ADDRESS ) != 0x00UL )
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235 /* The task will start in THUMB mode. */
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236 *pxTopOfStack |= portTHUMB_MODE_BIT;
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241 /* Next the return address, which in this case is the start of the task. */
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242 *pxTopOfStack = ( StackType_t ) pxCode;
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245 /* Next all the registers other than the stack pointer. */
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246 *pxTopOfStack = ( StackType_t ) 0x00000000; /* R14 */
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248 *pxTopOfStack = ( StackType_t ) 0x12121212; /* R12 */
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250 *pxTopOfStack = ( StackType_t ) 0x11111111; /* R11 */
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252 *pxTopOfStack = ( StackType_t ) 0x10101010; /* R10 */
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254 *pxTopOfStack = ( StackType_t ) 0x09090909; /* R9 */
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256 *pxTopOfStack = ( StackType_t ) 0x08080808; /* R8 */
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258 *pxTopOfStack = ( StackType_t ) 0x07070707; /* R7 */
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260 *pxTopOfStack = ( StackType_t ) 0x06060606; /* R6 */
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262 *pxTopOfStack = ( StackType_t ) 0x05050505; /* R5 */
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264 *pxTopOfStack = ( StackType_t ) 0x04040404; /* R4 */
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266 *pxTopOfStack = ( StackType_t ) 0x03030303; /* R3 */
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268 *pxTopOfStack = ( StackType_t ) 0x02020202; /* R2 */
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270 *pxTopOfStack = ( StackType_t ) 0x01010101; /* R1 */
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272 *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
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275 /* The task will start with a critical nesting count of 0 as interrupts are
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277 *pxTopOfStack = portNO_CRITICAL_NESTING;
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280 /* The task will start without a floating point context. A task that uses
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281 the floating point hardware must call vPortTaskUsesFPU() before executing
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282 any floating point instructions. */
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283 *pxTopOfStack = portNO_FLOATING_POINT_CONTEXT;
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285 return pxTopOfStack;
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287 /*-----------------------------------------------------------*/
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289 BaseType_t xPortStartScheduler( void )
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293 #if( configASSERT_DEFINED == 1 )
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295 volatile uint32_t ulOriginalPriority;
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296 volatile uint8_t * const pucFirstUserPriorityRegister = ( volatile uint8_t * const ) ( configINTERRUPT_CONTROLLER_BASE_ADDRESS + portINTERRUPT_PRIORITY_REGISTER_OFFSET );
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297 volatile uint8_t ucMaxPriorityValue;
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299 /* Determine how many priority bits are implemented in the GIC.
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301 Save the interrupt priority value that is about to be clobbered. */
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302 ulOriginalPriority = *pucFirstUserPriorityRegister;
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304 /* Determine the number of priority bits available. First write to
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305 all possible bits. */
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306 *pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE;
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308 /* Read the value back to see how many bits stuck. */
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309 ucMaxPriorityValue = *pucFirstUserPriorityRegister;
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311 /* Shift to the least significant bits. */
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312 while( ( ucMaxPriorityValue & portBIT_0_SET ) != portBIT_0_SET )
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314 ucMaxPriorityValue >>= ( uint8_t ) 0x01;
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317 /* Sanity check configUNIQUE_INTERRUPT_PRIORITIES matches the read
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319 configASSERT( ucMaxPriorityValue == portLOWEST_INTERRUPT_PRIORITY );
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321 /* Restore the clobbered interrupt priority register to its original
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323 *pucFirstUserPriorityRegister = ulOriginalPriority;
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325 #endif /* conifgASSERT_DEFINED */
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328 /* Only continue if the CPU is not in User mode. The CPU must be in a
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329 Privileged mode for the scheduler to start. */
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330 __asm volatile ( "MRS %0, APSR" : "=r" ( ulAPSR ) );
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331 ulAPSR &= portAPSR_MODE_BITS_MASK;
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332 configASSERT( ulAPSR != portAPSR_USER_MODE );
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334 if( ulAPSR != portAPSR_USER_MODE )
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336 /* Only continue if the binary point value is set to its lowest possible
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337 setting. See the comments in vPortValidateInterruptPriority() below for
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338 more information. */
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339 configASSERT( ( portICCBPR_BINARY_POINT_REGISTER & portBINARY_POINT_BITS ) <= portMAX_BINARY_POINT_VALUE );
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341 if( ( portICCBPR_BINARY_POINT_REGISTER & portBINARY_POINT_BITS ) <= portMAX_BINARY_POINT_VALUE )
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343 /* Interrupts are turned off in the CPU itself to ensure tick does
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344 not execute while the scheduler is being started. Interrupts are
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345 automatically turned back on in the CPU when the first task starts
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347 portCPU_IRQ_DISABLE();
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349 /* Start the timer that generates the tick ISR. */
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350 configSETUP_TICK_INTERRUPT();
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352 /* Start the first task executing. */
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353 vPortRestoreTaskContext();
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357 /* Will only get here if xTaskStartScheduler() was called with the CPU in
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358 a non-privileged mode or the binary point register was not set to its lowest
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362 /*-----------------------------------------------------------*/
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364 void vPortEndScheduler( void )
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366 /* Not implemented in ports where there is nothing to return to.
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367 Artificially force an assert. */
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368 configASSERT( ulCriticalNesting == 1000UL );
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370 /*-----------------------------------------------------------*/
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372 void vPortEnterCritical( void )
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374 /* Mask interrupts up to the max syscall interrupt priority. */
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375 ulPortSetInterruptMask();
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377 /* Now interrupts are disabled ulCriticalNesting can be accessed
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378 directly. Increment ulCriticalNesting to keep a count of how many times
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379 portENTER_CRITICAL() has been called. */
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380 ulCriticalNesting++;
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382 /*-----------------------------------------------------------*/
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384 void vPortExitCritical( void )
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386 if( ulCriticalNesting > portNO_CRITICAL_NESTING )
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388 /* Decrement the nesting count as the critical section is being
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390 ulCriticalNesting--;
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392 /* If the nesting level has reached zero then all interrupt
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393 priorities must be re-enabled. */
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394 if( ulCriticalNesting == portNO_CRITICAL_NESTING )
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396 /* Critical nesting has reached zero so all interrupt priorities
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397 should be unmasked. */
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398 portCLEAR_INTERRUPT_MASK();
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402 /*-----------------------------------------------------------*/
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404 void FreeRTOS_Tick_Handler( void )
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406 /* Set interrupt mask before altering scheduler structures. The tick
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407 handler runs at the lowest priority, so interrupts cannot already be masked,
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408 so there is no need to save and restore the current mask value. It is
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409 necessary to turn off interrupts in the CPU itself while the ICCPMR is being
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411 portCPU_IRQ_DISABLE();
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412 portICCPMR_PRIORITY_MASK_REGISTER = ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT );
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415 portCPU_IRQ_ENABLE();
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417 /* Increment the RTOS tick. */
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418 if( xTaskIncrementTick() != pdFALSE )
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420 ulPortYieldRequired = pdTRUE;
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423 /* Ensure all interrupt priorities are active again. */
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424 portCLEAR_INTERRUPT_MASK();
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425 configCLEAR_TICK_INTERRUPT();
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427 /*-----------------------------------------------------------*/
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429 void vPortTaskUsesFPU( void )
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431 uint32_t ulInitialFPSCR = 0;
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433 /* A task is registering the fact that it needs an FPU context. Set the
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434 FPU flag (which is saved as part of the task context). */
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435 ulPortTaskHasFPUContext = pdTRUE;
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437 /* Initialise the floating point status register. */
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438 __asm( "FMXR FPSCR, %0" :: "r" (ulInitialFPSCR) );
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440 /*-----------------------------------------------------------*/
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442 void vPortClearInterruptMask( uint32_t ulNewMaskValue )
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444 if( ulNewMaskValue == pdFALSE )
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446 portCLEAR_INTERRUPT_MASK();
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449 /*-----------------------------------------------------------*/
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451 uint32_t ulPortSetInterruptMask( void )
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455 /* Interrupt in the CPU must be turned off while the ICCPMR is being
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457 portCPU_IRQ_DISABLE();
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458 if( portICCPMR_PRIORITY_MASK_REGISTER == ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ) )
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460 /* Interrupts were already masked. */
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465 ulReturn = pdFALSE;
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466 portICCPMR_PRIORITY_MASK_REGISTER = ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT );
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470 portCPU_IRQ_ENABLE();
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474 /*-----------------------------------------------------------*/
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476 #if( configASSERT_DEFINED == 1 )
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478 void vPortValidateInterruptPriority( void )
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480 /* The following assertion will fail if a service routine (ISR) for
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481 an interrupt that has been assigned a priority above
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482 configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API
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483 function. ISR safe FreeRTOS API functions must *only* be called
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484 from interrupts that have been assigned a priority at or below
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485 configMAX_SYSCALL_INTERRUPT_PRIORITY.
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487 Numerically low interrupt priority numbers represent logically high
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488 interrupt priorities, therefore the priority of the interrupt must
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489 be set to a value equal to or numerically *higher* than
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490 configMAX_SYSCALL_INTERRUPT_PRIORITY.
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492 FreeRTOS maintains separate thread and ISR API functions to ensure
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493 interrupt entry is as fast and simple as possible.
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495 The following links provide detailed information:
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496 http://www.freertos.org/RTOS-Cortex-M3-M4.html
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497 http://www.freertos.org/FAQHelp.html */
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498 configASSERT( portICCRPR_RUNNING_PRIORITY_REGISTER >= ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ) );
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500 /* Priority grouping: The interrupt controller (GIC) allows the bits
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501 that define each interrupt's priority to be split between bits that
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502 define the interrupt's pre-emption priority bits and bits that define
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503 the interrupt's sub-priority. For simplicity all bits must be defined
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504 to be pre-emption priority bits. The following assertion will fail if
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505 this is not the case (if some bits represent a sub-priority).
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507 The priority grouping is configured by the GIC's binary point register
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508 (ICCBPR). Writting 0 to ICCBPR will ensure it is set to its lowest
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509 possible value (which may be above 0). */
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510 configASSERT( ( portICCBPR_BINARY_POINT_REGISTER & portBINARY_POINT_BITS ) <= portMAX_BINARY_POINT_VALUE );
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513 #endif /* configASSERT_DEFINED */
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514 /*-----------------------------------------------------------*/
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