git.sur5r.net Git - freertos/blob - FreeRTOS/Source/portable/GCC/ARM_CM3/port.c

   1 /*\r
   2     FreeRTOS V7.2.0 - Copyright (C) 2012 Real Time Engineers Ltd.\r
   3 \r
   4 \r
   5     ***************************************************************************\r
   6      *                                                                       *\r
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  22     ***************************************************************************\r
  23 \r
  24 \r
  25     This file is part of the FreeRTOS distribution.\r
  26 \r
  27     FreeRTOS is free software; you can redistribute it and/or modify it under\r
  28     the terms of the GNU General Public License (version 2) as published by the\r
  29     Free Software Foundation AND MODIFIED BY the FreeRTOS exception.\r
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  33     kernel.  FreeRTOS is distributed in the hope that it will be useful, but\r
  34     WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
  35     or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for\r
  36     more details. You should have received a copy of the GNU General Public\r
  37     License and the FreeRTOS license exception along with FreeRTOS; if not it\r
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  39     by writing to Richard Barry, contact details for whom are available on the\r
  40     FreeRTOS WEB site.\r
  41 \r
  42     1 tab == 4 spaces!\r
  43 \r
  44     ***************************************************************************\r
  45      *                                                                       *\r
  46      *    Having a problem?  Start by reading the FAQ "My application does   *\r
  47      *    not run, what could be wrong?                                      *\r
  48      *                                                                       *\r
  49      *    http://www.FreeRTOS.org/FAQHelp.html                               *\r
  50      *                                                                       *\r
  51     ***************************************************************************\r
  52 \r
  53 \r
  54     http://www.FreeRTOS.org - Documentation, training, latest information,\r
  55     license and contact details.\r
  56 \r
  57     http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
  58     including FreeRTOS+Trace - an indispensable productivity tool.\r
  59 \r
  60     Real Time Engineers ltd license FreeRTOS to High Integrity Systems, who sell\r
  61     the code with commercial support, indemnification, and middleware, under\r
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  64     the SafeRTOS brand: http://www.SafeRTOS.com.\r
  65 */\r
  66 \r
  67 /*-----------------------------------------------------------\r
  68  * Implementation of functions defined in portable.h for the ARM CM3 port.\r
  69  *----------------------------------------------------------*/\r
  70 \r
  71 /* Scheduler includes. */\r
  72 #include "FreeRTOS.h"\r
  73 #include "task.h"\r
  74 \r
  75 /* For backward compatibility, ensure configKERNEL_INTERRUPT_PRIORITY is\r
  76 defined.  The value should also ensure backward compatibility.\r
  77 FreeRTOS.org versions prior to V4.4.0 did not include this definition. */\r
  78 #ifndef configKERNEL_INTERRUPT_PRIORITY\r
  79         #define configKERNEL_INTERRUPT_PRIORITY 255\r
  80 #endif\r
  81 \r
  82 #ifndef configSYSTICK_CLOCK_HZ\r
  83         #define configSYSTICK_CLOCK_HZ configCPU_CLOCK_HZ\r
  84         #if configUSE_TICKLESS_IDLE == 1\r
  85                 static const unsigned long ulStoppedTimerCompensation = 45UL;\r
  86         #endif\r
  87 #else /* configSYSTICK_CLOCK_HZ */\r
  88         #if configUSE_TICKLESS_IDLE == 1\r
  89                 /* Assumes the SysTick clock is slower than the CPU clock. */\r
  90                 static const unsigned long ulStoppedTimerCompensation = 45UL / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ );\r
  91         #endif\r
  92 #endif  /* configSYSTICK_CLOCK_HZ */\r
  93 \r
  94 /* Constants required to manipulate the core.  Registers first... */\r
  95 #define portNVIC_SYSTICK_CTRL_REG                       ( * ( ( volatile unsigned long * ) 0xe000e010 ) )\r
  96 #define portNVIC_SYSTICK_LOAD_REG                       ( * ( ( volatile unsigned long * ) 0xe000e014 ) )\r
  97 #define portNVIC_SYSTICK_CURRENT_VALUE_REG      ( * ( ( volatile unsigned long * ) 0xe000e018 ) )\r
  98 #define portNVIC_INT_CTRL_REG                           ( * ( ( volatile unsigned long * ) 0xe000ed04 ) )\r
  99 #define portNVIC_SYSPRI2_REG                            ( * ( ( volatile unsigned long * ) 0xe000ed20 ) )\r
 100 /* ...then bits in the registers. */\r
 101 #define portNVIC_SYSTICK_CLK_BIT                        ( 1UL << 2UL )\r
 102 #define portNVIC_SYSTICK_INT_BIT                        ( 1UL << 1UL )\r
 103 #define portNVIC_SYSTICK_ENABLE_BIT                     ( 1UL << 0UL )\r
 104 #define portNVIC_SYSTICK_COUNT_FLAG_BIT         ( 1UL << 16UL )\r
 105 #define portNVIC_PENDSVSET_BIT                          ( 1UL << 28UL )\r
 106 #define portNVIC_PENDSVCLEAR_BIT                        ( 1UL << 27UL )\r
 107 #define portNVIC_PEND_SYSTICK_CLEAR_BIT         ( 1UL << 25UL )\r
 108 \r
 109 #define portNVIC_PENDSV_PRI                             ( ( ( unsigned long ) configKERNEL_INTERRUPT_PRIORITY ) << 16UL )\r
 110 #define portNVIC_SYSTICK_PRI                    ( ( ( unsigned long ) configKERNEL_INTERRUPT_PRIORITY ) << 24UL )\r
 111 \r
 112 /* Constants required to set up the initial stack. */\r
 113 #define portINITIAL_XPSR                        ( 0x01000000 )\r
 114 \r
 115 /* The priority used by the kernel is assigned to a variable to make access\r
 116 from inline assembler easier. */\r
 117 const unsigned long ulKernelPriority = configKERNEL_INTERRUPT_PRIORITY;\r
 118 \r
 119 /* Each task maintains its own interrupt status in the critical nesting\r
 120 variable. */\r
 121 static unsigned portBASE_TYPE uxCriticalNesting = 0xaaaaaaaa;\r
 122 \r
 123 /*\r
 124  * Setup the timer to generate the tick interrupts.\r
 125  */\r
 126 static void prvSetupTimerInterrupt( void );\r
 127 \r
 128 /*\r
 129  * Exception handlers.\r
 130  */\r
 131 void xPortPendSVHandler( void ) __attribute__ (( naked ));\r
 132 void xPortSysTickHandler( void );\r
 133 void vPortSVCHandler( void ) __attribute__ (( naked ));\r
 134 \r
 135 /*\r
 136  * Start first task is a separate function so it can be tested in isolation.\r
 137  */\r
 138 static void prvPortStartFirstTask( void ) __attribute__ (( naked ));\r
 139 \r
 140 /*-----------------------------------------------------------*/\r
 141 \r
 142 /*\r
 143  * The number of SysTick increments that make up one tick period.\r
 144  */\r
 145 static unsigned long ulTimerReloadValueForOneTick = 0;\r
 146 \r
 147 /*\r
 148  * The maximum number of tick periods that can be suppressed is limited by the\r
 149  * 24 bit resolution of the SysTick timer.\r
 150  */\r
 151 #if configUSE_TICKLESS_IDLE == 1\r
 152         static unsigned long xMaximumPossibleSuppressedTicks = 0;\r
 153 #endif /* configUSE_TICKLESS_IDLE */\r
 154 \r
 155 \r
 156 /*-----------------------------------------------------------*/\r
 157 \r
 158 /*\r
 159  * See header file for description.\r
 160  */\r
 161 portSTACK_TYPE *pxPortInitialiseStack( portSTACK_TYPE *pxTopOfStack, pdTASK_CODE pxCode, void *pvParameters )\r
 162 {\r
 163         /* Simulate the stack frame as it would be created by a context switch\r
 164         interrupt. */\r
 165         pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */\r
 166         *pxTopOfStack = portINITIAL_XPSR;       /* xPSR */\r
 167         pxTopOfStack--;\r
 168         *pxTopOfStack = ( portSTACK_TYPE ) pxCode;      /* PC */\r
 169         pxTopOfStack--;\r
 170         *pxTopOfStack = 0;      /* LR */\r
 171         pxTopOfStack -= 5;      /* R12, R3, R2 and R1. */\r
 172         *pxTopOfStack = ( portSTACK_TYPE ) pvParameters;        /* R0 */\r
 173         pxTopOfStack -= 8;      /* R11, R10, R9, R8, R7, R6, R5 and R4. */\r
 174 \r
 175         return pxTopOfStack;\r
 176 }\r
 177 /*-----------------------------------------------------------*/\r
 178 \r
 179 void vPortSVCHandler( void )\r
 180 {\r
 181         __asm volatile (\r
 182                                         "       ldr     r3, pxCurrentTCBConst2          \n" /* Restore the context. */\r
 183                                         "       ldr r1, [r3]                                    \n" /* Use pxCurrentTCBConst to get the pxCurrentTCB address. */\r
 184                                         "       ldr r0, [r1]                                    \n" /* The first item in pxCurrentTCB is the task top of stack. */\r
 185                                         "       ldmia r0!, {r4-r11}                             \n" /* Pop the registers that are not automatically saved on exception entry and the critical nesting count. */\r
 186                                         "       msr psp, r0                                             \n" /* Restore the task stack pointer. */\r
 187                                         "       mov r0, #0                                              \n"\r
 188                                         "       msr     basepri, r0                                     \n"\r
 189                                         "       orr r14, #0xd                                   \n"\r
 190                                         "       bx r14                                                  \n"\r
 191                                         "                                                                       \n"\r
 192                                         "       .align 2                                                \n"\r
 193                                         "pxCurrentTCBConst2: .word pxCurrentTCB                         \n"\r
 194                                 );\r
 195 }\r
 196 /*-----------------------------------------------------------*/\r
 197 \r
 198 static void prvPortStartFirstTask( void )\r
 199 {\r
 200         __asm volatile(\r
 201                                         " ldr r0, =0xE000ED08   \n" /* Use the NVIC offset register to locate the stack. */\r
 202                                         " ldr r0, [r0]                  \n"\r
 203                                         " ldr r0, [r0]                  \n"\r
 204                                         " msr msp, r0                   \n" /* Set the msp back to the start of the stack. */\r
 205                                         " cpsie i                               \n" /* Globally enable interrupts. */\r
 206                                         " svc 0                                 \n" /* System call to start first task. */\r
 207                                         " nop                                   \n"\r
 208                                 );\r
 209 }\r
 210 /*-----------------------------------------------------------*/\r
 211 \r
 212 /*\r
 213  * See header file for description.\r
 214  */\r
 215 portBASE_TYPE xPortStartScheduler( void )\r
 216 {\r
 217         /* configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0.\r
 218         See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */\r
 219         configASSERT( configMAX_SYSCALL_INTERRUPT_PRIORITY );\r
 220 \r
 221         /* Make PendSV, CallSV and SysTick the same priroity as the kernel. */\r
 222         portNVIC_SYSPRI2_REG |= portNVIC_PENDSV_PRI;\r
 223         portNVIC_SYSPRI2_REG |= portNVIC_SYSTICK_PRI;\r
 224 \r
 225         /* Start the timer that generates the tick ISR.  Interrupts are disabled\r
 226         here already. */\r
 227         prvSetupTimerInterrupt();\r
 228 \r
 229         /* Initialise the critical nesting count ready for the first task. */\r
 230         uxCriticalNesting = 0;\r
 231 \r
 232         /* Start the first task. */\r
 233         prvPortStartFirstTask();\r
 234 \r
 235         /* Should not get here! */\r
 236         return 0;\r
 237 }\r
 238 /*-----------------------------------------------------------*/\r
 239 \r
 240 void vPortEndScheduler( void )\r
 241 {\r
 242         /* It is unlikely that the CM3 port will require this function as there\r
 243         is nothing to return to.  */\r
 244 }\r
 245 /*-----------------------------------------------------------*/\r
 246 \r
 247 void vPortYieldFromISR( void )\r
 248 {\r
 249         /* Set a PendSV to request a context switch. */\r
 250         portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;\r
 251 }\r
 252 /*-----------------------------------------------------------*/\r
 253 \r
 254 void vPortEnterCritical( void )\r
 255 {\r
 256         portDISABLE_INTERRUPTS();\r
 257         uxCriticalNesting++;\r
 258 }\r
 259 /*-----------------------------------------------------------*/\r
 260 \r
 261 void vPortExitCritical( void )\r
 262 {\r
 263         uxCriticalNesting--;\r
 264         if( uxCriticalNesting == 0 )\r
 265         {\r
 266                 portENABLE_INTERRUPTS();\r
 267         }\r
 268 }\r
 269 /*-----------------------------------------------------------*/\r
 270 \r
 271 __attribute__(( naked )) unsigned long ulPortSetInterruptMask( void )\r
 272 {\r
 273         __asm volatile                                                                                                          \\r
 274         (                                                                                                                                       \\r
 275                 "       mrs r0, basepri                                                                                 \n" \\r
 276                 "       mov r1, %0                                                                                              \n"     \\r
 277                 "       msr basepri, r1                                                                                 \n" \\r
 278                 "       bx lr                                                                                                   \n" \\r
 279                 :: "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "r0", "r1"    \\r
 280         );\r
 281 \r
 282         /* This return will not be reached but is necessary to prevent compiler\r
 283         warnings. */\r
 284         return 0;\r
 285 }\r
 286 /*-----------------------------------------------------------*/\r
 287 \r
 288 __attribute__(( naked )) void vPortClearInterruptMask( unsigned long ulNewMaskValue )\r
 289 {\r
 290         __asm volatile                                                                                                  \\r
 291         (                                                                                                                               \\r
 292                 "       msr basepri, r0                                                                         \n"     \\r
 293                 "       bx lr                                                                                           \n" \\r
 294                 :::"r0"                                                                                                         \\r
 295         );\r
 296 }\r
 297 /*-----------------------------------------------------------*/\r
 298 \r
 299 void xPortPendSVHandler( void )\r
 300 {\r
 301         /* This is a naked function. */\r
 302 \r
 303         __asm volatile\r
 304         (\r
 305         "       mrs r0, psp                                                     \n"\r
 306         "                                                                               \n"\r
 307         "       ldr     r3, pxCurrentTCBConst                   \n" /* Get the location of the current TCB. */\r
 308         "       ldr     r2, [r3]                                                \n"\r
 309         "                                                                               \n"\r
 310         "       stmdb r0!, {r4-r11}                                     \n" /* Save the remaining registers. */\r
 311         "       str r0, [r2]                                            \n" /* Save the new top of stack into the first member of the TCB. */\r
 312         "                                                                               \n"\r
 313         "       stmdb sp!, {r3, r14}                            \n"\r
 314         "       mov r0, %0                                                      \n"\r
 315         "       msr basepri, r0                                         \n"\r
 316         "       bl vTaskSwitchContext                           \n"\r
 317         "       mov r0, #0                                                      \n"\r
 318         "       msr basepri, r0                                         \n"\r
 319         "       ldmia sp!, {r3, r14}                            \n"\r
 320         "                                                                               \n"     /* Restore the context, including the critical nesting count. */\r
 321         "       ldr r1, [r3]                                            \n"\r
 322         "       ldr r0, [r1]                                            \n" /* The first item in pxCurrentTCB is the task top of stack. */\r
 323         "       ldmia r0!, {r4-r11}                                     \n" /* Pop the registers. */\r
 324         "       msr psp, r0                                                     \n"\r
 325         "       bx r14                                                          \n"\r
 326         "                                                                               \n"\r
 327         "       .align 2                                                        \n"\r
 328         "pxCurrentTCBConst: .word pxCurrentTCB  \n"\r
 329         ::"i"(configMAX_SYSCALL_INTERRUPT_PRIORITY)\r
 330         );\r
 331 }\r
 332 /*-----------------------------------------------------------*/\r
 333 \r
 334 void xPortSysTickHandler( void )\r
 335 {\r
 336         /* If using preemption, also force a context switch. */\r
 337         #if configUSE_PREEMPTION == 1\r
 338                 portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;\r
 339         #endif\r
 340 \r
 341         #if configUSE_TICKLESS_IDLE == 1\r
 342                 portNVIC_SYSTICK_LOAD_REG = ulTimerReloadValueForOneTick;\r
 343         #endif\r
 344 \r
 345         ( void ) portSET_INTERRUPT_MASK_FROM_ISR();\r
 346         {\r
 347                 vTaskIncrementTick();\r
 348         }\r
 349         portCLEAR_INTERRUPT_MASK_FROM_ISR( 0 );\r
 350 }\r
 351 /*-----------------------------------------------------------*/\r
 352 \r
 353 #if configUSE_TICKLESS_IDLE == 1\r
 354 \r
 355         __attribute__((weak)) void vPortSuppressTicksAndSleep( portTickType xExpectedIdleTime )\r
 356         {\r
 357         unsigned long ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickIncrements;\r
 358 \r
 359                 /* Make sure the SysTick reload value does not overflow the counter. */\r
 360                 if( xExpectedIdleTime > xMaximumPossibleSuppressedTicks )\r
 361                 {\r
 362                         xExpectedIdleTime = xMaximumPossibleSuppressedTicks;\r
 363                 }\r
 364 \r
 365                 /* Calculate the reload value required to wait xExpectedIdleTime\r
 366                 tick periods.  -1 is used because this code will execute part way\r
 367                 through one of the tick periods, and the fraction of a tick period is\r
 368                 accounted for later. */\r
 369                 ulReloadValue = ( ulTimerReloadValueForOneTick * ( xExpectedIdleTime - 1UL ) );\r
 370                 if( ulReloadValue > ulStoppedTimerCompensation )\r
 371                 {\r
 372                         ulReloadValue -= ulStoppedTimerCompensation;\r
 373                 }\r
 374 \r
 375                 /* Stop the SysTick momentarily.  The time the SysTick is stopped for\r
 376                 is accounted for as best it can be, but using the tickless mode will\r
 377                 inevitably result in some tiny drift of the time maintained by the\r
 378                 kernel with respect to calendar time. */\r
 379                 portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT;\r
 380 \r
 381                 /* If a context switch is pending then abandon the low power entry as\r
 382                 the context switch might have been pended by an external interrupt that\r
 383                 requires processing. */\r
 384                 if( ( portNVIC_INT_CTRL_REG & portNVIC_PENDSVSET_BIT ) != 0 )\r
 385                 {\r
 386                         /* Restart SysTick. */\r
 387                         portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;\r
 388                 }\r
 389                 else\r
 390                 {\r
 391                         /* Adjust the reload value to take into account that the current\r
 392                         time slice is already partially complete. */\r
 393                         ulReloadValue += ( portNVIC_SYSTICK_LOAD_REG - ( portNVIC_SYSTICK_LOAD_REG - portNVIC_SYSTICK_CURRENT_VALUE_REG ) );\r
 394                         portNVIC_SYSTICK_LOAD_REG = ulReloadValue;\r
 395 \r
 396                         /* Clear the SysTick count flag and set the count value back to\r
 397                         zero. */\r
 398                         portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;\r
 399 \r
 400                         /* Restart SysTick. */\r
 401                         portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;\r
 402 \r
 403                         /* Sleep until something happens. */\r
 404                         portPRE_SLEEP_PROCESSING();\r
 405                         __asm volatile( "wfi" );\r
 406                         portPOST_SLEEP_PROCESSING();\r
 407 \r
 408                         /* Stop SysTick.  Again, the time the SysTick is stopped for is\r
 409                         accounted for as best it can be, but using the tickless mode will\r
 410                         inevitably result in some tiny drift of the time maintained by the\r
 411                         kernel with respect to calendar time. */\r
 412                         portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT;\r
 413 \r
 414                         if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 )\r
 415                         {\r
 416                                 /* The tick interrupt has already executed, and the SysTick\r
 417                                 count reloaded with the portNVIC_SYSTICK_LOAD_REG value.\r
 418                                 Reset the portNVIC_SYSTICK_LOAD_REG with whatever remains of\r
 419                                 this tick period. */\r
 420                                 portNVIC_SYSTICK_LOAD_REG = ulTimerReloadValueForOneTick - ( ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG );\r
 421 \r
 422                                 /* The tick interrupt handler will already have pended the tick\r
 423                                 processing in the kernel.  As the pending tick will be\r
 424                                 processed as soon as this function exits, the tick value\r
 425                                 maintained by the tick is stepped forward by one less than the\r
 426                                 time spent waiting. */\r
 427                                 ulCompleteTickPeriods = xExpectedIdleTime - 1UL;\r
 428                         }\r
 429                         else\r
 430                         {\r
 431                                 /* Something other than the tick interrupt ended the sleep.\r
 432                                 Work out how long the sleep lasted. */\r
 433                                 ulCompletedSysTickIncrements = ( xExpectedIdleTime * ulTimerReloadValueForOneTick ) - portNVIC_SYSTICK_CURRENT_VALUE_REG;\r
 434 \r
 435                                 /* How many complete tick periods passed while the processor\r
 436                                 was waiting? */\r
 437                                 ulCompleteTickPeriods = ulCompletedSysTickIncrements / ulTimerReloadValueForOneTick;\r
 438 \r
 439                                 /* The reload value is set to whatever fraction of a single tick\r
 440                                 period remains. */\r
 441                                 portNVIC_SYSTICK_LOAD_REG = ( ( ulCompleteTickPeriods + 1 ) * ulTimerReloadValueForOneTick ) - ulCompletedSysTickIncrements;\r
 442                         }\r
 443 \r
 444                         /* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG\r
 445                         again, then set portNVIC_SYSTICK_LOAD_REG back to its standard\r
 446                         value. */\r
 447                         portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;\r
 448                         portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;\r
 449 \r
 450                         vTaskStepTick( ulCompleteTickPeriods );\r
 451                 }\r
 452         }\r
 453 \r
 454 #endif /* #if configUSE_TICKLESS_IDLE */\r
 455 /*-----------------------------------------------------------*/\r
 456 \r
 457 /*\r
 458  * Setup the systick timer to generate the tick interrupts at the required\r
 459  * frequency.\r
 460  */\r
 461 void prvSetupTimerInterrupt( void )\r
 462 {\r
 463         /* Calculate the constants required to configure the tick interrupt. */\r
 464         ulTimerReloadValueForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;\r
 465         #if configUSE_TICKLESS_IDLE == 1\r
 466                 xMaximumPossibleSuppressedTicks = 0xffffffUL / ( ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL );\r
 467         #endif /* configUSE_TICKLESS_IDLE */\r
 468 \r
 469         /* Configure SysTick to interrupt at the requested rate. */\r
 470         portNVIC_SYSTICK_LOAD_REG = ulTimerReloadValueForOneTick;\r
 471         portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;\r
 472 }\r
 473 /*-----------------------------------------------------------*/\r
 474 \r