git.sur5r.net Git - freertos/blob - FreeRTOS/Source/portable/GCC/ARM_CM3/port.c

   1 /*\r
   2     FreeRTOS V7.4.2 - Copyright (C) 2013 Real Time Engineers Ltd.\r
   3 \r
   4     FEATURES AND PORTS ARE ADDED TO FREERTOS ALL THE TIME.  PLEASE VISIT\r
   5     http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
   6 \r
   7     ***************************************************************************\r
   8      *                                                                       *\r
   9      *    FreeRTOS tutorial books are available in pdf and paperback.        *\r
  10      *    Complete, revised, and edited pdf reference manuals are also       *\r
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  12      *                                                                       *\r
  13      *    Purchasing FreeRTOS documentation will not only help you, by       *\r
  14      *    ensuring you get running as quickly as possible and with an        *\r
  15      *    in-depth knowledge of how to use FreeRTOS, it will also help       *\r
  16      *    the FreeRTOS project to continue with its mission of providing     *\r
  17      *    professional grade, cross platform, de facto standard solutions    *\r
  18      *    for microcontrollers - completely free of charge!                  *\r
  19      *                                                                       *\r
  20      *    >>> See http://www.FreeRTOS.org/Documentation for details. <<<     *\r
  21      *                                                                       *\r
  22      *    Thank you for using FreeRTOS, and thank you for your support!      *\r
  23      *                                                                       *\r
  24     ***************************************************************************\r
  25 \r
  26 \r
  27     This file is part of the FreeRTOS distribution.\r
  28 \r
  29     FreeRTOS is free software; you can redistribute it and/or modify it under\r
  30     the terms of the GNU General Public License (version 2) as published by the\r
  31     Free Software Foundation AND MODIFIED BY the FreeRTOS exception.\r
  32 \r
  33     >>>>>>NOTE<<<<<< The modification to the GPL is included to allow you to\r
  34     distribute a combined work that includes FreeRTOS without being obliged to\r
  35     provide the source code for proprietary components outside of the FreeRTOS\r
  36     kernel.\r
  37 \r
  38     FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r
  39     WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r
  40     FOR A PARTICULAR PURPOSE.  See the GNU General Public License for more\r
  41     details. You should have received a copy of the GNU General Public License\r
  42     and the FreeRTOS license exception along with FreeRTOS; if not it can be\r
  43     viewed here: http://www.freertos.org/a00114.html and also obtained by\r
  44     writing to Real Time Engineers Ltd., contact details for whom are available\r
  45     on the FreeRTOS WEB site.\r
  46 \r
  47     1 tab == 4 spaces!\r
  48 \r
  49     ***************************************************************************\r
  50      *                                                                       *\r
  51      *    Having a problem?  Start by reading the FAQ "My application does   *\r
  52      *    not run, what could be wrong?"                                     *\r
  53      *                                                                       *\r
  54      *    http://www.FreeRTOS.org/FAQHelp.html                               *\r
  55      *                                                                       *\r
  56     ***************************************************************************\r
  57 \r
  58 \r
  59     http://www.FreeRTOS.org - Documentation, books, training, latest versions,\r
  60     license and Real Time Engineers Ltd. contact details.\r
  61 \r
  62     http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
  63     including FreeRTOS+Trace - an indispensable productivity tool, and our new\r
  64     fully thread aware and reentrant UDP/IP stack.\r
  65 \r
  66     http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High\r
  67     Integrity Systems, who sell the code with commercial support,\r
  68     indemnification and middleware, under the OpenRTOS brand.\r
  69 \r
  70     http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
  71     engineered and independently SIL3 certified version for use in safety and\r
  72     mission critical applications that require provable dependability.\r
  73 */\r
  74 \r
  75 /*-----------------------------------------------------------\r
  76  * Implementation of functions defined in portable.h for the ARM CM3 port.\r
  77  *----------------------------------------------------------*/\r
  78 \r
  79 /* Scheduler includes. */\r
  80 #include "FreeRTOS.h"\r
  81 #include "task.h"\r
  82 \r
  83 /* For backward compatibility, ensure configKERNEL_INTERRUPT_PRIORITY is\r
  84 defined.  The value should also ensure backward compatibility.\r
  85 FreeRTOS.org versions prior to V4.4.0 did not include this definition. */\r
  86 #ifndef configKERNEL_INTERRUPT_PRIORITY\r
  87         #define configKERNEL_INTERRUPT_PRIORITY 255\r
  88 #endif\r
  89 \r
  90 #ifndef configSYSTICK_CLOCK_HZ\r
  91         #define configSYSTICK_CLOCK_HZ configCPU_CLOCK_HZ\r
  92 #endif\r
  93 \r
  94 /* Constants required to manipulate the core.  Registers first... */\r
  95 #define portNVIC_SYSTICK_CTRL_REG                       ( * ( ( volatile unsigned long * ) 0xe000e010 ) )\r
  96 #define portNVIC_SYSTICK_LOAD_REG                       ( * ( ( volatile unsigned long * ) 0xe000e014 ) )\r
  97 #define portNVIC_SYSTICK_CURRENT_VALUE_REG      ( * ( ( volatile unsigned long * ) 0xe000e018 ) )\r
  98 #define portNVIC_SYSPRI2_REG                            ( * ( ( volatile unsigned long * ) 0xe000ed20 ) )\r
  99 /* ...then bits in the registers. */\r
 100 #define portNVIC_SYSTICK_CLK_BIT                        ( 1UL << 2UL )\r
 101 #define portNVIC_SYSTICK_INT_BIT                        ( 1UL << 1UL )\r
 102 #define portNVIC_SYSTICK_ENABLE_BIT                     ( 1UL << 0UL )\r
 103 #define portNVIC_SYSTICK_COUNT_FLAG_BIT         ( 1UL << 16UL )\r
 104 #define portNVIC_PENDSVCLEAR_BIT                        ( 1UL << 27UL )\r
 105 #define portNVIC_PEND_SYSTICK_CLEAR_BIT         ( 1UL << 25UL )\r
 106 \r
 107 #define portNVIC_PENDSV_PRI                                     ( ( ( unsigned long ) configKERNEL_INTERRUPT_PRIORITY ) << 16UL )\r
 108 #define portNVIC_SYSTICK_PRI                            ( ( ( unsigned long ) configKERNEL_INTERRUPT_PRIORITY ) << 24UL )\r
 109 \r
 110 /* Constants required to check the validity of an interrupt prority. */\r
 111 #define portFIRST_USER_INTERRUPT_NUMBER         ( 16 )\r
 112 #define portNVIC_IP_REGISTERS_OFFSET_16         ( 0xE000E3F0 )\r
 113 #define portAIRCR_REG                                           ( * ( ( volatile unsigned long * ) 0xE000ED0C ) )\r
 114 #define portPRIORITY_GROUP_MASK                         ( 0x07UL << 8UL )\r
 115 \r
 116 /* Constants required to set up the initial stack. */\r
 117 #define portINITIAL_XPSR                                        ( 0x01000000 )\r
 118 \r
 119 /* The systick is a 24-bit counter. */\r
 120 #define portMAX_24_BIT_NUMBER                           ( 0xffffffUL )\r
 121 \r
 122 /* A fiddle factor to estimate the number of SysTick counts that would have\r
 123 occurred while the SysTick counter is stopped during tickless idle\r
 124 calculations. */\r
 125 #define portMISSED_COUNTS_FACTOR                        ( 45UL )\r
 126 \r
 127 /* Each task maintains its own interrupt status in the critical nesting\r
 128 variable. */\r
 129 static unsigned portBASE_TYPE uxCriticalNesting = 0xaaaaaaaa;\r
 130 \r
 131 /*\r
 132  * Setup the timer to generate the tick interrupts.  The implementation in this\r
 133  * file is weak to allow application writers to change the timer used to\r
 134  * generate the tick interrupt.\r
 135  */\r
 136 void vPortSetupTimerInterrupt( void );\r
 137 \r
 138 /*\r
 139  * Exception handlers.\r
 140  */\r
 141 void xPortPendSVHandler( void ) __attribute__ (( naked ));\r
 142 void xPortSysTickHandler( void );\r
 143 void vPortSVCHandler( void ) __attribute__ (( naked ));\r
 144 \r
 145 /*\r
 146  * Start first task is a separate function so it can be tested in isolation.\r
 147  */\r
 148 static void prvPortStartFirstTask( void ) __attribute__ (( naked ));\r
 149 \r
 150 /*-----------------------------------------------------------*/\r
 151 \r
 152 /*\r
 153  * The number of SysTick increments that make up one tick period.\r
 154  */\r
 155 #if configUSE_TICKLESS_IDLE == 1\r
 156         static unsigned long ulTimerCountsForOneTick = 0;\r
 157 #endif /* configUSE_TICKLESS_IDLE */\r
 158 \r
 159 /*\r
 160  * The maximum number of tick periods that can be suppressed is limited by the\r
 161  * 24 bit resolution of the SysTick timer.\r
 162  */\r
 163 #if configUSE_TICKLESS_IDLE == 1\r
 164         static unsigned long xMaximumPossibleSuppressedTicks = 0;\r
 165 #endif /* configUSE_TICKLESS_IDLE */\r
 166 \r
 167 /*\r
 168  * Compensate for the CPU cycles that pass while the SysTick is stopped (low\r
 169  * power functionality only.\r
 170  */\r
 171 #if configUSE_TICKLESS_IDLE == 1\r
 172         static unsigned long ulStoppedTimerCompensation = 0;\r
 173 #endif /* configUSE_TICKLESS_IDLE */\r
 174 \r
 175 /*\r
 176  * Used by the portASSERT_IF_INTERRUPT_PRIORITY_INVALID() macro to ensure \r
 177  * FreeRTOS API functions are not called from interrupts that have been assigned\r
 178  * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY.\r
 179  */\r
 180 #if ( configASSERT_DEFINED == 1 )\r
 181          static unsigned char ucMaxSysCallPriority = 0;\r
 182          static const volatile unsigned char * const pcInterruptPriorityRegisters = ( const volatile unsigned char * const ) portNVIC_IP_REGISTERS_OFFSET_16;\r
 183 #endif /* configASSERT_DEFINED */\r
 184 \r
 185 /*-----------------------------------------------------------*/\r
 186 \r
 187 /*\r
 188  * See header file for description.\r
 189  */\r
 190 portSTACK_TYPE *pxPortInitialiseStack( portSTACK_TYPE *pxTopOfStack, pdTASK_CODE pxCode, void *pvParameters )\r
 191 {\r
 192         /* Simulate the stack frame as it would be created by a context switch\r
 193         interrupt. */\r
 194         pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */\r
 195         *pxTopOfStack = portINITIAL_XPSR;       /* xPSR */\r
 196         pxTopOfStack--;\r
 197         *pxTopOfStack = ( portSTACK_TYPE ) pxCode;      /* PC */\r
 198         pxTopOfStack--;\r
 199         *pxTopOfStack = 0;      /* LR */\r
 200         pxTopOfStack -= 5;      /* R12, R3, R2 and R1. */\r
 201         *pxTopOfStack = ( portSTACK_TYPE ) pvParameters;        /* R0 */\r
 202         pxTopOfStack -= 8;      /* R11, R10, R9, R8, R7, R6, R5 and R4. */\r
 203 \r
 204         return pxTopOfStack;\r
 205 }\r
 206 /*-----------------------------------------------------------*/\r
 207 \r
 208 void vPortSVCHandler( void )\r
 209 {\r
 210         __asm volatile (\r
 211                                         "       ldr     r3, pxCurrentTCBConst2          \n" /* Restore the context. */\r
 212                                         "       ldr r1, [r3]                                    \n" /* Use pxCurrentTCBConst to get the pxCurrentTCB address. */\r
 213                                         "       ldr r0, [r1]                                    \n" /* The first item in pxCurrentTCB is the task top of stack. */\r
 214                                         "       ldmia r0!, {r4-r11}                             \n" /* Pop the registers that are not automatically saved on exception entry and the critical nesting count. */\r
 215                                         "       msr psp, r0                                             \n" /* Restore the task stack pointer. */\r
 216                                         "       mov r0, #0                                              \n"\r
 217                                         "       msr     basepri, r0                                     \n"\r
 218                                         "       orr r14, #0xd                                   \n"\r
 219                                         "       bx r14                                                  \n"\r
 220                                         "                                                                       \n"\r
 221                                         "       .align 2                                                \n"\r
 222                                         "pxCurrentTCBConst2: .word pxCurrentTCB                         \n"\r
 223                                 );\r
 224 }\r
 225 /*-----------------------------------------------------------*/\r
 226 \r
 227 static void prvPortStartFirstTask( void )\r
 228 {\r
 229         __asm volatile(\r
 230                                         " ldr r0, =0xE000ED08   \n" /* Use the NVIC offset register to locate the stack. */\r
 231                                         " ldr r0, [r0]                  \n"\r
 232                                         " ldr r0, [r0]                  \n"\r
 233                                         " msr msp, r0                   \n" /* Set the msp back to the start of the stack. */\r
 234                                         " cpsie i                               \n" /* Globally enable interrupts. */\r
 235                                         " svc 0                                 \n" /* System call to start first task. */\r
 236                                         " nop                                   \n"\r
 237                                 );\r
 238 }\r
 239 /*-----------------------------------------------------------*/\r
 240 \r
 241 /*\r
 242  * See header file for description.\r
 243  */\r
 244 portBASE_TYPE xPortStartScheduler( void )\r
 245 {\r
 246         /* configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0.\r
 247         See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */\r
 248         configASSERT( configMAX_SYSCALL_INTERRUPT_PRIORITY );\r
 249 \r
 250         #if( configASSERT_DEFINED == 1 )\r
 251         {\r
 252                 volatile unsigned long ulOriginalPriority;\r
 253                 volatile char * const pcFirstUserPriorityRegister = ( volatile char * const ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER );\r
 254 \r
 255                 /* Determine the maximum priority from which ISR safe FreeRTOS API\r
 256                 functions can be called.  ISR safe functions are those that end in\r
 257                 "FromISR".  FreeRTOS maintains separate thread and ISR API functions to\r
 258                 ensure interrupt entry is as fast and simple as possible.\r
 259 \r
 260                 Save the interrupt priority value that is about to be clobbered. */\r
 261                 ulOriginalPriority = *pcFirstUserPriorityRegister;\r
 262 \r
 263                 /* Write the configMAX_SYSCALL_INTERRUPT_PRIORITY value to an interrupt\r
 264                 priority register. */\r
 265                 *pcFirstUserPriorityRegister = configMAX_SYSCALL_INTERRUPT_PRIORITY;\r
 266 \r
 267                 /* Read back the written priority to obtain its value as seen by the\r
 268                 hardware, which will only implement a subset of the priority bits. */\r
 269                 ucMaxSysCallPriority = *pcFirstUserPriorityRegister;\r
 270 \r
 271                 /* Restore the clobbered interrupt priority register to its original\r
 272                 value. */\r
 273                 *pcFirstUserPriorityRegister = ulOriginalPriority;\r
 274         }\r
 275         #endif /* conifgASSERT_DEFINED */\r
 276 \r
 277         /* Make PendSV and SysTick the lowest priority interrupts. */\r
 278         portNVIC_SYSPRI2_REG |= portNVIC_PENDSV_PRI;\r
 279         portNVIC_SYSPRI2_REG |= portNVIC_SYSTICK_PRI;\r
 280 \r
 281         /* Start the timer that generates the tick ISR.  Interrupts are disabled\r
 282         here already. */\r
 283         vPortSetupTimerInterrupt();\r
 284 \r
 285         /* Initialise the critical nesting count ready for the first task. */\r
 286         uxCriticalNesting = 0;\r
 287 \r
 288         /* Start the first task. */\r
 289         prvPortStartFirstTask();\r
 290 \r
 291         /* Should not get here! */\r
 292         return 0;\r
 293 }\r
 294 /*-----------------------------------------------------------*/\r
 295 \r
 296 void vPortEndScheduler( void )\r
 297 {\r
 298         /* It is unlikely that the CM3 port will require this function as there\r
 299         is nothing to return to.  */\r
 300 }\r
 301 /*-----------------------------------------------------------*/\r
 302 \r
 303 void vPortYield( void )\r
 304 {\r
 305         /* Set a PendSV to request a context switch. */\r
 306         portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;\r
 307 \r
 308         /* Barriers are normally not required but do ensure the code is completely\r
 309         within the specified behaviour for the architecture. */\r
 310         __asm volatile( "dsb" );\r
 311         __asm volatile( "isb" );\r
 312 }\r
 313 /*-----------------------------------------------------------*/\r
 314 \r
 315 void vPortEnterCritical( void )\r
 316 {\r
 317         portDISABLE_INTERRUPTS();\r
 318         uxCriticalNesting++;\r
 319         __asm volatile( "dsb" );\r
 320         __asm volatile( "isb" );\r
 321 }\r
 322 /*-----------------------------------------------------------*/\r
 323 \r
 324 void vPortExitCritical( void )\r
 325 {\r
 326         uxCriticalNesting--;\r
 327         if( uxCriticalNesting == 0 )\r
 328         {\r
 329                 portENABLE_INTERRUPTS();\r
 330         }\r
 331 }\r
 332 /*-----------------------------------------------------------*/\r
 333 \r
 334 __attribute__(( naked )) unsigned long ulPortSetInterruptMask( void )\r
 335 {\r
 336         __asm volatile                                                                                                          \\r
 337         (                                                                                                                                       \\r
 338                 "       mrs r0, basepri                                                                                 \n" \\r
 339                 "       mov r1, %0                                                                                              \n"     \\r
 340                 "       msr basepri, r1                                                                                 \n" \\r
 341                 "       bx lr                                                                                                   \n" \\r
 342                 :: "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "r0", "r1"    \\r
 343         );\r
 344 \r
 345         /* This return will not be reached but is necessary to prevent compiler\r
 346         warnings. */\r
 347         return 0;\r
 348 }\r
 349 /*-----------------------------------------------------------*/\r
 350 \r
 351 __attribute__(( naked )) void vPortClearInterruptMask( unsigned long ulNewMaskValue )\r
 352 {\r
 353         __asm volatile                                                                                                  \\r
 354         (                                                                                                                               \\r
 355                 "       msr basepri, r0                                                                         \n"     \\r
 356                 "       bx lr                                                                                           \n" \\r
 357                 :::"r0"                                                                                                         \\r
 358         );\r
 359 \r
 360         /* Just to avoid compiler warnings. */\r
 361         ( void ) ulNewMaskValue;\r
 362 }\r
 363 /*-----------------------------------------------------------*/\r
 364 \r
 365 void xPortPendSVHandler( void )\r
 366 {\r
 367         /* This is a naked function. */\r
 368 \r
 369         __asm volatile\r
 370         (\r
 371         "       mrs r0, psp                                                     \n"\r
 372         "                                                                               \n"\r
 373         "       ldr     r3, pxCurrentTCBConst                   \n" /* Get the location of the current TCB. */\r
 374         "       ldr     r2, [r3]                                                \n"\r
 375         "                                                                               \n"\r
 376         "       stmdb r0!, {r4-r11}                                     \n" /* Save the remaining registers. */\r
 377         "       str r0, [r2]                                            \n" /* Save the new top of stack into the first member of the TCB. */\r
 378         "                                                                               \n"\r
 379         "       stmdb sp!, {r3, r14}                            \n"\r
 380         "       mov r0, %0                                                      \n"\r
 381         "       msr basepri, r0                                         \n"\r
 382         "       bl vTaskSwitchContext                           \n"\r
 383         "       mov r0, #0                                                      \n"\r
 384         "       msr basepri, r0                                         \n"\r
 385         "       ldmia sp!, {r3, r14}                            \n"\r
 386         "                                                                               \n"     /* Restore the context, including the critical nesting count. */\r
 387         "       ldr r1, [r3]                                            \n"\r
 388         "       ldr r0, [r1]                                            \n" /* The first item in pxCurrentTCB is the task top of stack. */\r
 389         "       ldmia r0!, {r4-r11}                                     \n" /* Pop the registers. */\r
 390         "       msr psp, r0                                                     \n"\r
 391         "       bx r14                                                          \n"\r
 392         "                                                                               \n"\r
 393         "       .align 2                                                        \n"\r
 394         "pxCurrentTCBConst: .word pxCurrentTCB  \n"\r
 395         ::"i"(configMAX_SYSCALL_INTERRUPT_PRIORITY)\r
 396         );\r
 397 }\r
 398 /*-----------------------------------------------------------*/\r
 399 \r
 400 void xPortSysTickHandler( void )\r
 401 {\r
 402         /* The SysTick runs at the lowest interrupt priority, so when this interrupt\r
 403         executes all interrupts must be unmasked.  There is therefore no need to\r
 404         save and then restore the interrupt mask value as its value is already\r
 405         known. */\r
 406         ( void ) portSET_INTERRUPT_MASK_FROM_ISR();\r
 407         {\r
 408                 /* Increment the RTOS tick. */\r
 409                 if( xTaskIncrementTick() != pdFALSE )\r
 410                 {\r
 411                         /* A context switch is required.  Context switching is performed in\r
 412                         the PendSV interrupt.  Pend the PendSV interrupt. */\r
 413                         portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;\r
 414                 }\r
 415         }\r
 416         portCLEAR_INTERRUPT_MASK_FROM_ISR( 0 );\r
 417 }\r
 418 /*-----------------------------------------------------------*/\r
 419 \r
 420 #if configUSE_TICKLESS_IDLE == 1\r
 421 \r
 422         __attribute__((weak)) void vPortSuppressTicksAndSleep( portTickType xExpectedIdleTime )\r
 423         {\r
 424         unsigned long ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements;\r
 425         portTickType xModifiableIdleTime;\r
 426 \r
 427                 /* Make sure the SysTick reload value does not overflow the counter. */\r
 428                 if( xExpectedIdleTime > xMaximumPossibleSuppressedTicks )\r
 429                 {\r
 430                         xExpectedIdleTime = xMaximumPossibleSuppressedTicks;\r
 431                 }\r
 432 \r
 433                 /* Stop the SysTick momentarily.  The time the SysTick is stopped for\r
 434                 is accounted for as best it can be, but using the tickless mode will\r
 435                 inevitably result in some tiny drift of the time maintained by the\r
 436                 kernel with respect to calendar time. */\r
 437                 portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT;\r
 438 \r
 439                 /* Calculate the reload value required to wait xExpectedIdleTime\r
 440                 tick periods.  -1 is used because this code will execute part way\r
 441                 through one of the tick periods. */\r
 442                 ulReloadValue = portNVIC_SYSTICK_CURRENT_VALUE_REG + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) );\r
 443                 if( ulReloadValue > ulStoppedTimerCompensation )\r
 444                 {\r
 445                         ulReloadValue -= ulStoppedTimerCompensation;\r
 446                 }\r
 447 \r
 448                 /* Enter a critical section but don't use the taskENTER_CRITICAL()\r
 449                 method as that will mask interrupts that should exit sleep mode. */\r
 450                 __asm volatile( "cpsid i" );\r
 451 \r
 452                 /* If a context switch is pending or a task is waiting for the scheduler\r
 453                 to be unsuspended then abandon the low power entry. */\r
 454                 if( eTaskConfirmSleepModeStatus() == eAbortSleep )\r
 455                 {\r
 456                         /* Restart SysTick. */\r
 457                         portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;\r
 458 \r
 459                         /* Re-enable interrupts - see comments above the cpsid instruction()\r
 460                         above. */\r
 461                         __asm volatile( "cpsie i" );\r
 462                 }\r
 463                 else\r
 464                 {\r
 465                         /* Set the new reload value. */\r
 466                         portNVIC_SYSTICK_LOAD_REG = ulReloadValue;\r
 467 \r
 468                         /* Clear the SysTick count flag and set the count value back to\r
 469                         zero. */\r
 470                         portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;\r
 471 \r
 472                         /* Restart SysTick. */\r
 473                         portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;\r
 474 \r
 475                         /* Sleep until something happens.  configPRE_SLEEP_PROCESSING() can\r
 476                         set its parameter to 0 to indicate that its implementation contains\r
 477                         its own wait for interrupt or wait for event instruction, and so wfi\r
 478                         should not be executed again.  However, the original expected idle\r
 479                         time variable must remain unmodified, so a copy is taken. */\r
 480                         xModifiableIdleTime = xExpectedIdleTime;\r
 481                         configPRE_SLEEP_PROCESSING( xModifiableIdleTime );\r
 482                         if( xModifiableIdleTime > 0 )\r
 483                         {\r
 484                                 __asm volatile( "dsb" );\r
 485                                 __asm volatile( "wfi" );\r
 486                                 __asm volatile( "isb" );\r
 487                         }\r
 488                         configPOST_SLEEP_PROCESSING( xExpectedIdleTime );\r
 489 \r
 490                         /* Stop SysTick.  Again, the time the SysTick is stopped for is\r
 491                         accounted for as best it can be, but using the tickless mode will\r
 492                         inevitably result in some tiny drift of the time maintained by the\r
 493                         kernel with respect to calendar time. */\r
 494                         portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT;\r
 495 \r
 496                         /* Re-enable interrupts - see comments above the cpsid instruction()\r
 497                         above. */\r
 498                         __asm volatile( "cpsie i" );\r
 499 \r
 500                         if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 )\r
 501                         {\r
 502                                 /* The tick interrupt has already executed, and the SysTick\r
 503                                 count reloaded with ulReloadValue.  Reset the\r
 504                                 portNVIC_SYSTICK_LOAD_REG with whatever remains of this tick\r
 505                                 period. */\r
 506                                 portNVIC_SYSTICK_LOAD_REG = ( ulTimerCountsForOneTick - 1UL ) - ( ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG );\r
 507 \r
 508                                 /* The tick interrupt handler will already have pended the tick\r
 509                                 processing in the kernel.  As the pending tick will be\r
 510                                 processed as soon as this function exits, the tick value\r
 511                                 maintained by the tick is stepped forward by one less than the\r
 512                                 time spent waiting. */\r
 513                                 ulCompleteTickPeriods = xExpectedIdleTime - 1UL;\r
 514                         }\r
 515                         else\r
 516                         {\r
 517                                 /* Something other than the tick interrupt ended the sleep.\r
 518                                 Work out how long the sleep lasted rounded to complete tick\r
 519                                 periods (not the ulReload value which accounted for part\r
 520                                 ticks). */\r
 521                                 ulCompletedSysTickDecrements = ( xExpectedIdleTime * ulTimerCountsForOneTick ) - portNVIC_SYSTICK_CURRENT_VALUE_REG;\r
 522 \r
 523                                 /* How many complete tick periods passed while the processor\r
 524                                 was waiting? */\r
 525                                 ulCompleteTickPeriods = ulCompletedSysTickDecrements / ulTimerCountsForOneTick;\r
 526 \r
 527                                 /* The reload value is set to whatever fraction of a single tick\r
 528                                 period remains. */\r
 529                                 portNVIC_SYSTICK_LOAD_REG = ( ( ulCompleteTickPeriods + 1 ) * ulTimerCountsForOneTick ) - ulCompletedSysTickDecrements;\r
 530                         }\r
 531 \r
 532                         /* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG\r
 533                         again, then set portNVIC_SYSTICK_LOAD_REG back to its standard\r
 534                         value. */\r
 535                         portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;\r
 536                         portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;\r
 537 \r
 538                         vTaskStepTick( ulCompleteTickPeriods );\r
 539 \r
 540                         /* The counter must start by the time the reload value is reset. */\r
 541                         configASSERT( portNVIC_SYSTICK_CURRENT_VALUE_REG );\r
 542                         portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;\r
 543                 }\r
 544         }\r
 545 \r
 546 #endif /* #if configUSE_TICKLESS_IDLE */\r
 547 /*-----------------------------------------------------------*/\r
 548 \r
 549 /*\r
 550  * Setup the systick timer to generate the tick interrupts at the required\r
 551  * frequency.\r
 552  */\r
 553 __attribute__(( weak )) void vPortSetupTimerInterrupt( void )\r
 554 {\r
 555         /* Calculate the constants required to configure the tick interrupt. */\r
 556         #if configUSE_TICKLESS_IDLE == 1\r
 557         {\r
 558                 ulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ );\r
 559                 xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick;\r
 560                 ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ );\r
 561         }\r
 562         #endif /* configUSE_TICKLESS_IDLE */\r
 563 \r
 564         /* Configure SysTick to interrupt at the requested rate. */\r
 565         portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;;\r
 566         portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;\r
 567 }\r
 568 /*-----------------------------------------------------------*/\r
 569 \r
 570 #if( configASSERT_DEFINED == 1 )\r
 571 \r
 572         void vPortValidateInterruptPriority( void )\r
 573         {\r
 574         unsigned long ulCurrentInterrupt;\r
 575         unsigned char ucCurrentPriority;\r
 576 \r
 577                 /* Obtain the number of the currently executing interrupt. */\r
 578                 __asm volatile( "mrs %0, ipsr" : "=r"( ulCurrentInterrupt ) );\r
 579 \r
 580                 /* Is the interrupt number a user defined interrupt? */\r
 581                 if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER )\r
 582                 {\r
 583                         /* Look up the interrupt's priority. */\r
 584                         ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ];\r
 585 \r
 586                         /* The following assertion will fail if a service routine (ISR) for \r
 587                         an interrupt that has been assigned a priority above\r
 588                         configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API\r
 589                         function.  ISR safe FreeRTOS API functions must *only* be called \r
 590                         from interrupts that have been assigned a priority at or below\r
 591                         configMAX_SYSCALL_INTERRUPT_PRIORITY.\r
 592                         \r
 593                         Numerically low interrupt priority numbers represent logically high\r
 594                         interrupt priorities, therefore the priority of the interrupt must \r
 595                         be set to a value equal to or numerically *higher* than \r
 596                         configMAX_SYSCALL_INTERRUPT_PRIORITY.\r
 597                         \r
 598                         Interrupts that use the FreeRTOS API must not be left at their\r
 599                         default priority of     zero as that is the highest possible priority,\r
 600                         which is guaranteed to be above configMAX_SYSCALL_INTERRUPT_PRIORITY, \r
 601                         and     therefore also guaranteed to be invalid.  \r
 602                         \r
 603                         FreeRTOS maintains separate thread and ISR API functions to ensure \r
 604                         interrupt entry is as fast and simple as possible.\r
 605                         \r
 606                         The following links provide detailed information:\r
 607                         http://www.freertos.org/RTOS-Cortex-M3-M4.html\r
 608                         http://www.freertos.org/FAQHelp.html */\r
 609                         configASSERT( ucCurrentPriority >= ucMaxSysCallPriority );\r
 610                 }\r
 611 \r
 612                 /* Priority grouping:  The interrupt controller (NVIC) allows the bits \r
 613                 that define each interrupt's priority to be split between bits that \r
 614                 define the interrupt's pre-emption priority bits and bits that define\r
 615                 the interrupt's sub-priority.  For simplicity all bits must be defined \r
 616                 to be pre-emption priority bits.  The following assertion will fail if\r
 617                 this is not the case (if some bits represent a sub-priority).  \r
 618                 \r
 619                 If CMSIS libraries are being used then the correct setting can be \r
 620                 achieved by calling     NVIC_SetPriorityGrouping( 0 ); before starting the \r
 621                 scheduler. */\r
 622                 configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) == 0 );\r
 623         }\r
 624 \r
 625 #endif /* configASSERT_DEFINED */\r
 626 \r
 627 \r
 628 \r
 629 \r
 630 \r
 631 \r
 632 \r
 633 \r
 634 \r
 635 \r
 636 \r
 637 \r
 638 \r
 639 \r
 640 \r
 641 \r
 642 \r
 643 \r
 644 \r
 645 \r
 646 \r