git.sur5r.net Git - freertos/blob - FreeRTOS/Source/portable/GCC/ARM_CM3/port.c

   1 /*\r
   2     FreeRTOS V7.4.2 - Copyright (C) 2013 Real Time Engineers Ltd.\r
   3 \r
   4     FEATURES AND PORTS ARE ADDED TO FREERTOS ALL THE TIME.  PLEASE VISIT\r
   5     http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
   6 \r
   7     ***************************************************************************\r
   8      *                                                                       *\r
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  10      *    Complete, revised, and edited pdf reference manuals are also       *\r
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  23      *                                                                       *\r
  24     ***************************************************************************\r
  25 \r
  26 \r
  27     This file is part of the FreeRTOS distribution.\r
  28 \r
  29     FreeRTOS is free software; you can redistribute it and/or modify it under\r
  30     the terms of the GNU General Public License (version 2) as published by the\r
  31     Free Software Foundation AND MODIFIED BY the FreeRTOS exception.\r
  32 \r
  33     >>>>>>NOTE<<<<<< The modification to the GPL is included to allow you to\r
  34     distribute a combined work that includes FreeRTOS without being obliged to\r
  35     provide the source code for proprietary components outside of the FreeRTOS\r
  36     kernel.\r
  37 \r
  38     FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r
  39     WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r
  40     FOR A PARTICULAR PURPOSE.  See the GNU General Public License for more\r
  41     details. You should have received a copy of the GNU General Public License\r
  42     and the FreeRTOS license exception along with FreeRTOS; if not it can be\r
  43     viewed here: http://www.freertos.org/a00114.html and also obtained by\r
  44     writing to Real Time Engineers Ltd., contact details for whom are available\r
  45     on the FreeRTOS WEB site.\r
  46 \r
  47     1 tab == 4 spaces!\r
  48 \r
  49     ***************************************************************************\r
  50      *                                                                       *\r
  51      *    Having a problem?  Start by reading the FAQ "My application does   *\r
  52      *    not run, what could be wrong?"                                     *\r
  53      *                                                                       *\r
  54      *    http://www.FreeRTOS.org/FAQHelp.html                               *\r
  55      *                                                                       *\r
  56     ***************************************************************************\r
  57 \r
  58 \r
  59     http://www.FreeRTOS.org - Documentation, books, training, latest versions,\r
  60     license and Real Time Engineers Ltd. contact details.\r
  61 \r
  62     http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
  63     including FreeRTOS+Trace - an indispensable productivity tool, and our new\r
  64     fully thread aware and reentrant UDP/IP stack.\r
  65 \r
  66     http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High\r
  67     Integrity Systems, who sell the code with commercial support,\r
  68     indemnification and middleware, under the OpenRTOS brand.\r
  69 \r
  70     http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
  71     engineered and independently SIL3 certified version for use in safety and\r
  72     mission critical applications that require provable dependability.\r
  73 */\r
  74 \r
  75 /*-----------------------------------------------------------\r
  76  * Implementation of functions defined in portable.h for the ARM CM3 port.\r
  77  *----------------------------------------------------------*/\r
  78 \r
  79 /* Scheduler includes. */\r
  80 #include "FreeRTOS.h"\r
  81 #include "task.h"\r
  82 \r
  83 /* For backward compatibility, ensure configKERNEL_INTERRUPT_PRIORITY is\r
  84 defined.  The value should also ensure backward compatibility.\r
  85 FreeRTOS.org versions prior to V4.4.0 did not include this definition. */\r
  86 #ifndef configKERNEL_INTERRUPT_PRIORITY\r
  87         #define configKERNEL_INTERRUPT_PRIORITY 255\r
  88 #endif\r
  89 \r
  90 #ifndef configSYSTICK_CLOCK_HZ\r
  91         #define configSYSTICK_CLOCK_HZ configCPU_CLOCK_HZ\r
  92 #endif\r
  93 \r
  94 /* Constants required to manipulate the core.  Registers first... */\r
  95 #define portNVIC_SYSTICK_CTRL_REG                       ( * ( ( volatile unsigned long * ) 0xe000e010 ) )\r
  96 #define portNVIC_SYSTICK_LOAD_REG                       ( * ( ( volatile unsigned long * ) 0xe000e014 ) )\r
  97 #define portNVIC_SYSTICK_CURRENT_VALUE_REG      ( * ( ( volatile unsigned long * ) 0xe000e018 ) )\r
  98 #define portNVIC_SYSPRI2_REG                            ( * ( ( volatile unsigned long * ) 0xe000ed20 ) )\r
  99 /* ...then bits in the registers. */\r
 100 #define portNVIC_SYSTICK_CLK_BIT                        ( 1UL << 2UL )\r
 101 #define portNVIC_SYSTICK_INT_BIT                        ( 1UL << 1UL )\r
 102 #define portNVIC_SYSTICK_ENABLE_BIT                     ( 1UL << 0UL )\r
 103 #define portNVIC_SYSTICK_COUNT_FLAG_BIT         ( 1UL << 16UL )\r
 104 #define portNVIC_PENDSVCLEAR_BIT                        ( 1UL << 27UL )\r
 105 #define portNVIC_PEND_SYSTICK_CLEAR_BIT         ( 1UL << 25UL )\r
 106 \r
 107 #define portNVIC_PENDSV_PRI                                     ( ( ( unsigned long ) configKERNEL_INTERRUPT_PRIORITY ) << 16UL )\r
 108 #define portNVIC_SYSTICK_PRI                            ( ( ( unsigned long ) configKERNEL_INTERRUPT_PRIORITY ) << 24UL )\r
 109 \r
 110 /* Constants required to set up the initial stack. */\r
 111 #define portINITIAL_XPSR                                        ( 0x01000000 )\r
 112 \r
 113 /* The systick is a 24-bit counter. */\r
 114 #define portMAX_24_BIT_NUMBER                           ( 0xffffffUL )\r
 115 \r
 116 /* A fiddle factor to estimate the number of SysTick counts that would have\r
 117 occurred while the SysTick counter is stopped during tickless idle\r
 118 calculations. */\r
 119 #define portMISSED_COUNTS_FACTOR                        ( 45UL )\r
 120 \r
 121 /* Each task maintains its own interrupt status in the critical nesting\r
 122 variable. */\r
 123 static unsigned portBASE_TYPE uxCriticalNesting = 0xaaaaaaaa;\r
 124 \r
 125 /*\r
 126  * Setup the timer to generate the tick interrupts.  The implementation in this\r
 127  * file is weak to allow application writers to change the timer used to\r
 128  * generate the tick interrupt.\r
 129  */\r
 130 void vPortSetupTimerInterrupt( void );\r
 131 \r
 132 /*\r
 133  * Exception handlers.\r
 134  */\r
 135 void xPortPendSVHandler( void ) __attribute__ (( naked ));\r
 136 void xPortSysTickHandler( void );\r
 137 void vPortSVCHandler( void ) __attribute__ (( naked ));\r
 138 \r
 139 /*\r
 140  * Start first task is a separate function so it can be tested in isolation.\r
 141  */\r
 142 static void prvPortStartFirstTask( void ) __attribute__ (( naked ));\r
 143 \r
 144 /*-----------------------------------------------------------*/\r
 145 \r
 146 /*\r
 147  * The number of SysTick increments that make up one tick period.\r
 148  */\r
 149 #if configUSE_TICKLESS_IDLE == 1\r
 150         static unsigned long ulTimerCountsForOneTick = 0;\r
 151 #endif /* configUSE_TICKLESS_IDLE */\r
 152 \r
 153 /*\r
 154  * The maximum number of tick periods that can be suppressed is limited by the\r
 155  * 24 bit resolution of the SysTick timer.\r
 156  */\r
 157 #if configUSE_TICKLESS_IDLE == 1\r
 158         static unsigned long xMaximumPossibleSuppressedTicks = 0;\r
 159 #endif /* configUSE_TICKLESS_IDLE */\r
 160 \r
 161 /*\r
 162  * Compensate for the CPU cycles that pass while the SysTick is stopped (low\r
 163  * power functionality only.\r
 164  */\r
 165 #if configUSE_TICKLESS_IDLE == 1\r
 166         static unsigned long ulStoppedTimerCompensation = 0;\r
 167 #endif /* configUSE_TICKLESS_IDLE */\r
 168 \r
 169 /*-----------------------------------------------------------*/\r
 170 \r
 171 /*\r
 172  * See header file for description.\r
 173  */\r
 174 portSTACK_TYPE *pxPortInitialiseStack( portSTACK_TYPE *pxTopOfStack, pdTASK_CODE pxCode, void *pvParameters )\r
 175 {\r
 176         /* Simulate the stack frame as it would be created by a context switch\r
 177         interrupt. */\r
 178         pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */\r
 179         *pxTopOfStack = portINITIAL_XPSR;       /* xPSR */\r
 180         pxTopOfStack--;\r
 181         *pxTopOfStack = ( portSTACK_TYPE ) pxCode;      /* PC */\r
 182         pxTopOfStack--;\r
 183         *pxTopOfStack = 0;      /* LR */\r
 184         pxTopOfStack -= 5;      /* R12, R3, R2 and R1. */\r
 185         *pxTopOfStack = ( portSTACK_TYPE ) pvParameters;        /* R0 */\r
 186         pxTopOfStack -= 8;      /* R11, R10, R9, R8, R7, R6, R5 and R4. */\r
 187 \r
 188         return pxTopOfStack;\r
 189 }\r
 190 /*-----------------------------------------------------------*/\r
 191 \r
 192 void vPortSVCHandler( void )\r
 193 {\r
 194         __asm volatile (\r
 195                                         "       ldr     r3, pxCurrentTCBConst2          \n" /* Restore the context. */\r
 196                                         "       ldr r1, [r3]                                    \n" /* Use pxCurrentTCBConst to get the pxCurrentTCB address. */\r
 197                                         "       ldr r0, [r1]                                    \n" /* The first item in pxCurrentTCB is the task top of stack. */\r
 198                                         "       ldmia r0!, {r4-r11}                             \n" /* Pop the registers that are not automatically saved on exception entry and the critical nesting count. */\r
 199                                         "       msr psp, r0                                             \n" /* Restore the task stack pointer. */\r
 200                                         "       mov r0, #0                                              \n"\r
 201                                         "       msr     basepri, r0                                     \n"\r
 202                                         "       orr r14, #0xd                                   \n"\r
 203                                         "       bx r14                                                  \n"\r
 204                                         "                                                                       \n"\r
 205                                         "       .align 2                                                \n"\r
 206                                         "pxCurrentTCBConst2: .word pxCurrentTCB                         \n"\r
 207                                 );\r
 208 }\r
 209 /*-----------------------------------------------------------*/\r
 210 \r
 211 static void prvPortStartFirstTask( void )\r
 212 {\r
 213         __asm volatile(\r
 214                                         " ldr r0, =0xE000ED08   \n" /* Use the NVIC offset register to locate the stack. */\r
 215                                         " ldr r0, [r0]                  \n"\r
 216                                         " ldr r0, [r0]                  \n"\r
 217                                         " msr msp, r0                   \n" /* Set the msp back to the start of the stack. */\r
 218                                         " cpsie i                               \n" /* Globally enable interrupts. */\r
 219                                         " svc 0                                 \n" /* System call to start first task. */\r
 220                                         " nop                                   \n"\r
 221                                 );\r
 222 }\r
 223 /*-----------------------------------------------------------*/\r
 224 \r
 225 /*\r
 226  * See header file for description.\r
 227  */\r
 228 portBASE_TYPE xPortStartScheduler( void )\r
 229 {\r
 230         /* configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0.\r
 231         See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */\r
 232         configASSERT( configMAX_SYSCALL_INTERRUPT_PRIORITY );\r
 233 \r
 234         /* Make PendSV and SysTick the lowest priority interrupts. */\r
 235         portNVIC_SYSPRI2_REG |= portNVIC_PENDSV_PRI;\r
 236         portNVIC_SYSPRI2_REG |= portNVIC_SYSTICK_PRI;\r
 237 \r
 238         /* Start the timer that generates the tick ISR.  Interrupts are disabled\r
 239         here already. */\r
 240         vPortSetupTimerInterrupt();\r
 241 \r
 242         /* Initialise the critical nesting count ready for the first task. */\r
 243         uxCriticalNesting = 0;\r
 244 \r
 245         /* Start the first task. */\r
 246         prvPortStartFirstTask();\r
 247 \r
 248         /* Should not get here! */\r
 249         return 0;\r
 250 }\r
 251 /*-----------------------------------------------------------*/\r
 252 \r
 253 void vPortEndScheduler( void )\r
 254 {\r
 255         /* It is unlikely that the CM3 port will require this function as there\r
 256         is nothing to return to.  */\r
 257 }\r
 258 /*-----------------------------------------------------------*/\r
 259 \r
 260 void vPortYield( void )\r
 261 {\r
 262         /* Set a PendSV to request a context switch. */\r
 263         portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;\r
 264 \r
 265         /* Barriers are normally not required but do ensure the code is completely\r
 266         within the specified behaviour for the architecture. */\r
 267         __asm volatile( "dsb" );\r
 268         __asm volatile( "isb" );\r
 269 }\r
 270 /*-----------------------------------------------------------*/\r
 271 \r
 272 void vPortEnterCritical( void )\r
 273 {\r
 274         portDISABLE_INTERRUPTS();\r
 275         uxCriticalNesting++;\r
 276         __asm volatile( "dsb" );\r
 277         __asm volatile( "isb" );\r
 278 }\r
 279 /*-----------------------------------------------------------*/\r
 280 \r
 281 void vPortExitCritical( void )\r
 282 {\r
 283         uxCriticalNesting--;\r
 284         if( uxCriticalNesting == 0 )\r
 285         {\r
 286                 portENABLE_INTERRUPTS();\r
 287         }\r
 288 }\r
 289 /*-----------------------------------------------------------*/\r
 290 \r
 291 __attribute__(( naked )) unsigned long ulPortSetInterruptMask( void )\r
 292 {\r
 293         __asm volatile                                                                                                          \\r
 294         (                                                                                                                                       \\r
 295                 "       mrs r0, basepri                                                                                 \n" \\r
 296                 "       mov r1, %0                                                                                              \n"     \\r
 297                 "       msr basepri, r1                                                                                 \n" \\r
 298                 "       bx lr                                                                                                   \n" \\r
 299                 :: "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "r0", "r1"    \\r
 300         );\r
 301 \r
 302         /* This return will not be reached but is necessary to prevent compiler\r
 303         warnings. */\r
 304         return 0;\r
 305 }\r
 306 /*-----------------------------------------------------------*/\r
 307 \r
 308 __attribute__(( naked )) void vPortClearInterruptMask( unsigned long ulNewMaskValue )\r
 309 {\r
 310         __asm volatile                                                                                                  \\r
 311         (                                                                                                                               \\r
 312                 "       msr basepri, r0                                                                         \n"     \\r
 313                 "       bx lr                                                                                           \n" \\r
 314                 :::"r0"                                                                                                         \\r
 315         );\r
 316 \r
 317         /* Just to avoid compiler warnings. */\r
 318         ( void ) ulNewMaskValue;\r
 319 }\r
 320 /*-----------------------------------------------------------*/\r
 321 \r
 322 void xPortPendSVHandler( void )\r
 323 {\r
 324         /* This is a naked function. */\r
 325 \r
 326         __asm volatile\r
 327         (\r
 328         "       mrs r0, psp                                                     \n"\r
 329         "                                                                               \n"\r
 330         "       ldr     r3, pxCurrentTCBConst                   \n" /* Get the location of the current TCB. */\r
 331         "       ldr     r2, [r3]                                                \n"\r
 332         "                                                                               \n"\r
 333         "       stmdb r0!, {r4-r11}                                     \n" /* Save the remaining registers. */\r
 334         "       str r0, [r2]                                            \n" /* Save the new top of stack into the first member of the TCB. */\r
 335         "                                                                               \n"\r
 336         "       stmdb sp!, {r3, r14}                            \n"\r
 337         "       mov r0, %0                                                      \n"\r
 338         "       msr basepri, r0                                         \n"\r
 339         "       bl vTaskSwitchContext                           \n"\r
 340         "       mov r0, #0                                                      \n"\r
 341         "       msr basepri, r0                                         \n"\r
 342         "       ldmia sp!, {r3, r14}                            \n"\r
 343         "                                                                               \n"     /* Restore the context, including the critical nesting count. */\r
 344         "       ldr r1, [r3]                                            \n"\r
 345         "       ldr r0, [r1]                                            \n" /* The first item in pxCurrentTCB is the task top of stack. */\r
 346         "       ldmia r0!, {r4-r11}                                     \n" /* Pop the registers. */\r
 347         "       msr psp, r0                                                     \n"\r
 348         "       bx r14                                                          \n"\r
 349         "                                                                               \n"\r
 350         "       .align 2                                                        \n"\r
 351         "pxCurrentTCBConst: .word pxCurrentTCB  \n"\r
 352         ::"i"(configMAX_SYSCALL_INTERRUPT_PRIORITY)\r
 353         );\r
 354 }\r
 355 /*-----------------------------------------------------------*/\r
 356 \r
 357 void xPortSysTickHandler( void )\r
 358 {\r
 359         /* The SysTick runs at the lowest interrupt priority, so when this interrupt\r
 360         executes all interrupts must be unmasked.  There is therefore no need to\r
 361         save and then restore the interrupt mask value as its value is already\r
 362         known. */\r
 363         ( void ) portSET_INTERRUPT_MASK_FROM_ISR();\r
 364         {\r
 365                 /* Increment the RTOS tick. */\r
 366                 if( xTaskIncrementTick() != pdFALSE )\r
 367                 {\r
 368                         /* A context switch is required.  Context switching is performed in\r
 369                         the PendSV interrupt.  Pend the PendSV interrupt. */\r
 370                         portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;\r
 371                 }\r
 372         }\r
 373         portCLEAR_INTERRUPT_MASK_FROM_ISR( 0 );\r
 374 }\r
 375 /*-----------------------------------------------------------*/\r
 376 \r
 377 #if configUSE_TICKLESS_IDLE == 1\r
 378 \r
 379         __attribute__((weak)) void vPortSuppressTicksAndSleep( portTickType xExpectedIdleTime )\r
 380         {\r
 381         unsigned long ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements;\r
 382         portTickType xModifiableIdleTime;\r
 383 \r
 384                 /* Make sure the SysTick reload value does not overflow the counter. */\r
 385                 if( xExpectedIdleTime > xMaximumPossibleSuppressedTicks )\r
 386                 {\r
 387                         xExpectedIdleTime = xMaximumPossibleSuppressedTicks;\r
 388                 }\r
 389 \r
 390                 /* Stop the SysTick momentarily.  The time the SysTick is stopped for\r
 391                 is accounted for as best it can be, but using the tickless mode will\r
 392                 inevitably result in some tiny drift of the time maintained by the\r
 393                 kernel with respect to calendar time. */\r
 394                 portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT;\r
 395 \r
 396                 /* Calculate the reload value required to wait xExpectedIdleTime\r
 397                 tick periods.  -1 is used because this code will execute part way\r
 398                 through one of the tick periods. */\r
 399                 ulReloadValue = portNVIC_SYSTICK_CURRENT_VALUE_REG + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) );\r
 400                 if( ulReloadValue > ulStoppedTimerCompensation )\r
 401                 {\r
 402                         ulReloadValue -= ulStoppedTimerCompensation;\r
 403                 }\r
 404 \r
 405                 /* Enter a critical section but don't use the taskENTER_CRITICAL()\r
 406                 method as that will mask interrupts that should exit sleep mode. */\r
 407                 __asm volatile( "cpsid i" );\r
 408 \r
 409                 /* If a context switch is pending or a task is waiting for the scheduler\r
 410                 to be unsuspended then abandon the low power entry. */\r
 411                 if( eTaskConfirmSleepModeStatus() == eAbortSleep )\r
 412                 {\r
 413                         /* Restart SysTick. */\r
 414                         portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;\r
 415 \r
 416                         /* Re-enable interrupts - see comments above the cpsid instruction()\r
 417                         above. */\r
 418                         __asm volatile( "cpsie i" );\r
 419                 }\r
 420                 else\r
 421                 {\r
 422                         /* Set the new reload value. */\r
 423                         portNVIC_SYSTICK_LOAD_REG = ulReloadValue;\r
 424 \r
 425                         /* Clear the SysTick count flag and set the count value back to\r
 426                         zero. */\r
 427                         portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;\r
 428 \r
 429                         /* Restart SysTick. */\r
 430                         portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;\r
 431 \r
 432                         /* Sleep until something happens.  configPRE_SLEEP_PROCESSING() can\r
 433                         set its parameter to 0 to indicate that its implementation contains\r
 434                         its own wait for interrupt or wait for event instruction, and so wfi\r
 435                         should not be executed again.  However, the original expected idle\r
 436                         time variable must remain unmodified, so a copy is taken. */\r
 437                         xModifiableIdleTime = xExpectedIdleTime;\r
 438                         configPRE_SLEEP_PROCESSING( xModifiableIdleTime );\r
 439                         if( xModifiableIdleTime > 0 )\r
 440                         {\r
 441                                 __asm volatile( "dsb" );\r
 442                                 __asm volatile( "wfi" );\r
 443                                 __asm volatile( "isb" );\r
 444                         }\r
 445                         configPOST_SLEEP_PROCESSING( xExpectedIdleTime );\r
 446 \r
 447                         /* Stop SysTick.  Again, the time the SysTick is stopped for is\r
 448                         accounted for as best it can be, but using the tickless mode will\r
 449                         inevitably result in some tiny drift of the time maintained by the\r
 450                         kernel with respect to calendar time. */\r
 451                         portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT;\r
 452 \r
 453                         /* Re-enable interrupts - see comments above the cpsid instruction()\r
 454                         above. */\r
 455                         __asm volatile( "cpsie i" );\r
 456 \r
 457                         if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 )\r
 458                         {\r
 459                                 /* The tick interrupt has already executed, and the SysTick\r
 460                                 count reloaded with ulReloadValue.  Reset the\r
 461                                 portNVIC_SYSTICK_LOAD_REG with whatever remains of this tick\r
 462                                 period. */\r
 463                                 portNVIC_SYSTICK_LOAD_REG = ( ulTimerCountsForOneTick - 1UL ) - ( ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG );\r
 464 \r
 465                                 /* The tick interrupt handler will already have pended the tick\r
 466                                 processing in the kernel.  As the pending tick will be\r
 467                                 processed as soon as this function exits, the tick value\r
 468                                 maintained by the tick is stepped forward by one less than the\r
 469                                 time spent waiting. */\r
 470                                 ulCompleteTickPeriods = xExpectedIdleTime - 1UL;\r
 471                         }\r
 472                         else\r
 473                         {\r
 474                                 /* Something other than the tick interrupt ended the sleep.\r
 475                                 Work out how long the sleep lasted rounded to complete tick\r
 476                                 periods (not the ulReload value which accounted for part\r
 477                                 ticks). */\r
 478                                 ulCompletedSysTickDecrements = ( xExpectedIdleTime * ulTimerCountsForOneTick ) - portNVIC_SYSTICK_CURRENT_VALUE_REG;\r
 479 \r
 480                                 /* How many complete tick periods passed while the processor\r
 481                                 was waiting? */\r
 482                                 ulCompleteTickPeriods = ulCompletedSysTickDecrements / ulTimerCountsForOneTick;\r
 483 \r
 484                                 /* The reload value is set to whatever fraction of a single tick\r
 485                                 period remains. */\r
 486                                 portNVIC_SYSTICK_LOAD_REG = ( ( ulCompleteTickPeriods + 1 ) * ulTimerCountsForOneTick ) - ulCompletedSysTickDecrements;\r
 487                         }\r
 488 \r
 489                         /* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG\r
 490                         again, then set portNVIC_SYSTICK_LOAD_REG back to its standard\r
 491                         value. */\r
 492                         portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;\r
 493                         portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;\r
 494 \r
 495                         vTaskStepTick( ulCompleteTickPeriods );\r
 496 \r
 497                         /* The counter must start by the time the reload value is reset. */\r
 498                         configASSERT( portNVIC_SYSTICK_CURRENT_VALUE_REG );\r
 499                         portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;\r
 500                 }\r
 501         }\r
 502 \r
 503 #endif /* #if configUSE_TICKLESS_IDLE */\r
 504 /*-----------------------------------------------------------*/\r
 505 \r
 506 /*\r
 507  * Setup the systick timer to generate the tick interrupts at the required\r
 508  * frequency.\r
 509  */\r
 510 __attribute__(( weak )) void vPortSetupTimerInterrupt( void )\r
 511 {\r
 512         /* Calculate the constants required to configure the tick interrupt. */\r
 513         #if configUSE_TICKLESS_IDLE == 1\r
 514         {\r
 515                 ulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ );\r
 516                 xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick;\r
 517                 ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ );\r
 518         }\r
 519         #endif /* configUSE_TICKLESS_IDLE */\r
 520 \r
 521         /* Configure SysTick to interrupt at the requested rate. */\r
 522         portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;;\r
 523         portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;\r
 524 }\r
 525 /*-----------------------------------------------------------*/\r
 526 \r