2 FreeRTOS V7.5.3 - Copyright (C) 2013 Real Time Engineers Ltd.
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5 VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
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7 ***************************************************************************
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9 * FreeRTOS provides completely free yet professionally developed, *
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10 * robust, strictly quality controlled, supported, and cross *
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11 * platform software that has become a de facto standard. *
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13 * Help yourself get started quickly and support the FreeRTOS *
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14 * project by purchasing a FreeRTOS tutorial book, reference *
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15 * manual, or both from: http://www.FreeRTOS.org/Documentation *
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19 ***************************************************************************
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21 This file is part of the FreeRTOS distribution.
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23 FreeRTOS is free software; you can redistribute it and/or modify it under
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24 the terms of the GNU General Public License (version 2) as published by the
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25 Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.
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27 >>! NOTE: The modification to the GPL is included to allow you to distribute
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28 >>! a combined work that includes FreeRTOS without being obliged to provide
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29 >>! the source code for proprietary components outside of the FreeRTOS
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32 FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
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33 WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
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34 FOR A PARTICULAR PURPOSE. Full license text is available from the following
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35 link: http://www.freertos.org/a00114.html
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39 ***************************************************************************
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41 * Having a problem? Start by reading the FAQ "My application does *
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42 * not run, what could be wrong?" *
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44 * http://www.FreeRTOS.org/FAQHelp.html *
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46 ***************************************************************************
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48 http://www.FreeRTOS.org - Documentation, books, training, latest versions,
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49 license and Real Time Engineers Ltd. contact details.
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51 http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
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52 including FreeRTOS+Trace - an indispensable productivity tool, a DOS
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53 compatible FAT file system, and our tiny thread aware UDP/IP stack.
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55 http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High
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56 Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS
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57 licenses offer ticketed support, indemnification and middleware.
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59 http://www.SafeRTOS.com - High Integrity Systems also provide a safety
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60 engineered and independently SIL3 certified version for use in safety and
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61 mission critical applications that require provable dependability.
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66 /*-----------------------------------------------------------
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67 * Implementation of functions defined in portable.h for the ARM CM3 port.
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68 *----------------------------------------------------------*/
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70 /* Scheduler includes. */
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71 #include "FreeRTOS.h"
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74 /* For backward compatibility, ensure configKERNEL_INTERRUPT_PRIORITY is
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75 defined. The value should also ensure backward compatibility.
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76 FreeRTOS.org versions prior to V4.4.0 did not include this definition. */
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77 #ifndef configKERNEL_INTERRUPT_PRIORITY
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78 #define configKERNEL_INTERRUPT_PRIORITY 255
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81 #ifndef configSYSTICK_CLOCK_HZ
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82 #define configSYSTICK_CLOCK_HZ configCPU_CLOCK_HZ
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85 /* Constants required to manipulate the core. Registers first... */
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86 #define portNVIC_SYSTICK_CTRL_REG ( * ( ( volatile unsigned long * ) 0xe000e010 ) )
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87 #define portNVIC_SYSTICK_LOAD_REG ( * ( ( volatile unsigned long * ) 0xe000e014 ) )
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88 #define portNVIC_SYSTICK_CURRENT_VALUE_REG ( * ( ( volatile unsigned long * ) 0xe000e018 ) )
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89 #define portNVIC_SYSPRI2_REG ( * ( ( volatile unsigned long * ) 0xe000ed20 ) )
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90 /* ...then bits in the registers. */
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91 #define portNVIC_SYSTICK_CLK_BIT ( 1UL << 2UL )
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92 #define portNVIC_SYSTICK_INT_BIT ( 1UL << 1UL )
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93 #define portNVIC_SYSTICK_ENABLE_BIT ( 1UL << 0UL )
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94 #define portNVIC_SYSTICK_COUNT_FLAG_BIT ( 1UL << 16UL )
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95 #define portNVIC_PENDSVCLEAR_BIT ( 1UL << 27UL )
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96 #define portNVIC_PEND_SYSTICK_CLEAR_BIT ( 1UL << 25UL )
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98 #define portNVIC_PENDSV_PRI ( ( ( unsigned long ) configKERNEL_INTERRUPT_PRIORITY ) << 16UL )
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99 #define portNVIC_SYSTICK_PRI ( ( ( unsigned long ) configKERNEL_INTERRUPT_PRIORITY ) << 24UL )
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101 /* Constants required to check the validity of an interrupt priority. */
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102 #define portFIRST_USER_INTERRUPT_NUMBER ( 16 )
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103 #define portNVIC_IP_REGISTERS_OFFSET_16 ( 0xE000E3F0 )
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104 #define portAIRCR_REG ( * ( ( volatile unsigned long * ) 0xE000ED0C ) )
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105 #define portMAX_8_BIT_VALUE ( ( unsigned char ) 0xff )
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106 #define portTOP_BIT_OF_BYTE ( ( unsigned char ) 0x80 )
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107 #define portMAX_PRIGROUP_BITS ( ( unsigned char ) 7 )
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108 #define portPRIORITY_GROUP_MASK ( 0x07UL << 8UL )
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109 #define portPRIGROUP_SHIFT ( 8UL )
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111 /* Constants required to set up the initial stack. */
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112 #define portINITIAL_XPSR ( 0x01000000UL )
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114 /* The systick is a 24-bit counter. */
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115 #define portMAX_24_BIT_NUMBER ( 0xffffffUL )
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117 /* A fiddle factor to estimate the number of SysTick counts that would have
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118 occurred while the SysTick counter is stopped during tickless idle
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120 #define portMISSED_COUNTS_FACTOR ( 45UL )
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122 /* Let the user override the pre-loading of the initial LR with the address of
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123 prvTaskExitError() in case is messes up unwinding of the stack in the
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125 #ifdef configTASK_RETURN_ADDRESS
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126 #define portTASK_RETURN_ADDRESS configTASK_RETURN_ADDRESS
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128 #define portTASK_RETURN_ADDRESS prvTaskExitError
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131 /* Each task maintains its own interrupt status in the critical nesting
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133 static unsigned portBASE_TYPE uxCriticalNesting = 0xaaaaaaaa;
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136 * Setup the timer to generate the tick interrupts. The implementation in this
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137 * file is weak to allow application writers to change the timer used to
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138 * generate the tick interrupt.
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140 void vPortSetupTimerInterrupt( void );
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143 * Exception handlers.
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145 void xPortPendSVHandler( void ) __attribute__ (( naked ));
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146 void xPortSysTickHandler( void );
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147 void vPortSVCHandler( void ) __attribute__ (( naked ));
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150 * Start first task is a separate function so it can be tested in isolation.
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152 static void prvPortStartFirstTask( void ) __attribute__ (( naked ));
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155 * Used to catch tasks that attempt to return from their implementing function.
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157 static void prvTaskExitError( void );
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159 /*-----------------------------------------------------------*/
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162 * The number of SysTick increments that make up one tick period.
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164 #if configUSE_TICKLESS_IDLE == 1
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165 static unsigned long ulTimerCountsForOneTick = 0;
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166 #endif /* configUSE_TICKLESS_IDLE */
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169 * The maximum number of tick periods that can be suppressed is limited by the
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170 * 24 bit resolution of the SysTick timer.
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172 #if configUSE_TICKLESS_IDLE == 1
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173 static unsigned long xMaximumPossibleSuppressedTicks = 0;
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174 #endif /* configUSE_TICKLESS_IDLE */
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177 * Compensate for the CPU cycles that pass while the SysTick is stopped (low
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178 * power functionality only.
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180 #if configUSE_TICKLESS_IDLE == 1
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181 static unsigned long ulStoppedTimerCompensation = 0;
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182 #endif /* configUSE_TICKLESS_IDLE */
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185 * Used by the portASSERT_IF_INTERRUPT_PRIORITY_INVALID() macro to ensure
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186 * FreeRTOS API functions are not called from interrupts that have been assigned
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187 * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY.
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189 #if ( configASSERT_DEFINED == 1 )
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190 static unsigned char ucMaxSysCallPriority = 0;
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191 static unsigned long ulMaxPRIGROUPValue = 0;
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192 static const volatile unsigned char * const pcInterruptPriorityRegisters = ( const volatile unsigned char * const ) portNVIC_IP_REGISTERS_OFFSET_16;
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193 #endif /* configASSERT_DEFINED */
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195 /*-----------------------------------------------------------*/
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198 * See header file for description.
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200 portSTACK_TYPE *pxPortInitialiseStack( portSTACK_TYPE *pxTopOfStack, pdTASK_CODE pxCode, void *pvParameters )
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202 /* Simulate the stack frame as it would be created by a context switch
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204 pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
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205 *pxTopOfStack = portINITIAL_XPSR; /* xPSR */
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207 *pxTopOfStack = ( portSTACK_TYPE ) pxCode; /* PC */
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209 *pxTopOfStack = ( portSTACK_TYPE ) portTASK_RETURN_ADDRESS; /* LR */
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210 pxTopOfStack -= 5; /* R12, R3, R2 and R1. */
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211 *pxTopOfStack = ( portSTACK_TYPE ) pvParameters; /* R0 */
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212 pxTopOfStack -= 8; /* R11, R10, R9, R8, R7, R6, R5 and R4. */
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214 return pxTopOfStack;
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216 /*-----------------------------------------------------------*/
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218 static void prvTaskExitError( void )
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220 /* A function that implements a task must not exit or attempt to return to
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221 its caller as there is nothing to return to. If a task wants to exit it
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222 should instead call vTaskDelete( NULL ).
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224 Artificially force an assert() to be triggered if configASSERT() is
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225 defined, then stop here so application writers can catch the error. */
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226 configASSERT( uxCriticalNesting == ~0UL );
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227 portDISABLE_INTERRUPTS();
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230 /*-----------------------------------------------------------*/
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232 void vPortSVCHandler( void )
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235 " ldr r3, pxCurrentTCBConst2 \n" /* Restore the context. */
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236 " ldr r1, [r3] \n" /* Use pxCurrentTCBConst to get the pxCurrentTCB address. */
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237 " ldr r0, [r1] \n" /* The first item in pxCurrentTCB is the task top of stack. */
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238 " ldmia r0!, {r4-r11} \n" /* Pop the registers that are not automatically saved on exception entry and the critical nesting count. */
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239 " msr psp, r0 \n" /* Restore the task stack pointer. */
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241 " msr basepri, r0 \n"
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242 " orr r14, #0xd \n"
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246 "pxCurrentTCBConst2: .word pxCurrentTCB \n"
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249 /*-----------------------------------------------------------*/
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251 static void prvPortStartFirstTask( void )
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254 " ldr r0, =0xE000ED08 \n" /* Use the NVIC offset register to locate the stack. */
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257 " msr msp, r0 \n" /* Set the msp back to the start of the stack. */
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258 " cpsie i \n" /* Globally enable interrupts. */
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259 " svc 0 \n" /* System call to start first task. */
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263 /*-----------------------------------------------------------*/
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266 * See header file for description.
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268 portBASE_TYPE xPortStartScheduler( void )
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270 /* configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0.
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271 See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
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272 configASSERT( configMAX_SYSCALL_INTERRUPT_PRIORITY );
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274 #if( configASSERT_DEFINED == 1 )
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276 volatile unsigned long ulOriginalPriority;
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277 volatile char * const pcFirstUserPriorityRegister = ( volatile char * const ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER );
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278 volatile unsigned char ucMaxPriorityValue;
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280 /* Determine the maximum priority from which ISR safe FreeRTOS API
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281 functions can be called. ISR safe functions are those that end in
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282 "FromISR". FreeRTOS maintains separate thread and ISR API functions to
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283 ensure interrupt entry is as fast and simple as possible.
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285 Save the interrupt priority value that is about to be clobbered. */
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286 ulOriginalPriority = *pcFirstUserPriorityRegister;
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288 /* Determine the number of priority bits available. First write to all
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290 *pcFirstUserPriorityRegister = portMAX_8_BIT_VALUE;
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292 /* Read the value back to see how many bits stuck. */
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293 ucMaxPriorityValue = *pcFirstUserPriorityRegister;
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295 /* Use the same mask on the maximum system call priority. */
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296 ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;
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298 /* Calculate the maximum acceptable priority group value for the number
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299 of bits read back. */
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300 ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS;
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301 while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )
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303 ulMaxPRIGROUPValue--;
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304 ucMaxPriorityValue <<= ( unsigned char ) 0x01;
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307 /* Shift the priority group value back to its position within the AIRCR
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309 ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;
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310 ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK;
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312 /* Restore the clobbered interrupt priority register to its original
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314 *pcFirstUserPriorityRegister = ulOriginalPriority;
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316 #endif /* conifgASSERT_DEFINED */
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318 /* Make PendSV and SysTick the lowest priority interrupts. */
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319 portNVIC_SYSPRI2_REG |= portNVIC_PENDSV_PRI;
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320 portNVIC_SYSPRI2_REG |= portNVIC_SYSTICK_PRI;
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322 /* Start the timer that generates the tick ISR. Interrupts are disabled
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324 vPortSetupTimerInterrupt();
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326 /* Initialise the critical nesting count ready for the first task. */
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327 uxCriticalNesting = 0;
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329 /* Start the first task. */
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330 prvPortStartFirstTask();
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332 /* Should not get here! */
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335 /*-----------------------------------------------------------*/
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337 void vPortEndScheduler( void )
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339 /* It is unlikely that the CM3 port will require this function as there
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340 is nothing to return to. */
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342 /*-----------------------------------------------------------*/
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344 void vPortYield( void )
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346 /* Set a PendSV to request a context switch. */
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347 portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
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349 /* Barriers are normally not required but do ensure the code is completely
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350 within the specified behaviour for the architecture. */
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351 __asm volatile( "dsb" );
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352 __asm volatile( "isb" );
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354 /*-----------------------------------------------------------*/
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356 void vPortEnterCritical( void )
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358 portDISABLE_INTERRUPTS();
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359 uxCriticalNesting++;
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360 __asm volatile( "dsb" );
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361 __asm volatile( "isb" );
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363 /*-----------------------------------------------------------*/
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365 void vPortExitCritical( void )
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367 uxCriticalNesting--;
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368 if( uxCriticalNesting == 0 )
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370 portENABLE_INTERRUPTS();
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373 /*-----------------------------------------------------------*/
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375 __attribute__(( naked )) unsigned long ulPortSetInterruptMask( void )
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379 " mrs r0, basepri \n" \
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381 " msr basepri, r1 \n" \
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383 :: "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "r0", "r1" \
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386 /* This return will not be reached but is necessary to prevent compiler
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390 /*-----------------------------------------------------------*/
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392 __attribute__(( naked )) void vPortClearInterruptMask( unsigned long ulNewMaskValue )
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396 " msr basepri, r0 \n" \
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401 /* Just to avoid compiler warnings. */
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402 ( void ) ulNewMaskValue;
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404 /*-----------------------------------------------------------*/
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406 void xPortPendSVHandler( void )
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408 /* This is a naked function. */
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414 " ldr r3, pxCurrentTCBConst \n" /* Get the location of the current TCB. */
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417 " stmdb r0!, {r4-r11} \n" /* Save the remaining registers. */
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418 " str r0, [r2] \n" /* Save the new top of stack into the first member of the TCB. */
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420 " stmdb sp!, {r3, r14} \n"
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422 " msr basepri, r0 \n"
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423 " bl vTaskSwitchContext \n"
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425 " msr basepri, r0 \n"
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426 " ldmia sp!, {r3, r14} \n"
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427 " \n" /* Restore the context, including the critical nesting count. */
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429 " ldr r0, [r1] \n" /* The first item in pxCurrentTCB is the task top of stack. */
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430 " ldmia r0!, {r4-r11} \n" /* Pop the registers. */
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435 "pxCurrentTCBConst: .word pxCurrentTCB \n"
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436 ::"i"(configMAX_SYSCALL_INTERRUPT_PRIORITY)
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439 /*-----------------------------------------------------------*/
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441 void xPortSysTickHandler( void )
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443 /* The SysTick runs at the lowest interrupt priority, so when this interrupt
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444 executes all interrupts must be unmasked. There is therefore no need to
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445 save and then restore the interrupt mask value as its value is already
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447 ( void ) portSET_INTERRUPT_MASK_FROM_ISR();
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449 /* Increment the RTOS tick. */
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450 if( xTaskIncrementTick() != pdFALSE )
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452 /* A context switch is required. Context switching is performed in
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453 the PendSV interrupt. Pend the PendSV interrupt. */
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454 portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
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457 portCLEAR_INTERRUPT_MASK_FROM_ISR( 0 );
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459 /*-----------------------------------------------------------*/
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461 #if configUSE_TICKLESS_IDLE == 1
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463 __attribute__((weak)) void vPortSuppressTicksAndSleep( portTickType xExpectedIdleTime )
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465 unsigned long ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements;
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466 portTickType xModifiableIdleTime;
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468 /* Make sure the SysTick reload value does not overflow the counter. */
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469 if( xExpectedIdleTime > xMaximumPossibleSuppressedTicks )
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471 xExpectedIdleTime = xMaximumPossibleSuppressedTicks;
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474 /* Stop the SysTick momentarily. The time the SysTick is stopped for
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475 is accounted for as best it can be, but using the tickless mode will
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476 inevitably result in some tiny drift of the time maintained by the
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477 kernel with respect to calendar time. */
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478 portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT;
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480 /* Calculate the reload value required to wait xExpectedIdleTime
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481 tick periods. -1 is used because this code will execute part way
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482 through one of the tick periods. */
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483 ulReloadValue = portNVIC_SYSTICK_CURRENT_VALUE_REG + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) );
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484 if( ulReloadValue > ulStoppedTimerCompensation )
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486 ulReloadValue -= ulStoppedTimerCompensation;
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489 /* Enter a critical section but don't use the taskENTER_CRITICAL()
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490 method as that will mask interrupts that should exit sleep mode. */
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491 __asm volatile( "cpsid i" );
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493 /* If a context switch is pending or a task is waiting for the scheduler
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494 to be unsuspended then abandon the low power entry. */
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495 if( eTaskConfirmSleepModeStatus() == eAbortSleep )
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497 /* Restart from whatever is left in the count register to complete
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498 this tick period. */
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499 portNVIC_SYSTICK_LOAD_REG = portNVIC_SYSTICK_CURRENT_VALUE_REG;
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501 /* Restart SysTick. */
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502 portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;
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504 /* Reset the reload register to the value required for normal tick
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506 portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
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508 /* Re-enable interrupts - see comments above the cpsid instruction()
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510 __asm volatile( "cpsie i" );
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514 /* Set the new reload value. */
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515 portNVIC_SYSTICK_LOAD_REG = ulReloadValue;
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517 /* Clear the SysTick count flag and set the count value back to
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519 portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
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521 /* Restart SysTick. */
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522 portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;
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524 /* Sleep until something happens. configPRE_SLEEP_PROCESSING() can
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525 set its parameter to 0 to indicate that its implementation contains
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526 its own wait for interrupt or wait for event instruction, and so wfi
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527 should not be executed again. However, the original expected idle
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528 time variable must remain unmodified, so a copy is taken. */
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529 xModifiableIdleTime = xExpectedIdleTime;
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530 configPRE_SLEEP_PROCESSING( xModifiableIdleTime );
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531 if( xModifiableIdleTime > 0 )
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533 __asm volatile( "dsb" );
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534 __asm volatile( "wfi" );
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535 __asm volatile( "isb" );
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537 configPOST_SLEEP_PROCESSING( xExpectedIdleTime );
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539 /* Stop SysTick. Again, the time the SysTick is stopped for is
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540 accounted for as best it can be, but using the tickless mode will
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541 inevitably result in some tiny drift of the time maintained by the
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542 kernel with respect to calendar time. */
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543 portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT;
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545 /* Re-enable interrupts - see comments above the cpsid instruction()
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547 __asm volatile( "cpsie i" );
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549 if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 )
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551 unsigned long ulCalculatedLoadValue;
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553 /* The tick interrupt has already executed, and the SysTick
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554 count reloaded with ulReloadValue. Reset the
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555 portNVIC_SYSTICK_LOAD_REG with whatever remains of this tick
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557 ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ) - ( ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG );
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559 /* Don't allow a tiny value, or values that have somehow
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560 underflowed because the post sleep hook did something
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561 that took too long. */
\r
562 if( ( ulCalculatedLoadValue < ulStoppedTimerCompensation ) || ( ulCalculatedLoadValue > ulTimerCountsForOneTick ) )
\r
564 ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL );
\r
567 portNVIC_SYSTICK_LOAD_REG = ulCalculatedLoadValue;
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569 /* The tick interrupt handler will already have pended the tick
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570 processing in the kernel. As the pending tick will be
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571 processed as soon as this function exits, the tick value
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572 maintained by the tick is stepped forward by one less than the
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573 time spent waiting. */
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574 ulCompleteTickPeriods = xExpectedIdleTime - 1UL;
\r
578 /* Something other than the tick interrupt ended the sleep.
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579 Work out how long the sleep lasted rounded to complete tick
\r
580 periods (not the ulReload value which accounted for part
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582 ulCompletedSysTickDecrements = ( xExpectedIdleTime * ulTimerCountsForOneTick ) - portNVIC_SYSTICK_CURRENT_VALUE_REG;
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584 /* How many complete tick periods passed while the processor
\r
586 ulCompleteTickPeriods = ulCompletedSysTickDecrements / ulTimerCountsForOneTick;
\r
588 /* The reload value is set to whatever fraction of a single tick
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590 portNVIC_SYSTICK_LOAD_REG = ( ( ulCompleteTickPeriods + 1 ) * ulTimerCountsForOneTick ) - ulCompletedSysTickDecrements;
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593 /* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG
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594 again, then set portNVIC_SYSTICK_LOAD_REG back to its standard
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595 value. The critical section is used to ensure the tick interrupt
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596 can only execute once in the case that the reload register is near
\r
598 portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
\r
599 portENTER_CRITICAL();
\r
601 portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;
\r
602 vTaskStepTick( ulCompleteTickPeriods );
\r
603 portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
\r
605 portEXIT_CRITICAL();
\r
609 #endif /* #if configUSE_TICKLESS_IDLE */
\r
610 /*-----------------------------------------------------------*/
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613 * Setup the systick timer to generate the tick interrupts at the required
\r
616 __attribute__(( weak )) void vPortSetupTimerInterrupt( void )
\r
618 /* Calculate the constants required to configure the tick interrupt. */
\r
619 #if configUSE_TICKLESS_IDLE == 1
\r
621 ulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ );
\r
622 xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick;
\r
623 ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ );
\r
625 #endif /* configUSE_TICKLESS_IDLE */
\r
627 /* Configure SysTick to interrupt at the requested rate. */
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628 portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;;
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629 portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;
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631 /*-----------------------------------------------------------*/
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633 #if( configASSERT_DEFINED == 1 )
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635 void vPortValidateInterruptPriority( void )
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637 unsigned long ulCurrentInterrupt;
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638 unsigned char ucCurrentPriority;
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640 /* Obtain the number of the currently executing interrupt. */
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641 __asm volatile( "mrs %0, ipsr" : "=r"( ulCurrentInterrupt ) );
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643 /* Is the interrupt number a user defined interrupt? */
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644 if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER )
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646 /* Look up the interrupt's priority. */
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647 ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ];
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649 /* The following assertion will fail if a service routine (ISR) for
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650 an interrupt that has been assigned a priority above
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651 configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API
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652 function. ISR safe FreeRTOS API functions must *only* be called
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653 from interrupts that have been assigned a priority at or below
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654 configMAX_SYSCALL_INTERRUPT_PRIORITY.
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656 Numerically low interrupt priority numbers represent logically high
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657 interrupt priorities, therefore the priority of the interrupt must
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658 be set to a value equal to or numerically *higher* than
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659 configMAX_SYSCALL_INTERRUPT_PRIORITY.
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661 Interrupts that use the FreeRTOS API must not be left at their
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662 default priority of zero as that is the highest possible priority,
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663 which is guaranteed to be above configMAX_SYSCALL_INTERRUPT_PRIORITY,
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664 and therefore also guaranteed to be invalid.
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666 FreeRTOS maintains separate thread and ISR API functions to ensure
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667 interrupt entry is as fast and simple as possible.
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669 The following links provide detailed information:
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670 http://www.freertos.org/RTOS-Cortex-M3-M4.html
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671 http://www.freertos.org/FAQHelp.html */
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672 configASSERT( ucCurrentPriority >= ucMaxSysCallPriority );
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675 /* Priority grouping: The interrupt controller (NVIC) allows the bits
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676 that define each interrupt's priority to be split between bits that
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677 define the interrupt's pre-emption priority bits and bits that define
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678 the interrupt's sub-priority. For simplicity all bits must be defined
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679 to be pre-emption priority bits. The following assertion will fail if
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680 this is not the case (if some bits represent a sub-priority).
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682 If the application only uses CMSIS libraries for interrupt
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683 configuration then the correct setting can be achieved on all Cortex-M
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684 devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the
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685 scheduler. Note however that some vendor specific peripheral libraries
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686 assume a non-zero priority group setting, in which cases using a value
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687 of zero will result in unpredicable behaviour. */
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688 configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue );
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691 #endif /* configASSERT_DEFINED */
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