2 FreeRTOS V9.0.1 - Copyright (C) 2017 Real Time Engineers Ltd.
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5 VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
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7 This file is part of the FreeRTOS distribution.
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9 FreeRTOS is free software; you can redistribute it and/or modify it under
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10 the terms of the GNU General Public License (version 2) as published by the
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11 Free Software Foundation >>>> AND MODIFIED BY <<<< the FreeRTOS exception.
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13 ***************************************************************************
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14 >>! NOTE: The modification to the GPL is included to allow you to !<<
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15 >>! distribute a combined work that includes FreeRTOS without being !<<
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16 >>! obliged to provide the source code for proprietary components !<<
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17 >>! outside of the FreeRTOS kernel. !<<
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18 ***************************************************************************
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20 FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
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21 WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
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22 FOR A PARTICULAR PURPOSE. Full license text is available on the following
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23 link: http://www.freertos.org/a00114.html
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25 ***************************************************************************
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27 * FreeRTOS provides completely free yet professionally developed, *
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28 * robust, strictly quality controlled, supported, and cross *
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29 * platform software that is more than just the market leader, it *
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30 * is the industry's de facto standard. *
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32 * Help yourself get started quickly while simultaneously helping *
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33 * to support the FreeRTOS project by purchasing a FreeRTOS *
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34 * tutorial book, reference manual, or both: *
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35 * http://www.FreeRTOS.org/Documentation *
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37 ***************************************************************************
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39 http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading
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40 the FAQ page "My application does not run, what could be wrong?". Have you
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41 defined configASSERT()?
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43 http://www.FreeRTOS.org/support - In return for receiving this top quality
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44 embedded software for free we request you assist our global community by
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45 participating in the support forum.
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47 http://www.FreeRTOS.org/training - Investing in training allows your team to
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48 be as productive as possible as early as possible. Now you can receive
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49 FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers
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50 Ltd, and the world's leading authority on the world's leading RTOS.
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52 http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
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53 including FreeRTOS+Trace - an indispensable productivity tool, a DOS
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54 compatible FAT file system, and our tiny thread aware UDP/IP stack.
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56 http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.
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57 Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.
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59 http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High
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60 Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS
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61 licenses offer ticketed support, indemnification and commercial middleware.
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63 http://www.SafeRTOS.com - High Integrity Systems also provide a safety
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64 engineered and independently SIL3 certified version for use in safety and
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65 mission critical applications that require provable dependability.
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70 /*-----------------------------------------------------------
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71 * Implementation of functions defined in portable.h for the ARM CM3 port.
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72 *----------------------------------------------------------*/
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74 /* Scheduler includes. */
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75 #include "FreeRTOS.h"
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78 /* For backward compatibility, ensure configKERNEL_INTERRUPT_PRIORITY is
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79 defined. The value should also ensure backward compatibility.
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80 FreeRTOS.org versions prior to V4.4.0 did not include this definition. */
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81 #ifndef configKERNEL_INTERRUPT_PRIORITY
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82 #define configKERNEL_INTERRUPT_PRIORITY 255
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85 #ifndef configSYSTICK_CLOCK_HZ
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86 #define configSYSTICK_CLOCK_HZ configCPU_CLOCK_HZ
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87 /* Ensure the SysTick is clocked at the same frequency as the core. */
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88 #define portNVIC_SYSTICK_CLK_BIT ( 1UL << 2UL )
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90 /* The way the SysTick is clocked is not modified in case it is not the same
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92 #define portNVIC_SYSTICK_CLK_BIT ( 0 )
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95 /* Constants required to manipulate the core. Registers first... */
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96 #define portNVIC_SYSTICK_CTRL_REG ( * ( ( volatile uint32_t * ) 0xe000e010 ) )
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97 #define portNVIC_SYSTICK_LOAD_REG ( * ( ( volatile uint32_t * ) 0xe000e014 ) )
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98 #define portNVIC_SYSTICK_CURRENT_VALUE_REG ( * ( ( volatile uint32_t * ) 0xe000e018 ) )
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99 #define portNVIC_SYSPRI2_REG ( * ( ( volatile uint32_t * ) 0xe000ed20 ) )
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100 /* ...then bits in the registers. */
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101 #define portNVIC_SYSTICK_INT_BIT ( 1UL << 1UL )
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102 #define portNVIC_SYSTICK_ENABLE_BIT ( 1UL << 0UL )
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103 #define portNVIC_SYSTICK_COUNT_FLAG_BIT ( 1UL << 16UL )
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104 #define portNVIC_PENDSVCLEAR_BIT ( 1UL << 27UL )
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105 #define portNVIC_PEND_SYSTICK_CLEAR_BIT ( 1UL << 25UL )
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107 #define portNVIC_PENDSV_PRI ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 16UL )
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108 #define portNVIC_SYSTICK_PRI ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 24UL )
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110 /* Constants required to check the validity of an interrupt priority. */
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111 #define portFIRST_USER_INTERRUPT_NUMBER ( 16 )
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112 #define portNVIC_IP_REGISTERS_OFFSET_16 ( 0xE000E3F0 )
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113 #define portAIRCR_REG ( * ( ( volatile uint32_t * ) 0xE000ED0C ) )
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114 #define portMAX_8_BIT_VALUE ( ( uint8_t ) 0xff )
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115 #define portTOP_BIT_OF_BYTE ( ( uint8_t ) 0x80 )
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116 #define portMAX_PRIGROUP_BITS ( ( uint8_t ) 7 )
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117 #define portPRIORITY_GROUP_MASK ( 0x07UL << 8UL )
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118 #define portPRIGROUP_SHIFT ( 8UL )
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120 /* Masks off all bits but the VECTACTIVE bits in the ICSR register. */
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121 #define portVECTACTIVE_MASK ( 0xFFUL )
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123 /* Constants required to set up the initial stack. */
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124 #define portINITIAL_XPSR ( 0x01000000UL )
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126 /* The systick is a 24-bit counter. */
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127 #define portMAX_24_BIT_NUMBER ( 0xffffffUL )
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129 /* A fiddle factor to estimate the number of SysTick counts that would have
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130 occurred while the SysTick counter is stopped during tickless idle
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132 #define portMISSED_COUNTS_FACTOR ( 45UL )
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134 /* For strict compliance with the Cortex-M spec the task start address should
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135 have bit-0 clear, as it is loaded into the PC on exit from an ISR. */
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136 #define portSTART_ADDRESS_MASK ( ( StackType_t ) 0xfffffffeUL )
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138 /* Let the user override the pre-loading of the initial LR with the address of
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139 prvTaskExitError() in case it messes up unwinding of the stack in the
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141 #ifdef configTASK_RETURN_ADDRESS
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142 #define portTASK_RETURN_ADDRESS configTASK_RETURN_ADDRESS
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144 #define portTASK_RETURN_ADDRESS prvTaskExitError
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147 /* Each task maintains its own interrupt status in the critical nesting
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149 static UBaseType_t uxCriticalNesting = 0xaaaaaaaa;
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152 * Setup the timer to generate the tick interrupts. The implementation in this
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153 * file is weak to allow application writers to change the timer used to
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154 * generate the tick interrupt.
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156 void vPortSetupTimerInterrupt( void );
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159 * Exception handlers.
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161 void xPortPendSVHandler( void ) __attribute__ (( naked ));
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162 void xPortSysTickHandler( void );
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163 void vPortSVCHandler( void ) __attribute__ (( naked ));
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166 * Start first task is a separate function so it can be tested in isolation.
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168 static void prvPortStartFirstTask( void ) __attribute__ (( naked ));
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171 * Used to catch tasks that attempt to return from their implementing function.
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173 static void prvTaskExitError( void );
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175 /*-----------------------------------------------------------*/
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178 * The number of SysTick increments that make up one tick period.
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180 #if configUSE_TICKLESS_IDLE == 1
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181 static uint32_t ulTimerCountsForOneTick = 0;
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182 #endif /* configUSE_TICKLESS_IDLE */
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185 * The maximum number of tick periods that can be suppressed is limited by the
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186 * 24 bit resolution of the SysTick timer.
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188 #if configUSE_TICKLESS_IDLE == 1
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189 static uint32_t xMaximumPossibleSuppressedTicks = 0;
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190 #endif /* configUSE_TICKLESS_IDLE */
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193 * Compensate for the CPU cycles that pass while the SysTick is stopped (low
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194 * power functionality only.
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196 #if configUSE_TICKLESS_IDLE == 1
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197 static uint32_t ulStoppedTimerCompensation = 0;
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198 #endif /* configUSE_TICKLESS_IDLE */
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201 * Used by the portASSERT_IF_INTERRUPT_PRIORITY_INVALID() macro to ensure
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202 * FreeRTOS API functions are not called from interrupts that have been assigned
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203 * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY.
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205 #if ( configASSERT_DEFINED == 1 )
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206 static uint8_t ucMaxSysCallPriority = 0;
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207 static uint32_t ulMaxPRIGROUPValue = 0;
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208 static const volatile uint8_t * const pcInterruptPriorityRegisters = ( const volatile uint8_t * const ) portNVIC_IP_REGISTERS_OFFSET_16;
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209 #endif /* configASSERT_DEFINED */
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211 /*-----------------------------------------------------------*/
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214 * See header file for description.
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216 StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
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218 /* Simulate the stack frame as it would be created by a context switch
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220 pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
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221 *pxTopOfStack = portINITIAL_XPSR; /* xPSR */
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223 *pxTopOfStack = ( ( StackType_t ) pxCode ) & portSTART_ADDRESS_MASK; /* PC */
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225 *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR */
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226 pxTopOfStack -= 5; /* R12, R3, R2 and R1. */
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227 *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
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228 pxTopOfStack -= 8; /* R11, R10, R9, R8, R7, R6, R5 and R4. */
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230 return pxTopOfStack;
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232 /*-----------------------------------------------------------*/
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234 static void prvTaskExitError( void )
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236 /* A function that implements a task must not exit or attempt to return to
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237 its caller as there is nothing to return to. If a task wants to exit it
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238 should instead call vTaskDelete( NULL ).
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240 Artificially force an assert() to be triggered if configASSERT() is
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241 defined, then stop here so application writers can catch the error. */
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242 configASSERT( uxCriticalNesting == ~0UL );
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243 portDISABLE_INTERRUPTS();
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246 /*-----------------------------------------------------------*/
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248 void vPortSVCHandler( void )
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251 " ldr r3, pxCurrentTCBConst2 \n" /* Restore the context. */
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252 " ldr r1, [r3] \n" /* Use pxCurrentTCBConst to get the pxCurrentTCB address. */
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253 " ldr r0, [r1] \n" /* The first item in pxCurrentTCB is the task top of stack. */
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254 " ldmia r0!, {r4-r11} \n" /* Pop the registers that are not automatically saved on exception entry and the critical nesting count. */
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255 " msr psp, r0 \n" /* Restore the task stack pointer. */
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258 " msr basepri, r0 \n"
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259 " orr r14, #0xd \n"
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263 "pxCurrentTCBConst2: .word pxCurrentTCB \n"
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266 /*-----------------------------------------------------------*/
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268 static void prvPortStartFirstTask( void )
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271 " ldr r0, =0xE000ED08 \n" /* Use the NVIC offset register to locate the stack. */
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274 " msr msp, r0 \n" /* Set the msp back to the start of the stack. */
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275 " cpsie i \n" /* Globally enable interrupts. */
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279 " svc 0 \n" /* System call to start first task. */
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283 /*-----------------------------------------------------------*/
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286 * See header file for description.
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288 BaseType_t xPortStartScheduler( void )
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290 /* configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0.
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291 See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
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292 configASSERT( configMAX_SYSCALL_INTERRUPT_PRIORITY );
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294 #if( configASSERT_DEFINED == 1 )
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296 volatile uint32_t ulOriginalPriority;
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297 volatile uint8_t * const pucFirstUserPriorityRegister = ( volatile uint8_t * const ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER );
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298 volatile uint8_t ucMaxPriorityValue;
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300 /* Determine the maximum priority from which ISR safe FreeRTOS API
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301 functions can be called. ISR safe functions are those that end in
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302 "FromISR". FreeRTOS maintains separate thread and ISR API functions to
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303 ensure interrupt entry is as fast and simple as possible.
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305 Save the interrupt priority value that is about to be clobbered. */
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306 ulOriginalPriority = *pucFirstUserPriorityRegister;
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308 /* Determine the number of priority bits available. First write to all
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310 *pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE;
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312 /* Read the value back to see how many bits stuck. */
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313 ucMaxPriorityValue = *pucFirstUserPriorityRegister;
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315 /* Use the same mask on the maximum system call priority. */
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316 ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;
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318 /* Calculate the maximum acceptable priority group value for the number
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319 of bits read back. */
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320 ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS;
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321 while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )
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323 ulMaxPRIGROUPValue--;
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324 ucMaxPriorityValue <<= ( uint8_t ) 0x01;
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327 #ifdef __NVIC_PRIO_BITS
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329 /* Check the CMSIS configuration that defines the number of
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330 priority bits matches the number of priority bits actually queried
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331 from the hardware. */
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332 configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == __NVIC_PRIO_BITS );
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336 #ifdef configPRIO_BITS
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338 /* Check the FreeRTOS configuration that defines the number of
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339 priority bits matches the number of priority bits actually queried
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340 from the hardware. */
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341 configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == configPRIO_BITS );
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345 /* Shift the priority group value back to its position within the AIRCR
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347 ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;
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348 ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK;
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350 /* Restore the clobbered interrupt priority register to its original
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352 *pucFirstUserPriorityRegister = ulOriginalPriority;
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354 #endif /* conifgASSERT_DEFINED */
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356 /* Make PendSV and SysTick the lowest priority interrupts. */
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357 portNVIC_SYSPRI2_REG |= portNVIC_PENDSV_PRI;
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358 portNVIC_SYSPRI2_REG |= portNVIC_SYSTICK_PRI;
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360 /* Start the timer that generates the tick ISR. Interrupts are disabled
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362 vPortSetupTimerInterrupt();
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364 /* Initialise the critical nesting count ready for the first task. */
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365 uxCriticalNesting = 0;
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367 /* Start the first task. */
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368 prvPortStartFirstTask();
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370 /* Should never get here as the tasks will now be executing! Call the task
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371 exit error function to prevent compiler warnings about a static function
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372 not being called in the case that the application writer overrides this
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373 functionality by defining configTASK_RETURN_ADDRESS. */
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374 prvTaskExitError();
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376 /* Should not get here! */
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379 /*-----------------------------------------------------------*/
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381 void vPortEndScheduler( void )
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383 /* Not implemented in ports where there is nothing to return to.
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384 Artificially force an assert. */
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385 configASSERT( uxCriticalNesting == 1000UL );
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387 /*-----------------------------------------------------------*/
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389 void vPortEnterCritical( void )
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391 portDISABLE_INTERRUPTS();
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392 uxCriticalNesting++;
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394 /* This is not the interrupt safe version of the enter critical function so
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395 assert() if it is being called from an interrupt context. Only API
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396 functions that end in "FromISR" can be used in an interrupt. Only assert if
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397 the critical nesting count is 1 to protect against recursive calls if the
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398 assert function also uses a critical section. */
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399 if( uxCriticalNesting == 1 )
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401 configASSERT( ( portNVIC_INT_CTRL_REG & portVECTACTIVE_MASK ) == 0 );
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404 /*-----------------------------------------------------------*/
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406 void vPortExitCritical( void )
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408 configASSERT( uxCriticalNesting );
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409 uxCriticalNesting--;
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410 if( uxCriticalNesting == 0 )
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412 portENABLE_INTERRUPTS();
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415 /*-----------------------------------------------------------*/
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417 void xPortPendSVHandler( void )
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419 /* This is a naked function. */
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426 " ldr r3, pxCurrentTCBConst \n" /* Get the location of the current TCB. */
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429 " stmdb r0!, {r4-r11} \n" /* Save the remaining registers. */
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430 " str r0, [r2] \n" /* Save the new top of stack into the first member of the TCB. */
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432 " stmdb sp!, {r3, r14} \n"
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434 " msr basepri, r0 \n"
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435 " bl vTaskSwitchContext \n"
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437 " msr basepri, r0 \n"
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438 " ldmia sp!, {r3, r14} \n"
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439 " \n" /* Restore the context, including the critical nesting count. */
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441 " ldr r0, [r1] \n" /* The first item in pxCurrentTCB is the task top of stack. */
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442 " ldmia r0!, {r4-r11} \n" /* Pop the registers. */
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448 "pxCurrentTCBConst: .word pxCurrentTCB \n"
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449 ::"i"(configMAX_SYSCALL_INTERRUPT_PRIORITY)
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452 /*-----------------------------------------------------------*/
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454 void xPortSysTickHandler( void )
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456 /* The SysTick runs at the lowest interrupt priority, so when this interrupt
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457 executes all interrupts must be unmasked. There is therefore no need to
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458 save and then restore the interrupt mask value as its value is already
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460 portDISABLE_INTERRUPTS();
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462 /* Increment the RTOS tick. */
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463 if( xTaskIncrementTick() != pdFALSE )
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465 /* A context switch is required. Context switching is performed in
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466 the PendSV interrupt. Pend the PendSV interrupt. */
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467 portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
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470 portENABLE_INTERRUPTS();
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472 /*-----------------------------------------------------------*/
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474 #if configUSE_TICKLESS_IDLE == 1
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476 __attribute__((weak)) void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime )
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478 uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements;
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479 TickType_t xModifiableIdleTime;
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481 /* Make sure the SysTick reload value does not overflow the counter. */
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482 if( xExpectedIdleTime > xMaximumPossibleSuppressedTicks )
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484 xExpectedIdleTime = xMaximumPossibleSuppressedTicks;
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487 /* Stop the SysTick momentarily. The time the SysTick is stopped for
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488 is accounted for as best it can be, but using the tickless mode will
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489 inevitably result in some tiny drift of the time maintained by the
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490 kernel with respect to calendar time. */
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491 portNVIC_SYSTICK_CTRL_REG &= ~portNVIC_SYSTICK_ENABLE_BIT;
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493 /* Calculate the reload value required to wait xExpectedIdleTime
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494 tick periods. -1 is used because this code will execute part way
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495 through one of the tick periods. */
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496 ulReloadValue = portNVIC_SYSTICK_CURRENT_VALUE_REG + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) );
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497 if( ulReloadValue > ulStoppedTimerCompensation )
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499 ulReloadValue -= ulStoppedTimerCompensation;
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502 /* Enter a critical section but don't use the taskENTER_CRITICAL()
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503 method as that will mask interrupts that should exit sleep mode. */
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504 __asm volatile( "cpsid i" );
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505 __asm volatile( "dsb" );
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506 __asm volatile( "isb" );
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508 /* If a context switch is pending or a task is waiting for the scheduler
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509 to be unsuspended then abandon the low power entry. */
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510 if( eTaskConfirmSleepModeStatus() == eAbortSleep )
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512 /* Restart from whatever is left in the count register to complete
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513 this tick period. */
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514 portNVIC_SYSTICK_LOAD_REG = portNVIC_SYSTICK_CURRENT_VALUE_REG;
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516 /* Restart SysTick. */
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517 portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
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519 /* Reset the reload register to the value required for normal tick
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521 portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
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523 /* Re-enable interrupts - see comments above the cpsid instruction()
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525 __asm volatile( "cpsie i" );
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529 /* Set the new reload value. */
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530 portNVIC_SYSTICK_LOAD_REG = ulReloadValue;
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532 /* Clear the SysTick count flag and set the count value back to
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534 portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
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536 /* Restart SysTick. */
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537 portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
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539 /* Sleep until something happens. configPRE_SLEEP_PROCESSING() can
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540 set its parameter to 0 to indicate that its implementation contains
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541 its own wait for interrupt or wait for event instruction, and so wfi
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542 should not be executed again. However, the original expected idle
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543 time variable must remain unmodified, so a copy is taken. */
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544 xModifiableIdleTime = xExpectedIdleTime;
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545 configPRE_SLEEP_PROCESSING( xModifiableIdleTime );
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546 if( xModifiableIdleTime > 0 )
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548 __asm volatile( "dsb" );
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549 __asm volatile( "wfi" );
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550 __asm volatile( "isb" );
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552 configPOST_SLEEP_PROCESSING( xExpectedIdleTime );
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554 /* Re-enable interrupts - see comments above the cpsid instruction()
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556 __asm volatile( "cpsie i" );
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558 /* Disable the SysTick clock without reading the
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559 portNVIC_SYSTICK_CTRL_REG register to ensure the
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560 portNVIC_SYSTICK_COUNT_FLAG_BIT is not cleared if it is set. */
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561 portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT );
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563 /* Determine if the SysTick clock has already counted to zero and
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564 been set back to the current reload value (the reload back being
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565 correct for the entire expected idle time) or if the SysTick is yet
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566 to count to zero (in which case an interrupt other than the SysTick
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567 must have brought the system out of sleep mode). */
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568 if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 )
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570 uint32_t ulCalculatedLoadValue;
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572 /* The tick interrupt has already executed, and the SysTick
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573 count reloaded with ulReloadValue. Reset the
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574 portNVIC_SYSTICK_LOAD_REG with whatever remains of this tick
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576 ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ) - ( ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG );
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578 /* Don't allow a tiny value, or values that have somehow
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579 underflowed because the post sleep hook did something
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580 that took too long. */
\r
581 if( ( ulCalculatedLoadValue < ulStoppedTimerCompensation ) || ( ulCalculatedLoadValue > ulTimerCountsForOneTick ) )
\r
583 ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL );
\r
586 portNVIC_SYSTICK_LOAD_REG = ulCalculatedLoadValue;
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588 /* The tick interrupt handler will already have pended the tick
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589 processing in the kernel. As the pending tick will be
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590 processed as soon as this function exits, the tick value
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591 maintained by the tick is stepped forward by one less than the
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592 time spent waiting. */
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593 ulCompleteTickPeriods = xExpectedIdleTime - 1UL;
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597 /* Something other than the tick interrupt ended the sleep.
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598 Work out how long the sleep lasted rounded to complete tick
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599 periods (not the ulReload value which accounted for part
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601 ulCompletedSysTickDecrements = ( xExpectedIdleTime * ulTimerCountsForOneTick ) - portNVIC_SYSTICK_CURRENT_VALUE_REG;
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603 /* How many complete tick periods passed while the processor
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605 ulCompleteTickPeriods = ulCompletedSysTickDecrements / ulTimerCountsForOneTick;
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607 /* The reload value is set to whatever fraction of a single tick
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609 portNVIC_SYSTICK_LOAD_REG = ( ( ulCompleteTickPeriods + 1UL ) * ulTimerCountsForOneTick ) - ulCompletedSysTickDecrements;
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612 /* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG
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613 again, then set portNVIC_SYSTICK_LOAD_REG back to its standard
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614 value. The critical section is used to ensure the tick interrupt
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615 can only execute once in the case that the reload register is near
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617 portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
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618 portENTER_CRITICAL();
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620 portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
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621 vTaskStepTick( ulCompleteTickPeriods );
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622 portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
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624 portEXIT_CRITICAL();
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628 #endif /* #if configUSE_TICKLESS_IDLE */
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629 /*-----------------------------------------------------------*/
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632 * Setup the systick timer to generate the tick interrupts at the required
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635 __attribute__(( weak )) void vPortSetupTimerInterrupt( void )
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637 /* Calculate the constants required to configure the tick interrupt. */
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638 #if configUSE_TICKLESS_IDLE == 1
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640 ulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ );
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641 xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick;
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642 ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ );
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644 #endif /* configUSE_TICKLESS_IDLE */
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646 /* Stop and clear the SysTick. */
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647 portNVIC_SYSTICK_CTRL_REG = 0UL;
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648 portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
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650 /* Configure SysTick to interrupt at the requested rate. */
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651 portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;
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652 portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT );
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654 /*-----------------------------------------------------------*/
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656 #if( configASSERT_DEFINED == 1 )
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658 void vPortValidateInterruptPriority( void )
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660 uint32_t ulCurrentInterrupt;
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661 uint8_t ucCurrentPriority;
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663 /* Obtain the number of the currently executing interrupt. */
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664 __asm volatile( "mrs %0, ipsr" : "=r"( ulCurrentInterrupt ) );
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666 /* Is the interrupt number a user defined interrupt? */
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667 if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER )
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669 /* Look up the interrupt's priority. */
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670 ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ];
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672 /* The following assertion will fail if a service routine (ISR) for
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673 an interrupt that has been assigned a priority above
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674 configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API
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675 function. ISR safe FreeRTOS API functions must *only* be called
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676 from interrupts that have been assigned a priority at or below
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677 configMAX_SYSCALL_INTERRUPT_PRIORITY.
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679 Numerically low interrupt priority numbers represent logically high
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680 interrupt priorities, therefore the priority of the interrupt must
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681 be set to a value equal to or numerically *higher* than
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682 configMAX_SYSCALL_INTERRUPT_PRIORITY.
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684 Interrupts that use the FreeRTOS API must not be left at their
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685 default priority of zero as that is the highest possible priority,
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686 which is guaranteed to be above configMAX_SYSCALL_INTERRUPT_PRIORITY,
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687 and therefore also guaranteed to be invalid.
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689 FreeRTOS maintains separate thread and ISR API functions to ensure
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690 interrupt entry is as fast and simple as possible.
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692 The following links provide detailed information:
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693 http://www.freertos.org/RTOS-Cortex-M3-M4.html
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694 http://www.freertos.org/FAQHelp.html */
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695 configASSERT( ucCurrentPriority >= ucMaxSysCallPriority );
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698 /* Priority grouping: The interrupt controller (NVIC) allows the bits
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699 that define each interrupt's priority to be split between bits that
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700 define the interrupt's pre-emption priority bits and bits that define
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701 the interrupt's sub-priority. For simplicity all bits must be defined
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702 to be pre-emption priority bits. The following assertion will fail if
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703 this is not the case (if some bits represent a sub-priority).
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705 If the application only uses CMSIS libraries for interrupt
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706 configuration then the correct setting can be achieved on all Cortex-M
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707 devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the
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708 scheduler. Note however that some vendor specific peripheral libraries
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709 assume a non-zero priority group setting, in which cases using a value
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710 of zero will result in unpredicable behaviour. */
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711 configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue );
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714 #endif /* configASSERT_DEFINED */
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projects / freertos / blob